1 //===-- ARM_DWARF_Registers.cpp ---------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARM_DWARF_Registers.h"
16 using namespace lldb_private;
18 const char *GetARMDWARFRegisterName(unsigned reg_num) {
138 // Intel wireless MMX general purpose registers 0 - 7
139 // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
157 // Intel wireless MMX data registers 0 - 15
249 // Intel wireless MMX control register in co-processor 0 - 7
333 // NEON 128-bit vector registers (overlays the d registers)
370 bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo ®_info) {
371 ::memset(®_info, 0, sizeof(RegisterInfo));
372 ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
374 if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
375 reg_info.byte_size = 16;
376 reg_info.format = eFormatVectorOfUInt8;
377 reg_info.encoding = eEncodingVector;
380 if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
381 reg_info.byte_size = 8;
382 reg_info.format = eFormatFloat;
383 reg_info.encoding = eEncodingIEEE754;
384 } else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
385 reg_info.byte_size = 4;
386 reg_info.format = eFormatFloat;
387 reg_info.encoding = eEncodingIEEE754;
388 } else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
389 reg_info.byte_size = 12;
390 reg_info.format = eFormatFloat;
391 reg_info.encoding = eEncodingIEEE754;
393 reg_info.byte_size = 4;
394 reg_info.format = eFormatHex;
395 reg_info.encoding = eEncodingUint;
398 reg_info.kinds[eRegisterKindDWARF] = reg_num;
402 reg_info.name = "r0";
405 reg_info.name = "r1";
408 reg_info.name = "r2";
411 reg_info.name = "r3";
414 reg_info.name = "r4";
417 reg_info.name = "r5";
420 reg_info.name = "r6";
423 reg_info.name = "r7";
424 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
427 reg_info.name = "r8";
430 reg_info.name = "r9";
433 reg_info.name = "r10";
436 reg_info.name = "r11";
439 reg_info.name = "r12";
442 reg_info.name = "sp";
443 reg_info.alt_name = "r13";
444 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
447 reg_info.name = "lr";
448 reg_info.alt_name = "r14";
449 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
452 reg_info.name = "pc";
453 reg_info.alt_name = "r15";
454 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
457 reg_info.name = "cpsr";
458 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
462 reg_info.name = "s0";
465 reg_info.name = "s1";
468 reg_info.name = "s2";
471 reg_info.name = "s3";
474 reg_info.name = "s4";
477 reg_info.name = "s5";
480 reg_info.name = "s6";
483 reg_info.name = "s7";
486 reg_info.name = "s8";
489 reg_info.name = "s9";
492 reg_info.name = "s10";
495 reg_info.name = "s11";
498 reg_info.name = "s12";
501 reg_info.name = "s13";
504 reg_info.name = "s14";
507 reg_info.name = "s15";
510 reg_info.name = "s16";
513 reg_info.name = "s17";
516 reg_info.name = "s18";
519 reg_info.name = "s19";
522 reg_info.name = "s20";
525 reg_info.name = "s21";
528 reg_info.name = "s22";
531 reg_info.name = "s23";
534 reg_info.name = "s24";
537 reg_info.name = "s25";
540 reg_info.name = "s26";
543 reg_info.name = "s27";
546 reg_info.name = "s28";
549 reg_info.name = "s29";
552 reg_info.name = "s30";
555 reg_info.name = "s31";
560 reg_info.name = "f0";
563 reg_info.name = "f1";
566 reg_info.name = "f2";
569 reg_info.name = "f3";
572 reg_info.name = "f4";
575 reg_info.name = "f5";
578 reg_info.name = "f6";
581 reg_info.name = "f7";
584 // Intel wireless MMX general purpose registers 0 - 7
585 // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
587 reg_info.name = "wCGR0/ACC0";
590 reg_info.name = "wCGR1/ACC1";
593 reg_info.name = "wCGR2/ACC2";
596 reg_info.name = "wCGR3/ACC3";
599 reg_info.name = "wCGR4/ACC4";
602 reg_info.name = "wCGR5/ACC5";
605 reg_info.name = "wCGR6/ACC6";
608 reg_info.name = "wCGR7/ACC7";
611 // Intel wireless MMX data registers 0 - 15
613 reg_info.name = "wR0";
616 reg_info.name = "wR1";
619 reg_info.name = "wR2";
622 reg_info.name = "wR3";
625 reg_info.name = "wR4";
628 reg_info.name = "wR5";
631 reg_info.name = "wR6";
634 reg_info.name = "wR7";
637 reg_info.name = "wR8";
640 reg_info.name = "wR9";
643 reg_info.name = "wR10";
646 reg_info.name = "wR11";
649 reg_info.name = "wR12";
652 reg_info.name = "wR13";
655 reg_info.name = "wR14";
658 reg_info.name = "wR15";
662 reg_info.name = "spsr";
665 reg_info.name = "spsr_fiq";
668 reg_info.name = "spsr_irq";
671 reg_info.name = "spsr_abt";
674 reg_info.name = "spsr_und";
677 reg_info.name = "spsr_svc";
681 reg_info.name = "r8_usr";
684 reg_info.name = "r9_usr";
687 reg_info.name = "r10_usr";
690 reg_info.name = "r11_usr";
693 reg_info.name = "r12_usr";
696 reg_info.name = "r13_usr";
699 reg_info.name = "r14_usr";
702 reg_info.name = "r8_fiq";
705 reg_info.name = "r9_fiq";
708 reg_info.name = "r10_fiq";
711 reg_info.name = "r11_fiq";
714 reg_info.name = "r12_fiq";
717 reg_info.name = "r13_fiq";
720 reg_info.name = "r14_fiq";
723 reg_info.name = "r13_irq";
726 reg_info.name = "r14_irq";
729 reg_info.name = "r13_abt";
732 reg_info.name = "r14_abt";
735 reg_info.name = "r13_und";
738 reg_info.name = "r14_und";
741 reg_info.name = "r13_svc";
744 reg_info.name = "r14_svc";
747 // Intel wireless MMX control register in co-processor 0 - 7
749 reg_info.name = "wC0";
752 reg_info.name = "wC1";
755 reg_info.name = "wC2";
758 reg_info.name = "wC3";
761 reg_info.name = "wC4";
764 reg_info.name = "wC5";
767 reg_info.name = "wC6";
770 reg_info.name = "wC7";
775 reg_info.name = "d0";
778 reg_info.name = "d1";
781 reg_info.name = "d2";
784 reg_info.name = "d3";
787 reg_info.name = "d4";
790 reg_info.name = "d5";
793 reg_info.name = "d6";
796 reg_info.name = "d7";
799 reg_info.name = "d8";
802 reg_info.name = "d9";
805 reg_info.name = "d10";
808 reg_info.name = "d11";
811 reg_info.name = "d12";
814 reg_info.name = "d13";
817 reg_info.name = "d14";
820 reg_info.name = "d15";
823 reg_info.name = "d16";
826 reg_info.name = "d17";
829 reg_info.name = "d18";
832 reg_info.name = "d19";
835 reg_info.name = "d20";
838 reg_info.name = "d21";
841 reg_info.name = "d22";
844 reg_info.name = "d23";
847 reg_info.name = "d24";
850 reg_info.name = "d25";
853 reg_info.name = "d26";
856 reg_info.name = "d27";
859 reg_info.name = "d28";
862 reg_info.name = "d29";
865 reg_info.name = "d30";
868 reg_info.name = "d31";
871 // NEON 128-bit vector registers (overlays the d registers)
873 reg_info.name = "q0";
876 reg_info.name = "q1";
879 reg_info.name = "q2";
882 reg_info.name = "q3";
885 reg_info.name = "q4";
888 reg_info.name = "q5";
891 reg_info.name = "q6";
894 reg_info.name = "q7";
897 reg_info.name = "q8";
900 reg_info.name = "q9";
903 reg_info.name = "q10";
906 reg_info.name = "q11";
909 reg_info.name = "q12";
912 reg_info.name = "q13";
915 reg_info.name = "q14";
918 reg_info.name = "q15";