1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file defines a class for holding ownership of various simulated
12 /// hardware units. A Context also provides a utility routine for constructing
13 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
16 //===----------------------------------------------------------------------===//
19 #include "DispatchStage.h"
20 #include "ExecuteStage.h"
21 #include "FetchStage.h"
22 #include "RegisterFile.h"
23 #include "RetireControlUnit.h"
24 #include "RetireStage.h"
25 #include "Scheduler.h"
31 std::unique_ptr<Pipeline>
32 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
34 const MCSchedModel &SM = STI.getSchedModel();
36 // Create the hardware units defining the backend.
37 auto RCU = llvm::make_unique<RetireControlUnit>(SM);
38 auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
39 auto HWS = llvm::make_unique<Scheduler>(
40 SM, Opts.LoadQueueSize, Opts.StoreQueueSize, Opts.AssumeNoAlias);
42 // Create the pipeline and its stages.
43 auto P = llvm::make_unique<Pipeline>();
44 auto F = llvm::make_unique<FetchStage>(IB, SrcMgr);
45 auto D = llvm::make_unique<DispatchStage>(
46 STI, MRI, Opts.RegisterFileSize, Opts.DispatchWidth, *RCU, *PRF, *HWS);
47 auto R = llvm::make_unique<RetireStage>(*RCU, *PRF);
48 auto E = llvm::make_unique<ExecuteStage>(*RCU, *HWS);
50 // Add the hardware to the context.
51 addHardwareUnit(std::move(RCU));
52 addHardwareUnit(std::move(PRF));
53 addHardwareUnit(std::move(HWS));
55 // Build the pipeline.
56 P->appendStage(std::move(F));
57 P->appendStage(std::move(D));
58 P->appendStage(std::move(R));
59 P->appendStage(std::move(E));