1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "SubtargetFeatureInfo.h"
102 #include "llvm/ADT/CachedHashString.h"
103 #include "llvm/ADT/PointerUnion.h"
104 #include "llvm/ADT/STLExtras.h"
105 #include "llvm/ADT/SmallPtrSet.h"
106 #include "llvm/ADT/SmallVector.h"
107 #include "llvm/ADT/StringExtras.h"
108 #include "llvm/Support/CommandLine.h"
109 #include "llvm/Support/Debug.h"
110 #include "llvm/Support/ErrorHandling.h"
111 #include "llvm/TableGen/Error.h"
112 #include "llvm/TableGen/Record.h"
113 #include "llvm/TableGen/StringMatcher.h"
114 #include "llvm/TableGen/StringToOffsetTable.h"
115 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
122 using namespace llvm;
124 #define DEBUG_TYPE "asm-matcher-emitter"
126 cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
128 static cl::opt<std::string>
129 MatchPrefix("match-prefix", cl::init(""),
130 cl::desc("Only match instructions with the given prefix"),
131 cl::cat(AsmMatcherEmitterCat));
134 class AsmMatcherInfo;
136 // Register sets are used as keys in some second-order sets TableGen creates
137 // when generating its data structures. This means that the order of two
138 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
139 // can even affect compiler output (at least seen in diagnostics produced when
140 // all matches fail). So we use a type that sorts them consistently.
141 typedef std::set<Record*, LessRecordByID> RegisterSet;
143 class AsmMatcherEmitter {
144 RecordKeeper &Records;
146 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
148 void run(raw_ostream &o);
151 /// ClassInfo - Helper class for storing the information about a particular
152 /// class of operands which can be matched.
155 /// Invalid kind, for use as a sentinel value.
158 /// The class for a particular token.
161 /// The (first) register class, subsequent register classes are
162 /// RegisterClass0+1, and so on.
165 /// The (first) user defined class, subsequent user defined classes are
166 /// UserClass0+1, and so on.
170 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
171 /// N) for the Nth user defined class.
174 /// SuperClasses - The super classes of this class. Note that for simplicities
175 /// sake user operands only record their immediate super class, while register
176 /// operands include all superclasses.
177 std::vector<ClassInfo*> SuperClasses;
179 /// Name - The full class name, suitable for use in an enum.
182 /// ClassName - The unadorned generic name for this class (e.g., Token).
183 std::string ClassName;
185 /// ValueName - The name of the value this class represents; for a token this
186 /// is the literal token string, for an operand it is the TableGen class (or
187 /// empty if this is a derived class).
188 std::string ValueName;
190 /// PredicateMethod - The name of the operand method to test whether the
191 /// operand matches this class; this is not valid for Token or register kinds.
192 std::string PredicateMethod;
194 /// RenderMethod - The name of the operand method to add this operand to an
195 /// MCInst; this is not valid for Token or register kinds.
196 std::string RenderMethod;
198 /// ParserMethod - The name of the operand method to do a target specific
199 /// parsing on the operand.
200 std::string ParserMethod;
202 /// For register classes: the records for all the registers in this class.
203 RegisterSet Registers;
205 /// For custom match classes: the diagnostic kind for when the predicate fails.
206 std::string DiagnosticType;
208 /// Is this operand optional and not always required.
211 /// DefaultMethod - The name of the method that returns the default operand
212 /// for optional operand
213 std::string DefaultMethod;
216 /// isRegisterClass() - Check if this is a register class.
217 bool isRegisterClass() const {
218 return Kind >= RegisterClass0 && Kind < UserClass0;
221 /// isUserClass() - Check if this is a user defined class.
222 bool isUserClass() const {
223 return Kind >= UserClass0;
226 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
227 /// are related if they are in the same class hierarchy.
228 bool isRelatedTo(const ClassInfo &RHS) const {
229 // Tokens are only related to tokens.
230 if (Kind == Token || RHS.Kind == Token)
231 return Kind == Token && RHS.Kind == Token;
233 // Registers classes are only related to registers classes, and only if
234 // their intersection is non-empty.
235 if (isRegisterClass() || RHS.isRegisterClass()) {
236 if (!isRegisterClass() || !RHS.isRegisterClass())
240 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
241 std::set_intersection(Registers.begin(), Registers.end(),
242 RHS.Registers.begin(), RHS.Registers.end(),
243 II, LessRecordByID());
248 // Otherwise we have two users operands; they are related if they are in the
249 // same class hierarchy.
251 // FIXME: This is an oversimplification, they should only be related if they
252 // intersect, however we don't have that information.
253 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
254 const ClassInfo *Root = this;
255 while (!Root->SuperClasses.empty())
256 Root = Root->SuperClasses.front();
258 const ClassInfo *RHSRoot = &RHS;
259 while (!RHSRoot->SuperClasses.empty())
260 RHSRoot = RHSRoot->SuperClasses.front();
262 return Root == RHSRoot;
265 /// isSubsetOf - Test whether this class is a subset of \p RHS.
266 bool isSubsetOf(const ClassInfo &RHS) const {
267 // This is a subset of RHS if it is the same class...
271 // ... or if any of its super classes are a subset of RHS.
272 for (const ClassInfo *CI : SuperClasses)
273 if (CI->isSubsetOf(RHS))
279 int getTreeDepth() const {
281 const ClassInfo *Root = this;
282 while (!Root->SuperClasses.empty()) {
284 Root = Root->SuperClasses.front();
289 const ClassInfo *findRoot() const {
290 const ClassInfo *Root = this;
291 while (!Root->SuperClasses.empty())
292 Root = Root->SuperClasses.front();
296 /// Compare two classes. This does not produce a total ordering, but does
297 /// guarantee that subclasses are sorted before their parents, and that the
298 /// ordering is transitive.
299 bool operator<(const ClassInfo &RHS) const {
303 // First, enforce the ordering between the three different types of class.
304 // Tokens sort before registers, which sort before user classes.
306 if (RHS.Kind != Token)
308 assert(RHS.Kind == Token);
309 } else if (isRegisterClass()) {
310 if (RHS.Kind == Token)
312 else if (RHS.isUserClass())
314 assert(RHS.isRegisterClass());
315 } else if (isUserClass()) {
316 if (!RHS.isUserClass())
318 assert(RHS.isUserClass());
320 llvm_unreachable("Unknown ClassInfoKind");
323 if (Kind == Token || isUserClass()) {
324 // Related tokens and user classes get sorted by depth in the inheritence
325 // tree (so that subclasses are before their parents).
326 if (isRelatedTo(RHS)) {
327 if (getTreeDepth() > RHS.getTreeDepth())
329 if (getTreeDepth() < RHS.getTreeDepth())
332 // Unrelated tokens and user classes are ordered by the name of their
333 // root nodes, so that there is a consistent ordering between
334 // unconnected trees.
335 return findRoot()->ValueName < RHS.findRoot()->ValueName;
337 } else if (isRegisterClass()) {
338 // For register sets, sort by number of registers. This guarantees that
339 // a set will always sort before all of it's strict supersets.
340 if (Registers.size() != RHS.Registers.size())
341 return Registers.size() < RHS.Registers.size();
343 llvm_unreachable("Unknown ClassInfoKind");
346 // FIXME: We should be able to just return false here, as we only need a
347 // partial order (we use stable sorts, so this is deterministic) and the
348 // name of a class shouldn't be significant. However, some of the backends
349 // accidentally rely on this behaviour, so it will have to stay like this
350 // until they are fixed.
351 return ValueName < RHS.ValueName;
355 class AsmVariantInfo {
357 std::string RegisterPrefix;
358 std::string TokenizingCharacters;
359 std::string SeparatorCharacters;
360 std::string BreakCharacters;
365 /// MatchableInfo - Helper class for storing the necessary information for an
366 /// instruction or alias which is capable of being matched.
367 struct MatchableInfo {
369 /// Token - This is the token that the operand came from.
372 /// The unique class instance this operand should match.
375 /// The operand name this is, if anything.
378 /// The suboperand index within SrcOpName, or -1 for the entire operand.
381 /// Whether the token is "isolated", i.e., it is preceded and followed
383 bool IsIsolatedToken;
385 /// Register record if this token is singleton register.
386 Record *SingletonReg;
388 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
389 : Token(T), Class(nullptr), SubOpIdx(-1),
390 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
393 /// ResOperand - This represents a single operand in the result instruction
394 /// generated by the match. In cases (like addressing modes) where a single
395 /// assembler operand expands to multiple MCOperands, this represents the
396 /// single assembler operand, not the MCOperand.
399 /// RenderAsmOperand - This represents an operand result that is
400 /// generated by calling the render method on the assembly operand. The
401 /// corresponding AsmOperand is specified by AsmOperandNum.
404 /// TiedOperand - This represents a result operand that is a duplicate of
405 /// a previous result operand.
408 /// ImmOperand - This represents an immediate value that is dumped into
412 /// RegOperand - This represents a fixed register that is dumped in.
417 /// This is the operand # in the AsmOperands list that this should be
419 unsigned AsmOperandNum;
421 /// TiedOperandNum - This is the (earlier) result operand that should be
423 unsigned TiedOperandNum;
425 /// ImmVal - This is the immediate value added to the instruction.
428 /// Register - This is the register record.
432 /// MINumOperands - The number of MCInst operands populated by this
434 unsigned MINumOperands;
436 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
438 X.Kind = RenderAsmOperand;
439 X.AsmOperandNum = AsmOpNum;
440 X.MINumOperands = NumOperands;
444 static ResOperand getTiedOp(unsigned TiedOperandNum) {
446 X.Kind = TiedOperand;
447 X.TiedOperandNum = TiedOperandNum;
452 static ResOperand getImmOp(int64_t Val) {
460 static ResOperand getRegOp(Record *Reg) {
469 /// AsmVariantID - Target's assembly syntax variant no.
472 /// AsmString - The assembly string for this instruction (with variants
473 /// removed), e.g. "movsx $src, $dst".
474 std::string AsmString;
476 /// TheDef - This is the definition of the instruction or InstAlias that this
477 /// matchable came from.
478 Record *const TheDef;
480 /// DefRec - This is the definition that it came from.
481 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
483 const CodeGenInstruction *getResultInst() const {
484 if (DefRec.is<const CodeGenInstruction*>())
485 return DefRec.get<const CodeGenInstruction*>();
486 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
489 /// ResOperands - This is the operand list that should be built for the result
491 SmallVector<ResOperand, 8> ResOperands;
493 /// Mnemonic - This is the first token of the matched instruction, its
497 /// AsmOperands - The textual operands that this instruction matches,
498 /// annotated with a class and where in the OperandList they were defined.
499 /// This directly corresponds to the tokenized AsmString after the mnemonic is
501 SmallVector<AsmOperand, 8> AsmOperands;
503 /// Predicates - The required subtarget features to match this instruction.
504 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
506 /// ConversionFnKind - The enum value which is passed to the generated
507 /// convertToMCInst to convert parsed operands into an MCInst for this
509 std::string ConversionFnKind;
511 /// If this instruction is deprecated in some form.
514 /// If this is an alias, this is use to determine whether or not to using
515 /// the conversion function defined by the instruction's AsmMatchConverter
516 /// or to use the function generated by the alias.
517 bool UseInstAsmMatchConverter;
519 MatchableInfo(const CodeGenInstruction &CGI)
520 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
521 UseInstAsmMatchConverter(true) {
524 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
525 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
526 DefRec(Alias.release()),
527 UseInstAsmMatchConverter(
528 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
531 // Could remove this and the dtor if PointerUnion supported unique_ptr
532 // elements with a dynamic failure/assertion (like the one below) in the case
533 // where it was copied while being in an owning state.
534 MatchableInfo(const MatchableInfo &RHS)
535 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
536 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
537 Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
538 RequiredFeatures(RHS.RequiredFeatures),
539 ConversionFnKind(RHS.ConversionFnKind),
540 HasDeprecation(RHS.HasDeprecation),
541 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
542 assert(!DefRec.is<const CodeGenInstAlias *>());
546 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
549 // Two-operand aliases clone from the main matchable, but mark the second
550 // operand as a tied operand of the first for purposes of the assembler.
551 void formTwoOperandAlias(StringRef Constraint);
553 void initialize(const AsmMatcherInfo &Info,
554 SmallPtrSetImpl<Record*> &SingletonRegisters,
555 AsmVariantInfo const &Variant,
556 bool HasMnemonicFirst);
558 /// validate - Return true if this matchable is a valid thing to match against
559 /// and perform a bunch of validity checking.
560 bool validate(StringRef CommentDelimiter, bool Hack) const;
562 /// findAsmOperand - Find the AsmOperand with the specified name and
563 /// suboperand index.
564 int findAsmOperand(StringRef N, int SubOpIdx) const {
565 auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {
566 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
568 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
571 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
572 /// This does not check the suboperand index.
573 int findAsmOperandNamed(StringRef N) const {
574 auto I = find_if(AsmOperands,
575 [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
576 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
579 void buildInstructionResultOperands();
580 void buildAliasResultOperands();
582 /// operator< - Compare two matchables.
583 bool operator<(const MatchableInfo &RHS) const {
584 // The primary comparator is the instruction mnemonic.
585 if (int Cmp = Mnemonic.compare(RHS.Mnemonic))
588 if (AsmOperands.size() != RHS.AsmOperands.size())
589 return AsmOperands.size() < RHS.AsmOperands.size();
591 // Compare lexicographically by operand. The matcher validates that other
592 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
593 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
594 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
596 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
600 // Give matches that require more features higher precedence. This is useful
601 // because we cannot define AssemblerPredicates with the negation of
602 // processor features. For example, ARM v6 "nop" may be either a HINT or
603 // MOV. With v6, we want to match HINT. The assembler has no way to
604 // predicate MOV under "NoV6", but HINT will always match first because it
605 // requires V6 while MOV does not.
606 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
607 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
612 /// couldMatchAmbiguouslyWith - Check whether this matchable could
613 /// ambiguously match the same set of operands as \p RHS (without being a
614 /// strictly superior match).
615 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
616 // The primary comparator is the instruction mnemonic.
617 if (Mnemonic != RHS.Mnemonic)
620 // The number of operands is unambiguous.
621 if (AsmOperands.size() != RHS.AsmOperands.size())
624 // Otherwise, make sure the ordering of the two instructions is unambiguous
625 // by checking that either (a) a token or operand kind discriminates them,
626 // or (b) the ordering among equivalent kinds is consistent.
628 // Tokens and operand kinds are unambiguous (assuming a correct target
630 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
631 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
632 AsmOperands[i].Class->Kind == ClassInfo::Token)
633 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
634 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
637 // Otherwise, this operand could commute if all operands are equivalent, or
638 // there is a pair of operands that compare less than and a pair that
639 // compare greater than.
640 bool HasLT = false, HasGT = false;
641 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
642 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
644 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
648 return HasLT == HasGT;
654 void tokenizeAsmString(AsmMatcherInfo const &Info,
655 AsmVariantInfo const &Variant);
656 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
659 struct OperandMatchEntry {
660 unsigned OperandMask;
661 const MatchableInfo* MI;
664 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
667 X.OperandMask = opMask;
674 class AsmMatcherInfo {
677 RecordKeeper &Records;
679 /// The tablegen AsmParser record.
682 /// Target - The target information.
683 CodeGenTarget &Target;
685 /// The classes which are needed for matching.
686 std::forward_list<ClassInfo> Classes;
688 /// The information on the matchables to match.
689 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
691 /// Info for custom matching operands by user defined methods.
692 std::vector<OperandMatchEntry> OperandMatchInfo;
694 /// Map of Register records to their class information.
695 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
696 RegisterClassesTy RegisterClasses;
698 /// Map of Predicate records to their subtarget information.
699 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
701 /// Map of AsmOperandClass records to their class information.
702 std::map<Record*, ClassInfo*> AsmOperandClasses;
705 /// Map of token to class information which has already been constructed.
706 std::map<std::string, ClassInfo*> TokenClasses;
708 /// Map of RegisterClass records to their class information.
709 std::map<Record*, ClassInfo*> RegisterClassClasses;
712 /// getTokenClass - Lookup or create the class for the given token.
713 ClassInfo *getTokenClass(StringRef Token);
715 /// getOperandClass - Lookup or create the class for the given operand.
716 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
718 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
720 /// buildRegisterClasses - Build the ClassInfo* instances for register
722 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
724 /// buildOperandClasses - Build the ClassInfo* instances for user defined
726 void buildOperandClasses();
728 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
730 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
731 MatchableInfo::AsmOperand &Op);
734 AsmMatcherInfo(Record *AsmParser,
735 CodeGenTarget &Target,
736 RecordKeeper &Records);
738 /// Construct the various tables used during matching.
741 /// buildOperandMatchInfo - Build the necessary information to handle user
742 /// defined operand parsing methods.
743 void buildOperandMatchInfo();
745 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
747 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
748 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
749 const auto &I = SubtargetFeatures.find(Def);
750 return I == SubtargetFeatures.end() ? nullptr : &I->second;
753 RecordKeeper &getRecords() const {
757 bool hasOptionalOperands() const {
758 return find_if(Classes, [](const ClassInfo &Class) {
759 return Class.IsOptional;
764 } // end anonymous namespace
766 void MatchableInfo::dump() const {
767 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
769 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
770 const AsmOperand &Op = AsmOperands[i];
771 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
772 errs() << '\"' << Op.Token << "\"\n";
776 static std::pair<StringRef, StringRef>
777 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
778 // Split via the '='.
779 std::pair<StringRef, StringRef> Ops = S.split('=');
780 if (Ops.second == "")
781 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
782 // Trim whitespace and the leading '$' on the operand names.
783 size_t start = Ops.first.find_first_of('$');
784 if (start == std::string::npos)
785 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
786 Ops.first = Ops.first.slice(start + 1, std::string::npos);
787 size_t end = Ops.first.find_last_of(" \t");
788 Ops.first = Ops.first.slice(0, end);
789 // Now the second operand.
790 start = Ops.second.find_first_of('$');
791 if (start == std::string::npos)
792 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
793 Ops.second = Ops.second.slice(start + 1, std::string::npos);
794 end = Ops.second.find_last_of(" \t");
795 Ops.first = Ops.first.slice(0, end);
799 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
800 // Figure out which operands are aliased and mark them as tied.
801 std::pair<StringRef, StringRef> Ops =
802 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
804 // Find the AsmOperands that refer to the operands we're aliasing.
805 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
806 int DstAsmOperand = findAsmOperandNamed(Ops.second);
807 if (SrcAsmOperand == -1)
808 PrintFatalError(TheDef->getLoc(),
809 "unknown source two-operand alias operand '" + Ops.first +
811 if (DstAsmOperand == -1)
812 PrintFatalError(TheDef->getLoc(),
813 "unknown destination two-operand alias operand '" +
816 // Find the ResOperand that refers to the operand we're aliasing away
817 // and update it to refer to the combined operand instead.
818 for (ResOperand &Op : ResOperands) {
819 if (Op.Kind == ResOperand::RenderAsmOperand &&
820 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
821 Op.AsmOperandNum = DstAsmOperand;
825 // Remove the AsmOperand for the alias operand.
826 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
827 // Adjust the ResOperand references to any AsmOperands that followed
828 // the one we just deleted.
829 for (ResOperand &Op : ResOperands) {
832 // Nothing to do for operands that don't reference AsmOperands.
834 case ResOperand::RenderAsmOperand:
835 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
838 case ResOperand::TiedOperand:
839 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
846 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
847 /// if present, from specified token.
849 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
850 const AsmMatcherInfo &Info,
851 StringRef RegisterPrefix) {
852 StringRef Tok = Op.Token;
854 // If this token is not an isolated token, i.e., it isn't separated from
855 // other tokens (e.g. with whitespace), don't interpret it as a register name.
856 if (!Op.IsIsolatedToken)
859 if (RegisterPrefix.empty()) {
860 std::string LoweredTok = Tok.lower();
861 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
862 Op.SingletonReg = Reg->TheDef;
866 if (!Tok.startswith(RegisterPrefix))
869 StringRef RegName = Tok.substr(RegisterPrefix.size());
870 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
871 Op.SingletonReg = Reg->TheDef;
873 // If there is no register prefix (i.e. "%" in "%eax"), then this may
874 // be some random non-register token, just ignore it.
877 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
878 SmallPtrSetImpl<Record*> &SingletonRegisters,
879 AsmVariantInfo const &Variant,
880 bool HasMnemonicFirst) {
881 AsmVariantID = Variant.AsmVariantNo;
883 CodeGenInstruction::FlattenAsmStringVariants(AsmString,
884 Variant.AsmVariantNo);
886 tokenizeAsmString(Info, Variant);
888 // The first token of the instruction is the mnemonic, which must be a
889 // simple string, not a $foo variable or a singleton register.
890 if (AsmOperands.empty())
891 PrintFatalError(TheDef->getLoc(),
892 "Instruction '" + TheDef->getName() + "' has no tokens");
894 assert(!AsmOperands[0].Token.empty());
895 if (HasMnemonicFirst) {
896 Mnemonic = AsmOperands[0].Token;
897 if (Mnemonic[0] == '$')
898 PrintFatalError(TheDef->getLoc(),
899 "Invalid instruction mnemonic '" + Mnemonic + "'!");
901 // Remove the first operand, it is tracked in the mnemonic field.
902 AsmOperands.erase(AsmOperands.begin());
903 } else if (AsmOperands[0].Token[0] != '$')
904 Mnemonic = AsmOperands[0].Token;
906 // Compute the require features.
907 for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
908 if (const SubtargetFeatureInfo *Feature =
909 Info.getSubtargetFeature(Predicate))
910 RequiredFeatures.push_back(Feature);
912 // Collect singleton registers, if used.
913 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
914 extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
915 if (Record *Reg = Op.SingletonReg)
916 SingletonRegisters.insert(Reg);
919 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
921 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
924 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
927 /// Append an AsmOperand for the given substring of AsmString.
928 void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
929 AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));
932 /// tokenizeAsmString - Tokenize a simplified assembly string.
933 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
934 AsmVariantInfo const &Variant) {
935 StringRef String = AsmString;
938 bool IsIsolatedToken = true;
939 for (size_t i = 0, e = String.size(); i != e; ++i) {
940 char Char = String[i];
941 if (Variant.BreakCharacters.find(Char) != std::string::npos) {
943 addAsmOperand(String.slice(Prev, i), false);
945 IsIsolatedToken = false;
950 if (Variant.TokenizingCharacters.find(Char) != std::string::npos) {
952 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
954 IsIsolatedToken = false;
956 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
958 IsIsolatedToken = true;
961 if (Variant.SeparatorCharacters.find(Char) != std::string::npos) {
963 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
967 IsIsolatedToken = true;
974 addAsmOperand(String.slice(Prev, i), false);
976 IsIsolatedToken = false;
979 assert(i != String.size() && "Invalid quoted character");
980 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
982 IsIsolatedToken = false;
987 addAsmOperand(String.slice(Prev, i), false);
989 IsIsolatedToken = false;
992 // If this isn't "${", start new identifier looking like "$xxx"
993 if (i + 1 == String.size() || String[i + 1] != '{') {
998 size_t EndPos = String.find('}', i);
999 assert(EndPos != StringRef::npos &&
1000 "Missing brace in operand reference!");
1001 addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
1004 IsIsolatedToken = false;
1013 if (InTok && Prev != String.size())
1014 addAsmOperand(String.substr(Prev), IsIsolatedToken);
1017 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
1018 // Reject matchables with no .s string.
1019 if (AsmString.empty())
1020 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
1022 // Reject any matchables with a newline in them, they should be marked
1023 // isCodeGenOnly if they are pseudo instructions.
1024 if (AsmString.find('\n') != std::string::npos)
1025 PrintFatalError(TheDef->getLoc(),
1026 "multiline instruction is not valid for the asmparser, "
1027 "mark it isCodeGenOnly");
1029 // Remove comments from the asm string. We know that the asmstring only
1031 if (!CommentDelimiter.empty() &&
1032 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
1033 PrintFatalError(TheDef->getLoc(),
1034 "asmstring for instruction has comment character in it, "
1035 "mark it isCodeGenOnly");
1037 // Reject matchables with operand modifiers, these aren't something we can
1038 // handle, the target should be refactored to use operands instead of
1041 // Also, check for instructions which reference the operand multiple times;
1042 // this implies a constraint we would not honor.
1043 std::set<std::string> OperandNames;
1044 for (const AsmOperand &Op : AsmOperands) {
1045 StringRef Tok = Op.Token;
1046 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
1047 PrintFatalError(TheDef->getLoc(),
1048 "matchable with operand modifier '" + Tok +
1049 "' not supported by asm matcher. Mark isCodeGenOnly!");
1051 // Verify that any operand is only mentioned once.
1052 // We reject aliases and ignore instructions for now.
1053 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1055 PrintFatalError(TheDef->getLoc(),
1056 "ERROR: matchable with tied operand '" + Tok +
1057 "' can never be matched!");
1058 // FIXME: Should reject these. The ARM backend hits this with $lane in a
1059 // bunch of instructions. It is unclear what the right answer is.
1061 errs() << "warning: '" << TheDef->getName() << "': "
1062 << "ignoring instruction with tied operand '"
1072 static std::string getEnumNameForToken(StringRef Str) {
1075 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1077 case '*': Res += "_STAR_"; break;
1078 case '%': Res += "_PCT_"; break;
1079 case ':': Res += "_COLON_"; break;
1080 case '!': Res += "_EXCLAIM_"; break;
1081 case '.': Res += "_DOT_"; break;
1082 case '<': Res += "_LT_"; break;
1083 case '>': Res += "_GT_"; break;
1084 case '-': Res += "_MINUS_"; break;
1086 if ((*it >= 'A' && *it <= 'Z') ||
1087 (*it >= 'a' && *it <= 'z') ||
1088 (*it >= '0' && *it <= '9'))
1091 Res += "_" + utostr((unsigned) *it) + "_";
1098 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1099 ClassInfo *&Entry = TokenClasses[Token];
1102 Classes.emplace_front();
1103 Entry = &Classes.front();
1104 Entry->Kind = ClassInfo::Token;
1105 Entry->ClassName = "Token";
1106 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1107 Entry->ValueName = Token;
1108 Entry->PredicateMethod = "<invalid>";
1109 Entry->RenderMethod = "<invalid>";
1110 Entry->ParserMethod = "";
1111 Entry->DiagnosticType = "";
1112 Entry->IsOptional = false;
1113 Entry->DefaultMethod = "<invalid>";
1120 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1122 Record *Rec = OI.Rec;
1124 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1125 return getOperandClass(Rec, SubOpIdx);
1129 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1130 if (Rec->isSubClassOf("RegisterOperand")) {
1131 // RegisterOperand may have an associated ParserMatchClass. If it does,
1132 // use it, else just fall back to the underlying register class.
1133 const RecordVal *R = Rec->getValue("ParserMatchClass");
1134 if (!R || !R->getValue())
1135 PrintFatalError("Record `" + Rec->getName() +
1136 "' does not have a ParserMatchClass!\n");
1138 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1139 Record *MatchClass = DI->getDef();
1140 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1144 // No custom match class. Just use the register class.
1145 Record *ClassRec = Rec->getValueAsDef("RegClass");
1147 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1148 "' has no associated register class!\n");
1149 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1151 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1154 if (Rec->isSubClassOf("RegisterClass")) {
1155 if (ClassInfo *CI = RegisterClassClasses[Rec])
1157 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1160 if (!Rec->isSubClassOf("Operand"))
1161 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1162 "' does not derive from class Operand!\n");
1163 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1164 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1167 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1170 struct LessRegisterSet {
1171 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1172 // std::set<T> defines its own compariso "operator<", but it
1173 // performs a lexicographical comparison by T's innate comparison
1174 // for some reason. We don't want non-deterministic pointer
1175 // comparisons so use this instead.
1176 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1177 RHS.begin(), RHS.end(),
1182 void AsmMatcherInfo::
1183 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1184 const auto &Registers = Target.getRegBank().getRegisters();
1185 auto &RegClassList = Target.getRegBank().getRegClasses();
1187 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1189 // The register sets used for matching.
1190 RegisterSetSet RegisterSets;
1192 // Gather the defined sets.
1193 for (const CodeGenRegisterClass &RC : RegClassList)
1194 RegisterSets.insert(
1195 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1197 // Add any required singleton sets.
1198 for (Record *Rec : SingletonRegisters) {
1199 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1202 // Introduce derived sets where necessary (when a register does not determine
1203 // a unique register set class), and build the mapping of registers to the set
1204 // they should classify to.
1205 std::map<Record*, RegisterSet> RegisterMap;
1206 for (const CodeGenRegister &CGR : Registers) {
1207 // Compute the intersection of all sets containing this register.
1208 RegisterSet ContainingSet;
1210 for (const RegisterSet &RS : RegisterSets) {
1211 if (!RS.count(CGR.TheDef))
1214 if (ContainingSet.empty()) {
1220 std::swap(Tmp, ContainingSet);
1221 std::insert_iterator<RegisterSet> II(ContainingSet,
1222 ContainingSet.begin());
1223 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1227 if (!ContainingSet.empty()) {
1228 RegisterSets.insert(ContainingSet);
1229 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1233 // Construct the register classes.
1234 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1236 for (const RegisterSet &RS : RegisterSets) {
1237 Classes.emplace_front();
1238 ClassInfo *CI = &Classes.front();
1239 CI->Kind = ClassInfo::RegisterClass0 + Index;
1240 CI->ClassName = "Reg" + utostr(Index);
1241 CI->Name = "MCK_Reg" + utostr(Index);
1243 CI->PredicateMethod = ""; // unused
1244 CI->RenderMethod = "addRegOperands";
1246 // FIXME: diagnostic type.
1247 CI->DiagnosticType = "";
1248 CI->IsOptional = false;
1249 CI->DefaultMethod = ""; // unused
1250 RegisterSetClasses.insert(std::make_pair(RS, CI));
1254 // Find the superclasses; we could compute only the subgroup lattice edges,
1255 // but there isn't really a point.
1256 for (const RegisterSet &RS : RegisterSets) {
1257 ClassInfo *CI = RegisterSetClasses[RS];
1258 for (const RegisterSet &RS2 : RegisterSets)
1260 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1262 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1265 // Name the register classes which correspond to a user defined RegisterClass.
1266 for (const CodeGenRegisterClass &RC : RegClassList) {
1267 // Def will be NULL for non-user defined register classes.
1268 Record *Def = RC.getDef();
1271 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1272 RC.getOrder().end())];
1273 if (CI->ValueName.empty()) {
1274 CI->ClassName = RC.getName();
1275 CI->Name = "MCK_" + RC.getName();
1276 CI->ValueName = RC.getName();
1278 CI->ValueName = CI->ValueName + "," + RC.getName();
1280 RegisterClassClasses.insert(std::make_pair(Def, CI));
1283 // Populate the map for individual registers.
1284 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1285 ie = RegisterMap.end(); it != ie; ++it)
1286 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1288 // Name the register classes which correspond to singleton registers.
1289 for (Record *Rec : SingletonRegisters) {
1290 ClassInfo *CI = RegisterClasses[Rec];
1291 assert(CI && "Missing singleton register class info!");
1293 if (CI->ValueName.empty()) {
1294 CI->ClassName = Rec->getName();
1295 CI->Name = "MCK_" + Rec->getName().str();
1296 CI->ValueName = Rec->getName();
1298 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1302 void AsmMatcherInfo::buildOperandClasses() {
1303 std::vector<Record*> AsmOperands =
1304 Records.getAllDerivedDefinitions("AsmOperandClass");
1306 // Pre-populate AsmOperandClasses map.
1307 for (Record *Rec : AsmOperands) {
1308 Classes.emplace_front();
1309 AsmOperandClasses[Rec] = &Classes.front();
1313 for (Record *Rec : AsmOperands) {
1314 ClassInfo *CI = AsmOperandClasses[Rec];
1315 CI->Kind = ClassInfo::UserClass0 + Index;
1317 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1318 for (Init *I : Supers->getValues()) {
1319 DefInit *DI = dyn_cast<DefInit>(I);
1321 PrintError(Rec->getLoc(), "Invalid super class reference!");
1325 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1327 PrintError(Rec->getLoc(), "Invalid super class reference!");
1329 CI->SuperClasses.push_back(SC);
1331 CI->ClassName = Rec->getValueAsString("Name");
1332 CI->Name = "MCK_" + CI->ClassName;
1333 CI->ValueName = Rec->getName();
1335 // Get or construct the predicate method name.
1336 Init *PMName = Rec->getValueInit("PredicateMethod");
1337 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1338 CI->PredicateMethod = SI->getValue();
1340 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1341 CI->PredicateMethod = "is" + CI->ClassName;
1344 // Get or construct the render method name.
1345 Init *RMName = Rec->getValueInit("RenderMethod");
1346 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1347 CI->RenderMethod = SI->getValue();
1349 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1350 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1353 // Get the parse method name or leave it as empty.
1354 Init *PRMName = Rec->getValueInit("ParserMethod");
1355 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1356 CI->ParserMethod = SI->getValue();
1358 // Get the diagnostic type or leave it as empty.
1359 // Get the parse method name or leave it as empty.
1360 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1361 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1362 CI->DiagnosticType = SI->getValue();
1364 Init *IsOptional = Rec->getValueInit("IsOptional");
1365 if (BitInit *BI = dyn_cast<BitInit>(IsOptional))
1366 CI->IsOptional = BI->getValue();
1368 // Get or construct the default method name.
1369 Init *DMName = Rec->getValueInit("DefaultMethod");
1370 if (StringInit *SI = dyn_cast<StringInit>(DMName)) {
1371 CI->DefaultMethod = SI->getValue();
1373 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1374 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1381 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1382 CodeGenTarget &target,
1383 RecordKeeper &records)
1384 : Records(records), AsmParser(asmParser), Target(target) {
1387 /// buildOperandMatchInfo - Build the necessary information to handle user
1388 /// defined operand parsing methods.
1389 void AsmMatcherInfo::buildOperandMatchInfo() {
1391 /// Map containing a mask with all operands indices that can be found for
1392 /// that class inside a instruction.
1393 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1394 OpClassMaskTy OpClassMask;
1396 for (const auto &MI : Matchables) {
1397 OpClassMask.clear();
1399 // Keep track of all operands of this instructions which belong to the
1401 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1402 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1403 if (Op.Class->ParserMethod.empty())
1405 unsigned &OperandMask = OpClassMask[Op.Class];
1406 OperandMask |= (1 << i);
1409 // Generate operand match info for each mnemonic/operand class pair.
1410 for (const auto &OCM : OpClassMask) {
1411 unsigned OpMask = OCM.second;
1412 ClassInfo *CI = OCM.first;
1413 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1419 void AsmMatcherInfo::buildInfo() {
1420 // Build information about all of the AssemblerPredicates.
1421 const std::vector<std::pair<Record *, SubtargetFeatureInfo>>
1422 &SubtargetFeaturePairs = SubtargetFeatureInfo::getAll(Records);
1423 SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),
1424 SubtargetFeaturePairs.end());
1426 for (const auto &Pair : SubtargetFeatures)
1427 DEBUG(Pair.second.dump());
1429 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1431 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
1433 // Parse the instructions; we need to do this first so that we can gather the
1434 // singleton register classes.
1435 SmallPtrSet<Record*, 16> SingletonRegisters;
1436 unsigned VariantCount = Target.getAsmParserVariantCount();
1437 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1438 Record *AsmVariant = Target.getAsmParserVariant(VC);
1439 std::string CommentDelimiter =
1440 AsmVariant->getValueAsString("CommentDelimiter");
1441 AsmVariantInfo Variant;
1442 Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1443 Variant.TokenizingCharacters =
1444 AsmVariant->getValueAsString("TokenizingCharacters");
1445 Variant.SeparatorCharacters =
1446 AsmVariant->getValueAsString("SeparatorCharacters");
1447 Variant.BreakCharacters =
1448 AsmVariant->getValueAsString("BreakCharacters");
1449 Variant.Name = AsmVariant->getValueAsString("Name");
1450 Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1452 for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
1454 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1455 // filter the set of instructions we consider.
1456 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1459 // Ignore "codegen only" instructions.
1460 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1463 // Ignore instructions for different instructions
1464 const std::string V = CGI->TheDef->getValueAsString("AsmVariantName");
1465 if (!V.empty() && V != Variant.Name)
1468 auto II = llvm::make_unique<MatchableInfo>(*CGI);
1470 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1472 // Ignore instructions which shouldn't be matched and diagnose invalid
1473 // instruction definitions with an error.
1474 if (!II->validate(CommentDelimiter, true))
1477 Matchables.push_back(std::move(II));
1480 // Parse all of the InstAlias definitions and stick them in the list of
1482 std::vector<Record*> AllInstAliases =
1483 Records.getAllDerivedDefinitions("InstAlias");
1484 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1485 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1486 Variant.AsmVariantNo,
1489 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1490 // filter the set of instruction aliases we consider, based on the target
1492 if (!StringRef(Alias->ResultInst->TheDef->getName())
1493 .startswith( MatchPrefix))
1496 const std::string V = Alias->TheDef->getValueAsString("AsmVariantName");
1497 if (!V.empty() && V != Variant.Name)
1500 auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
1502 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1504 // Validate the alias definitions.
1505 II->validate(CommentDelimiter, false);
1507 Matchables.push_back(std::move(II));
1511 // Build info for the register classes.
1512 buildRegisterClasses(SingletonRegisters);
1514 // Build info for the user defined assembly operand classes.
1515 buildOperandClasses();
1517 // Build the information about matchables, now that we have fully formed
1519 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1520 for (auto &II : Matchables) {
1521 // Parse the tokens after the mnemonic.
1522 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1523 // don't precompute the loop bound.
1524 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1525 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1526 StringRef Token = Op.Token;
1528 // Check for singleton registers.
1529 if (Record *RegRecord = Op.SingletonReg) {
1530 Op.Class = RegisterClasses[RegRecord];
1531 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1532 "Unexpected class for singleton register");
1536 // Check for simple tokens.
1537 if (Token[0] != '$') {
1538 Op.Class = getTokenClass(Token);
1542 if (Token.size() > 1 && isdigit(Token[1])) {
1543 Op.Class = getTokenClass(Token);
1547 // Otherwise this is an operand reference.
1548 StringRef OperandName;
1549 if (Token[1] == '{')
1550 OperandName = Token.substr(2, Token.size() - 3);
1552 OperandName = Token.substr(1);
1554 if (II->DefRec.is<const CodeGenInstruction*>())
1555 buildInstructionOperandReference(II.get(), OperandName, i);
1557 buildAliasOperandReference(II.get(), OperandName, Op);
1560 if (II->DefRec.is<const CodeGenInstruction*>()) {
1561 II->buildInstructionResultOperands();
1562 // If the instruction has a two-operand alias, build up the
1563 // matchable here. We'll add them in bulk at the end to avoid
1564 // confusing this loop.
1565 std::string Constraint =
1566 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1567 if (Constraint != "") {
1568 // Start by making a copy of the original matchable.
1569 auto AliasII = llvm::make_unique<MatchableInfo>(*II);
1571 // Adjust it to be a two-operand alias.
1572 AliasII->formTwoOperandAlias(Constraint);
1574 // Add the alias to the matchables list.
1575 NewMatchables.push_back(std::move(AliasII));
1578 II->buildAliasResultOperands();
1580 if (!NewMatchables.empty())
1581 Matchables.insert(Matchables.end(),
1582 std::make_move_iterator(NewMatchables.begin()),
1583 std::make_move_iterator(NewMatchables.end()));
1585 // Process token alias definitions and set up the associated superclass
1587 std::vector<Record*> AllTokenAliases =
1588 Records.getAllDerivedDefinitions("TokenAlias");
1589 for (Record *Rec : AllTokenAliases) {
1590 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1591 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1592 if (FromClass == ToClass)
1593 PrintFatalError(Rec->getLoc(),
1594 "error: Destination value identical to source value.");
1595 FromClass->SuperClasses.push_back(ToClass);
1598 // Reorder classes so that classes precede super classes.
1601 #ifdef EXPENSIVE_CHECKS
1602 // Verify that the table is sorted and operator < works transitively.
1603 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1604 for (auto J = I; J != E; ++J) {
1606 assert(I == J || !J->isSubsetOf(*I));
1612 /// buildInstructionOperandReference - The specified operand is a reference to a
1613 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1614 void AsmMatcherInfo::
1615 buildInstructionOperandReference(MatchableInfo *II,
1616 StringRef OperandName,
1617 unsigned AsmOpIdx) {
1618 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1619 const CGIOperandList &Operands = CGI.Operands;
1620 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1622 // Map this token to an operand.
1624 if (!Operands.hasOperandNamed(OperandName, Idx))
1625 PrintFatalError(II->TheDef->getLoc(),
1626 "error: unable to find operand: '" + OperandName + "'");
1628 // If the instruction operand has multiple suboperands, but the parser
1629 // match class for the asm operand is still the default "ImmAsmOperand",
1630 // then handle each suboperand separately.
1631 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1632 Record *Rec = Operands[Idx].Rec;
1633 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1634 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1635 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1636 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1637 StringRef Token = Op->Token; // save this in case Op gets moved
1638 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1639 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1640 NewAsmOp.SubOpIdx = SI;
1641 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1643 // Replace Op with first suboperand.
1644 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1649 // Set up the operand class.
1650 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1652 // If the named operand is tied, canonicalize it to the untied operand.
1653 // For example, something like:
1654 // (outs GPR:$dst), (ins GPR:$src)
1655 // with an asmstring of
1657 // we want to canonicalize to:
1659 // so that we know how to provide the $dst operand when filling in the result.
1661 if (Operands[Idx].MINumOperands == 1)
1662 OITied = Operands[Idx].getTiedRegister();
1664 // The tied operand index is an MIOperand index, find the operand that
1666 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1667 OperandName = Operands[Idx.first].Name;
1668 Op->SubOpIdx = Idx.second;
1671 Op->SrcOpName = OperandName;
1674 /// buildAliasOperandReference - When parsing an operand reference out of the
1675 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1676 /// operand reference is by looking it up in the result pattern definition.
1677 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1678 StringRef OperandName,
1679 MatchableInfo::AsmOperand &Op) {
1680 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1682 // Set up the operand class.
1683 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1684 if (CGA.ResultOperands[i].isRecord() &&
1685 CGA.ResultOperands[i].getName() == OperandName) {
1686 // It's safe to go with the first one we find, because CodeGenInstAlias
1687 // validates that all operands with the same name have the same record.
1688 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1689 // Use the match class from the Alias definition, not the
1690 // destination instruction, as we may have an immediate that's
1691 // being munged by the match class.
1692 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1694 Op.SrcOpName = OperandName;
1698 PrintFatalError(II->TheDef->getLoc(),
1699 "error: unable to find operand: '" + OperandName + "'");
1702 void MatchableInfo::buildInstructionResultOperands() {
1703 const CodeGenInstruction *ResultInst = getResultInst();
1705 // Loop over all operands of the result instruction, determining how to
1707 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1708 // If this is a tied operand, just copy from the previously handled operand.
1710 if (OpInfo.MINumOperands == 1)
1711 TiedOp = OpInfo.getTiedRegister();
1713 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1717 // Find out what operand from the asmparser this MCInst operand comes from.
1718 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1719 if (OpInfo.Name.empty() || SrcOperand == -1) {
1720 // This may happen for operands that are tied to a suboperand of a
1721 // complex operand. Simply use a dummy value here; nobody should
1722 // use this operand slot.
1723 // FIXME: The long term goal is for the MCOperand list to not contain
1724 // tied operands at all.
1725 ResOperands.push_back(ResOperand::getImmOp(0));
1729 // Check if the one AsmOperand populates the entire operand.
1730 unsigned NumOperands = OpInfo.MINumOperands;
1731 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1732 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1736 // Add a separate ResOperand for each suboperand.
1737 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1738 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1739 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1740 "unexpected AsmOperands for suboperands");
1741 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1746 void MatchableInfo::buildAliasResultOperands() {
1747 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1748 const CodeGenInstruction *ResultInst = getResultInst();
1750 // Loop over all operands of the result instruction, determining how to
1752 unsigned AliasOpNo = 0;
1753 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1754 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1755 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1757 // If this is a tied operand, just copy from the previously handled operand.
1759 if (OpInfo->MINumOperands == 1)
1760 TiedOp = OpInfo->getTiedRegister();
1762 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1766 // Handle all the suboperands for this operand.
1767 const std::string &OpName = OpInfo->Name;
1768 for ( ; AliasOpNo < LastOpNo &&
1769 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1770 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1772 // Find out what operand from the asmparser that this MCInst operand
1774 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1775 case CodeGenInstAlias::ResultOperand::K_Record: {
1776 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1777 int SrcOperand = findAsmOperand(Name, SubIdx);
1778 if (SrcOperand == -1)
1779 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1780 TheDef->getName() + "' has operand '" + OpName +
1781 "' that doesn't appear in asm string!");
1782 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1783 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1787 case CodeGenInstAlias::ResultOperand::K_Imm: {
1788 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1789 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1792 case CodeGenInstAlias::ResultOperand::K_Reg: {
1793 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1794 ResOperands.push_back(ResOperand::getRegOp(Reg));
1803 getConverterOperandID(const std::string &Name,
1804 SmallSetVector<CachedHashString, 16> &Table,
1806 IsNew = Table.insert(CachedHashString(Name));
1808 unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();
1810 assert(ID < Table.size());
1815 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1816 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1817 bool HasMnemonicFirst, bool HasOptionalOperands,
1819 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
1820 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
1821 std::vector<std::vector<uint8_t> > ConversionTable;
1822 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1824 // TargetOperandClass - This is the target's operand class, like X86Operand.
1825 std::string TargetOperandClass = Target.getName().str() + "Operand";
1827 // Write the convert function to a separate stream, so we can drop it after
1828 // the enum. We'll build up the conversion handlers for the individual
1829 // operand types opportunistically as we encounter them.
1830 std::string ConvertFnBody;
1831 raw_string_ostream CvtOS(ConvertFnBody);
1832 // Start the unified conversion function.
1833 if (HasOptionalOperands) {
1834 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1835 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1836 << "unsigned Opcode,\n"
1837 << " const OperandVector &Operands,\n"
1838 << " const SmallBitVector &OptionalOperandsMask) {\n";
1840 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1841 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1842 << "unsigned Opcode,\n"
1843 << " const OperandVector &Operands) {\n";
1845 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
1846 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
1847 if (HasOptionalOperands) {
1848 CvtOS << " unsigned NumDefaults = 0;\n";
1850 CvtOS << " unsigned OpIdx;\n";
1851 CvtOS << " Inst.setOpcode(Opcode);\n";
1852 CvtOS << " for (const uint8_t *p = Converter; *p; p+= 2) {\n";
1853 if (HasOptionalOperands) {
1854 CvtOS << " OpIdx = *(p + 1) - NumDefaults;\n";
1856 CvtOS << " OpIdx = *(p + 1);\n";
1858 CvtOS << " switch (*p) {\n";
1859 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
1860 CvtOS << " case CVT_Reg:\n";
1861 CvtOS << " static_cast<" << TargetOperandClass
1862 << "&>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
1863 CvtOS << " break;\n";
1864 CvtOS << " case CVT_Tied:\n";
1865 CvtOS << " Inst.addOperand(Inst.getOperand(OpIdx));\n";
1866 CvtOS << " break;\n";
1868 std::string OperandFnBody;
1869 raw_string_ostream OpOS(OperandFnBody);
1870 // Start the operand number lookup function.
1871 OpOS << "void " << Target.getName() << ClassName << "::\n"
1872 << "convertToMapAndConstraints(unsigned Kind,\n";
1874 OpOS << "const OperandVector &Operands) {\n"
1875 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1876 << " unsigned NumMCOperands = 0;\n"
1877 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1878 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1879 << " switch (*p) {\n"
1880 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1881 << " case CVT_Reg:\n"
1882 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1883 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1884 << " ++NumMCOperands;\n"
1886 << " case CVT_Tied:\n"
1887 << " ++NumMCOperands;\n"
1890 // Pre-populate the operand conversion kinds with the standard always
1891 // available entries.
1892 OperandConversionKinds.insert(CachedHashString("CVT_Done"));
1893 OperandConversionKinds.insert(CachedHashString("CVT_Reg"));
1894 OperandConversionKinds.insert(CachedHashString("CVT_Tied"));
1895 enum { CVT_Done, CVT_Reg, CVT_Tied };
1897 for (auto &II : Infos) {
1898 // Check if we have a custom match function.
1899 std::string AsmMatchConverter =
1900 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1901 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1902 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1903 II->ConversionFnKind = Signature;
1905 // Check if we have already generated this signature.
1906 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
1909 // Remember this converter for the kind enum.
1910 unsigned KindID = OperandConversionKinds.size();
1911 OperandConversionKinds.insert(
1912 CachedHashString("CVT_" + getEnumNameForToken(AsmMatchConverter)));
1914 // Add the converter row for this instruction.
1915 ConversionTable.emplace_back();
1916 ConversionTable.back().push_back(KindID);
1917 ConversionTable.back().push_back(CVT_Done);
1919 // Add the handler to the conversion driver function.
1920 CvtOS << " case CVT_"
1921 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1922 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1925 // FIXME: Handle the operand number lookup for custom match functions.
1929 // Build the conversion function signature.
1930 std::string Signature = "Convert";
1932 std::vector<uint8_t> ConversionRow;
1934 // Compute the convert enum and the case body.
1935 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1937 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1938 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1940 // Generate code to populate each result operand.
1941 switch (OpInfo.Kind) {
1942 case MatchableInfo::ResOperand::RenderAsmOperand: {
1943 // This comes from something we parsed.
1944 const MatchableInfo::AsmOperand &Op =
1945 II->AsmOperands[OpInfo.AsmOperandNum];
1947 // Registers are always converted the same, don't duplicate the
1948 // conversion function based on them.
1951 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1953 Signature += utostr(OpInfo.MINumOperands);
1954 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1956 // Add the conversion kind, if necessary, and get the associated ID
1957 // the index of its entry in the vector).
1958 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1959 Op.Class->RenderMethod);
1960 if (Op.Class->IsOptional) {
1961 // For optional operands we must also care about DefaultMethod
1962 assert(HasOptionalOperands);
1963 Name += "_" + Op.Class->DefaultMethod;
1965 Name = getEnumNameForToken(Name);
1967 bool IsNewConverter = false;
1968 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1971 // Add the operand entry to the instruction kind conversion row.
1972 ConversionRow.push_back(ID);
1973 ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);
1975 if (!IsNewConverter)
1978 // This is a new operand kind. Add a handler for it to the
1979 // converter driver.
1980 CvtOS << " case " << Name << ":\n";
1981 if (Op.Class->IsOptional) {
1982 // If optional operand is not present in actual instruction then we
1983 // should call its DefaultMethod before RenderMethod
1984 assert(HasOptionalOperands);
1985 CvtOS << " if (OptionalOperandsMask[*(p + 1) - 1]) {\n"
1986 << " " << Op.Class->DefaultMethod << "()"
1987 << "->" << Op.Class->RenderMethod << "(Inst, "
1988 << OpInfo.MINumOperands << ");\n"
1989 << " ++NumDefaults;\n"
1991 << " static_cast<" << TargetOperandClass
1992 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
1993 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1996 CvtOS << " static_cast<" << TargetOperandClass
1997 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
1998 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2000 CvtOS << " break;\n";
2002 // Add a handler for the operand number lookup.
2003 OpOS << " case " << Name << ":\n"
2004 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2006 if (Op.Class->isRegisterClass())
2007 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2009 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2010 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2014 case MatchableInfo::ResOperand::TiedOperand: {
2015 // If this operand is tied to a previous one, just copy the MCInst
2016 // operand from the earlier one.We can only tie single MCOperand values.
2017 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2018 unsigned TiedOp = OpInfo.TiedOperandNum;
2019 assert(i > TiedOp && "Tied operand precedes its target!");
2020 Signature += "__Tie" + utostr(TiedOp);
2021 ConversionRow.push_back(CVT_Tied);
2022 ConversionRow.push_back(TiedOp);
2025 case MatchableInfo::ResOperand::ImmOperand: {
2026 int64_t Val = OpInfo.ImmVal;
2027 std::string Ty = "imm_" + itostr(Val);
2028 Ty = getEnumNameForToken(Ty);
2029 Signature += "__" + Ty;
2031 std::string Name = "CVT_" + Ty;
2032 bool IsNewConverter = false;
2033 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2035 // Add the operand entry to the instruction kind conversion row.
2036 ConversionRow.push_back(ID);
2037 ConversionRow.push_back(0);
2039 if (!IsNewConverter)
2042 CvtOS << " case " << Name << ":\n"
2043 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2046 OpOS << " case " << Name << ":\n"
2047 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2048 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2049 << " ++NumMCOperands;\n"
2053 case MatchableInfo::ResOperand::RegOperand: {
2054 std::string Reg, Name;
2055 if (!OpInfo.Register) {
2059 Reg = getQualifiedName(OpInfo.Register);
2060 Name = "reg" + OpInfo.Register->getName().str();
2062 Signature += "__" + Name;
2063 Name = "CVT_" + Name;
2064 bool IsNewConverter = false;
2065 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2067 // Add the operand entry to the instruction kind conversion row.
2068 ConversionRow.push_back(ID);
2069 ConversionRow.push_back(0);
2071 if (!IsNewConverter)
2073 CvtOS << " case " << Name << ":\n"
2074 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
2077 OpOS << " case " << Name << ":\n"
2078 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2079 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2080 << " ++NumMCOperands;\n"
2086 // If there were no operands, add to the signature to that effect
2087 if (Signature == "Convert")
2088 Signature += "_NoOperands";
2090 II->ConversionFnKind = Signature;
2092 // Save the signature. If we already have it, don't add a new row
2094 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
2097 // Add the row to the table.
2098 ConversionTable.push_back(std::move(ConversionRow));
2101 // Finish up the converter driver function.
2102 CvtOS << " }\n }\n}\n\n";
2104 // Finish up the operand number lookup function.
2105 OpOS << " }\n }\n}\n\n";
2107 OS << "namespace {\n";
2109 // Output the operand conversion kind enum.
2110 OS << "enum OperatorConversionKind {\n";
2111 for (const auto &Converter : OperandConversionKinds)
2112 OS << " " << Converter << ",\n";
2113 OS << " CVT_NUM_CONVERTERS\n";
2116 // Output the instruction conversion kind enum.
2117 OS << "enum InstructionConversionKind {\n";
2118 for (const auto &Signature : InstructionConversionKinds)
2119 OS << " " << Signature << ",\n";
2120 OS << " CVT_NUM_SIGNATURES\n";
2123 OS << "} // end anonymous namespace\n\n";
2125 // Output the conversion table.
2126 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2127 << MaxRowLength << "] = {\n";
2129 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2130 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2131 OS << " // " << InstructionConversionKinds[Row] << "\n";
2133 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2134 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2135 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2136 OS << "CVT_Done },\n";
2141 // Spit out the conversion driver function.
2144 // Spit out the operand number lookup function.
2148 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2149 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2150 std::forward_list<ClassInfo> &Infos,
2152 OS << "namespace {\n\n";
2154 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2155 << "/// instruction matching.\n";
2156 OS << "enum MatchClassKind {\n";
2157 OS << " InvalidMatchClass = 0,\n";
2158 OS << " OptionalMatchClass = 1,\n";
2159 for (const auto &CI : Infos) {
2160 OS << " " << CI.Name << ", // ";
2161 if (CI.Kind == ClassInfo::Token) {
2162 OS << "'" << CI.ValueName << "'\n";
2163 } else if (CI.isRegisterClass()) {
2164 if (!CI.ValueName.empty())
2165 OS << "register class '" << CI.ValueName << "'\n";
2167 OS << "derived register class\n";
2169 OS << "user defined class '" << CI.ValueName << "'\n";
2172 OS << " NumMatchClassKinds\n";
2178 /// emitValidateOperandClass - Emit the function to validate an operand class.
2179 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2181 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2182 << "MatchClassKind Kind) {\n";
2183 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2184 << Info.Target.getName() << "Operand&)GOp;\n";
2186 // The InvalidMatchClass is not to match any operand.
2187 OS << " if (Kind == InvalidMatchClass)\n";
2188 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2190 // Check for Token operands first.
2191 // FIXME: Use a more specific diagnostic type.
2192 OS << " if (Operand.isToken())\n";
2193 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2194 << " MCTargetAsmParser::Match_Success :\n"
2195 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2197 // Check the user classes. We don't care what order since we're only
2198 // actually matching against one of them.
2199 OS << " switch (Kind) {\n"
2200 " default: break;\n";
2201 for (const auto &CI : Info.Classes) {
2202 if (!CI.isUserClass())
2205 OS << " // '" << CI.ClassName << "' class\n";
2206 OS << " case " << CI.Name << ":\n";
2207 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2208 OS << " return MCTargetAsmParser::Match_Success;\n";
2209 if (!CI.DiagnosticType.empty())
2210 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2211 << CI.DiagnosticType << ";\n";
2215 OS << " } // end switch (Kind)\n\n";
2217 // Check for register operands, including sub-classes.
2218 OS << " if (Operand.isReg()) {\n";
2219 OS << " MatchClassKind OpKind;\n";
2220 OS << " switch (Operand.getReg()) {\n";
2221 OS << " default: OpKind = InvalidMatchClass; break;\n";
2222 for (const auto &RC : Info.RegisterClasses)
2223 OS << " case " << Info.Target.getName() << "::"
2224 << RC.first->getName() << ": OpKind = " << RC.second->Name
2227 OS << " return isSubclass(OpKind, Kind) ? "
2228 << "MCTargetAsmParser::Match_Success :\n "
2229 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2231 // Generic fallthrough match failure case for operands that don't have
2232 // specialized diagnostic types.
2233 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2237 /// emitIsSubclass - Emit the subclass predicate function.
2238 static void emitIsSubclass(CodeGenTarget &Target,
2239 std::forward_list<ClassInfo> &Infos,
2241 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2242 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2243 OS << " if (A == B)\n";
2244 OS << " return true;\n\n";
2246 bool EmittedSwitch = false;
2247 for (const auto &A : Infos) {
2248 std::vector<StringRef> SuperClasses;
2250 SuperClasses.push_back("OptionalMatchClass");
2251 for (const auto &B : Infos) {
2252 if (&A != &B && A.isSubsetOf(B))
2253 SuperClasses.push_back(B.Name);
2256 if (SuperClasses.empty())
2259 // If this is the first SuperClass, emit the switch header.
2260 if (!EmittedSwitch) {
2261 OS << " switch (A) {\n";
2262 OS << " default:\n";
2263 OS << " return false;\n";
2264 EmittedSwitch = true;
2267 OS << "\n case " << A.Name << ":\n";
2269 if (SuperClasses.size() == 1) {
2270 OS << " return B == " << SuperClasses.back() << ";\n";
2274 if (!SuperClasses.empty()) {
2275 OS << " switch (B) {\n";
2276 OS << " default: return false;\n";
2277 for (StringRef SC : SuperClasses)
2278 OS << " case " << SC << ": return true;\n";
2281 // No case statement to emit
2282 OS << " return false;\n";
2286 // If there were case statements emitted into the string stream write the
2291 OS << " return false;\n";
2296 /// emitMatchTokenString - Emit the function to match a token string to the
2297 /// appropriate match class value.
2298 static void emitMatchTokenString(CodeGenTarget &Target,
2299 std::forward_list<ClassInfo> &Infos,
2301 // Construct the match list.
2302 std::vector<StringMatcher::StringPair> Matches;
2303 for (const auto &CI : Infos) {
2304 if (CI.Kind == ClassInfo::Token)
2305 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2308 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2310 StringMatcher("Name", Matches, OS).Emit();
2312 OS << " return InvalidMatchClass;\n";
2316 /// emitMatchRegisterName - Emit the function to match a string to the target
2317 /// specific register enum.
2318 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2320 // Construct the match list.
2321 std::vector<StringMatcher::StringPair> Matches;
2322 const auto &Regs = Target.getRegBank().getRegisters();
2323 for (const CodeGenRegister &Reg : Regs) {
2324 if (Reg.TheDef->getValueAsString("AsmName").empty())
2327 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2328 "return " + utostr(Reg.EnumValue) + ";");
2331 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2333 StringMatcher("Name", Matches, OS).Emit();
2335 OS << " return 0;\n";
2339 /// Emit the function to match a string to the target
2340 /// specific register enum.
2341 static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
2343 // Construct the match list.
2344 std::vector<StringMatcher::StringPair> Matches;
2345 const auto &Regs = Target.getRegBank().getRegisters();
2346 for (const CodeGenRegister &Reg : Regs) {
2348 auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
2350 for (auto AltName : AltNames) {
2351 AltName = StringRef(AltName).trim();
2353 // don't handle empty alternative names
2354 if (AltName.empty())
2357 Matches.emplace_back(AltName,
2358 "return " + utostr(Reg.EnumValue) + ";");
2362 OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
2364 StringMatcher("Name", Matches, OS).Emit();
2366 OS << " return 0;\n";
2370 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2371 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2372 // Get the set of diagnostic types from all of the operand classes.
2373 std::set<StringRef> Types;
2374 for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2375 if (!OpClassEntry.second->DiagnosticType.empty())
2376 Types.insert(OpClassEntry.second->DiagnosticType);
2379 if (Types.empty()) return;
2381 // Now emit the enum entries.
2382 for (StringRef Type : Types)
2383 OS << " Match_" << Type << ",\n";
2384 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2387 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2388 /// user-level name for a subtarget feature.
2389 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2390 OS << "// User-level names for subtarget features that participate in\n"
2391 << "// instruction matching.\n"
2392 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2393 if (!Info.SubtargetFeatures.empty()) {
2394 OS << " switch(Val) {\n";
2395 for (const auto &SF : Info.SubtargetFeatures) {
2396 const SubtargetFeatureInfo &SFI = SF.second;
2397 // FIXME: Totally just a placeholder name to get the algorithm working.
2398 OS << " case " << SFI.getEnumName() << ": return \""
2399 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2401 OS << " default: return \"(unknown)\";\n";
2404 // Nothing to emit, so skip the switch
2405 OS << " return \"(unknown)\";\n";
2410 static std::string GetAliasRequiredFeatures(Record *R,
2411 const AsmMatcherInfo &Info) {
2412 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2414 unsigned NumFeatures = 0;
2415 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2416 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2419 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2420 "' is not marked as an AssemblerPredicate!");
2425 Result += F->getEnumName();
2429 if (NumFeatures > 1)
2430 Result = '(' + Result + ')';
2434 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2435 std::vector<Record*> &Aliases,
2436 unsigned Indent = 0,
2437 StringRef AsmParserVariantName = StringRef()){
2438 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2439 // iteration order of the map is stable.
2440 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2442 for (Record *R : Aliases) {
2443 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2444 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2445 if (AsmVariantName != AsmParserVariantName)
2447 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2449 if (AliasesFromMnemonic.empty())
2452 // Process each alias a "from" mnemonic at a time, building the code executed
2453 // by the string remapper.
2454 std::vector<StringMatcher::StringPair> Cases;
2455 for (const auto &AliasEntry : AliasesFromMnemonic) {
2456 const std::vector<Record*> &ToVec = AliasEntry.second;
2458 // Loop through each alias and emit code that handles each case. If there
2459 // are two instructions without predicates, emit an error. If there is one,
2461 std::string MatchCode;
2462 int AliasWithNoPredicate = -1;
2464 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2465 Record *R = ToVec[i];
2466 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2468 // If this unconditionally matches, remember it for later and diagnose
2470 if (FeatureMask.empty()) {
2471 if (AliasWithNoPredicate != -1) {
2472 // We can't have two aliases from the same mnemonic with no predicate.
2473 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2474 "two MnemonicAliases with the same 'from' mnemonic!");
2475 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2478 AliasWithNoPredicate = i;
2481 if (R->getValueAsString("ToMnemonic") == AliasEntry.first)
2482 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2484 if (!MatchCode.empty())
2485 MatchCode += "else ";
2486 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2487 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2490 if (AliasWithNoPredicate != -1) {
2491 Record *R = ToVec[AliasWithNoPredicate];
2492 if (!MatchCode.empty())
2493 MatchCode += "else\n ";
2494 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2497 MatchCode += "return;";
2499 Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
2501 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2504 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2505 /// emit a function for them and return true, otherwise return false.
2506 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2507 CodeGenTarget &Target) {
2508 // Ignore aliases when match-prefix is set.
2509 if (!MatchPrefix.empty())
2512 std::vector<Record*> Aliases =
2513 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2514 if (Aliases.empty()) return false;
2516 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2517 "uint64_t Features, unsigned VariantID) {\n";
2518 OS << " switch (VariantID) {\n";
2519 unsigned VariantCount = Target.getAsmParserVariantCount();
2520 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2521 Record *AsmVariant = Target.getAsmParserVariant(VC);
2522 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2523 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2524 OS << " case " << AsmParserVariantNo << ":\n";
2525 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2526 AsmParserVariantName);
2531 // Emit aliases that apply to all variants.
2532 emitMnemonicAliasVariant(OS, Info, Aliases);
2539 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2540 const AsmMatcherInfo &Info, StringRef ClassName,
2541 StringToOffsetTable &StringTable,
2542 unsigned MaxMnemonicIndex, bool HasMnemonicFirst) {
2543 unsigned MaxMask = 0;
2544 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2545 MaxMask |= OMI.OperandMask;
2548 // Emit the static custom operand parsing table;
2549 OS << "namespace {\n";
2550 OS << " struct OperandMatchEntry {\n";
2551 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
2552 << " RequiredFeatures;\n";
2553 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2555 OS << " " << getMinimalTypeForRange(std::distance(
2556 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2557 OS << " " << getMinimalTypeForRange(MaxMask)
2558 << " OperandMask;\n\n";
2559 OS << " StringRef getMnemonic() const {\n";
2560 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2561 OS << " MnemonicTable[Mnemonic]);\n";
2565 OS << " // Predicate for searching for an opcode.\n";
2566 OS << " struct LessOpcodeOperand {\n";
2567 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2568 OS << " return LHS.getMnemonic() < RHS;\n";
2570 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2571 OS << " return LHS < RHS.getMnemonic();\n";
2573 OS << " bool operator()(const OperandMatchEntry &LHS,";
2574 OS << " const OperandMatchEntry &RHS) {\n";
2575 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2579 OS << "} // end anonymous namespace.\n\n";
2581 OS << "static const OperandMatchEntry OperandMatchTable["
2582 << Info.OperandMatchInfo.size() << "] = {\n";
2584 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2585 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2586 const MatchableInfo &II = *OMI.MI;
2590 // Write the required features mask.
2591 if (!II.RequiredFeatures.empty()) {
2592 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2594 OS << II.RequiredFeatures[i]->getEnumName();
2599 // Store a pascal-style length byte in the mnemonic.
2600 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2601 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2602 << " /* " << II.Mnemonic << " */, ";
2606 OS << ", " << OMI.OperandMask;
2608 bool printComma = false;
2609 for (int i = 0, e = 31; i !=e; ++i)
2610 if (OMI.OperandMask & (1 << i)) {
2622 // Emit the operand class switch to call the correct custom parser for
2623 // the found operand class.
2624 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2625 << "tryCustomParseOperand(OperandVector"
2626 << " &Operands,\n unsigned MCK) {\n\n"
2627 << " switch(MCK) {\n";
2629 for (const auto &CI : Info.Classes) {
2630 if (CI.ParserMethod.empty())
2632 OS << " case " << CI.Name << ":\n"
2633 << " return " << CI.ParserMethod << "(Operands);\n";
2636 OS << " default:\n";
2637 OS << " return MatchOperand_NoMatch;\n";
2639 OS << " return MatchOperand_NoMatch;\n";
2642 // Emit the static custom operand parser. This code is very similar with
2643 // the other matcher. Also use MatchResultTy here just in case we go for
2644 // a better error handling.
2645 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2646 << "MatchOperandParserImpl(OperandVector"
2647 << " &Operands,\n StringRef Mnemonic) {\n";
2649 // Emit code to get the available features.
2650 OS << " // Get the current feature set.\n";
2651 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2653 OS << " // Get the next operand index.\n";
2654 OS << " unsigned NextOpNum = Operands.size()"
2655 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
2657 // Emit code to search the table.
2658 OS << " // Search the table.\n";
2659 if (HasMnemonicFirst) {
2660 OS << " auto MnemonicRange =\n";
2661 OS << " std::equal_range(std::begin(OperandMatchTable), "
2662 "std::end(OperandMatchTable),\n";
2663 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2665 OS << " auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
2666 " std::end(OperandMatchTable));\n";
2667 OS << " if (!Mnemonic.empty())\n";
2668 OS << " MnemonicRange =\n";
2669 OS << " std::equal_range(std::begin(OperandMatchTable), "
2670 "std::end(OperandMatchTable),\n";
2671 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2674 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2675 OS << " return MatchOperand_NoMatch;\n\n";
2677 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2678 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2680 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2681 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2683 // Emit check that the required features are available.
2684 OS << " // check if the available features match\n";
2685 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2686 << "!= it->RequiredFeatures) {\n";
2687 OS << " continue;\n";
2690 // Emit check to ensure the operand number matches.
2691 OS << " // check if the operand in question has a custom parser.\n";
2692 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2693 OS << " continue;\n\n";
2695 // Emit call to the custom parser method
2696 OS << " // call custom parse method to handle the operand\n";
2697 OS << " OperandMatchResultTy Result = ";
2698 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2699 OS << " if (Result != MatchOperand_NoMatch)\n";
2700 OS << " return Result;\n";
2703 OS << " // Okay, we had no match.\n";
2704 OS << " return MatchOperand_NoMatch;\n";
2708 void AsmMatcherEmitter::run(raw_ostream &OS) {
2709 CodeGenTarget Target(Records);
2710 Record *AsmParser = Target.getAsmParser();
2711 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2713 // Compute the information on the instructions to match.
2714 AsmMatcherInfo Info(AsmParser, Target, Records);
2717 // Sort the instruction table using the partial order on classes. We use
2718 // stable_sort to ensure that ambiguous instructions are still
2719 // deterministically ordered.
2720 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2721 [](const std::unique_ptr<MatchableInfo> &a,
2722 const std::unique_ptr<MatchableInfo> &b){
2725 #ifdef EXPENSIVE_CHECKS
2726 // Verify that the table is sorted and operator < works transitively.
2727 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2729 for (auto J = I; J != E; ++J) {
2730 assert(!(**J < **I));
2735 DEBUG_WITH_TYPE("instruction_info", {
2736 for (const auto &MI : Info.Matchables)
2740 // Check for ambiguous matchables.
2741 DEBUG_WITH_TYPE("ambiguous_instrs", {
2742 unsigned NumAmbiguous = 0;
2743 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2745 for (auto J = std::next(I); J != E; ++J) {
2746 const MatchableInfo &A = **I;
2747 const MatchableInfo &B = **J;
2749 if (A.couldMatchAmbiguouslyWith(B)) {
2750 errs() << "warning: ambiguous matchables:\n";
2752 errs() << "\nis incomparable with:\n";
2760 errs() << "warning: " << NumAmbiguous
2761 << " ambiguous matchables!\n";
2764 // Compute the information on the custom operand parsing.
2765 Info.buildOperandMatchInfo();
2767 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
2768 bool HasOptionalOperands = Info.hasOptionalOperands();
2770 // Write the output.
2772 // Information for the class declaration.
2773 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2774 OS << "#undef GET_ASSEMBLER_HEADER\n";
2775 OS << " // This should be included into the middle of the declaration of\n";
2776 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2777 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2778 if (HasOptionalOperands) {
2779 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2780 << "unsigned Opcode,\n"
2781 << " const OperandVector &Operands,\n"
2782 << " const SmallBitVector &OptionalOperandsMask);\n";
2784 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2785 << "unsigned Opcode,\n"
2786 << " const OperandVector &Operands);\n";
2788 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2789 OS << " const OperandVector &Operands) override;\n";
2790 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2791 << " MCInst &Inst,\n"
2792 << " uint64_t &ErrorInfo,"
2793 << " bool matchingInlineAsm,\n"
2794 << " unsigned VariantID = 0);\n";
2796 if (!Info.OperandMatchInfo.empty()) {
2797 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2798 OS << " OperandVector &Operands,\n";
2799 OS << " StringRef Mnemonic);\n";
2801 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2802 OS << " OperandVector &Operands,\n";
2803 OS << " unsigned MCK);\n\n";
2806 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2808 // Emit the operand match diagnostic enum names.
2809 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2810 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2811 emitOperandDiagnosticTypes(Info, OS);
2812 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2814 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2815 OS << "#undef GET_REGISTER_MATCHER\n\n";
2817 // Emit the subtarget feature enumeration.
2818 SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
2819 Info.SubtargetFeatures, OS);
2821 // Emit the function to match a register name to number.
2822 // This should be omitted for Mips target
2823 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2824 emitMatchRegisterName(Target, AsmParser, OS);
2826 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))
2827 emitMatchRegisterAltName(Target, AsmParser, OS);
2829 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2831 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2832 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2834 // Generate the helper function to get the names for subtarget features.
2835 emitGetSubtargetFeatureName(Info, OS);
2837 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2839 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2840 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2842 // Generate the function that remaps for mnemonic aliases.
2843 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2845 // Generate the convertToMCInst function to convert operands into an MCInst.
2846 // Also, generate the convertToMapAndConstraints function for MS-style inline
2847 // assembly. The latter doesn't actually generate a MCInst.
2848 emitConvertFuncs(Target, ClassName, Info.Matchables, HasMnemonicFirst,
2849 HasOptionalOperands, OS);
2851 // Emit the enumeration for classes which participate in matching.
2852 emitMatchClassEnumeration(Target, Info.Classes, OS);
2854 // Emit the routine to match token strings to their match class.
2855 emitMatchTokenString(Target, Info.Classes, OS);
2857 // Emit the subclass predicate routine.
2858 emitIsSubclass(Target, Info.Classes, OS);
2860 // Emit the routine to validate an operand against a match class.
2861 emitValidateOperandClass(Info, OS);
2863 // Emit the available features compute function.
2864 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
2865 Info.Target.getName(), ClassName, "ComputeAvailableFeatures",
2866 Info.SubtargetFeatures, OS);
2868 StringToOffsetTable StringTable;
2870 size_t MaxNumOperands = 0;
2871 unsigned MaxMnemonicIndex = 0;
2872 bool HasDeprecation = false;
2873 for (const auto &MI : Info.Matchables) {
2874 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2875 HasDeprecation |= MI->HasDeprecation;
2877 // Store a pascal-style length byte in the mnemonic.
2878 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2879 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2880 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2883 OS << "static const char *const MnemonicTable =\n";
2884 StringTable.EmitString(OS);
2887 // Emit the static match table; unused classes get initialized to 0 which is
2888 // guaranteed to be InvalidMatchClass.
2890 // FIXME: We can reduce the size of this table very easily. First, we change
2891 // it so that store the kinds in separate bit-fields for each index, which
2892 // only needs to be the max width used for classes at that index (we also need
2893 // to reject based on this during classification). If we then make sure to
2894 // order the match kinds appropriately (putting mnemonics last), then we
2895 // should only end up using a few bits for each class, especially the ones
2896 // following the mnemonic.
2897 OS << "namespace {\n";
2898 OS << " struct MatchEntry {\n";
2899 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2901 OS << " uint16_t Opcode;\n";
2902 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2904 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
2905 << " RequiredFeatures;\n";
2906 OS << " " << getMinimalTypeForRange(
2907 std::distance(Info.Classes.begin(), Info.Classes.end()))
2908 << " Classes[" << MaxNumOperands << "];\n";
2909 OS << " StringRef getMnemonic() const {\n";
2910 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2911 OS << " MnemonicTable[Mnemonic]);\n";
2915 OS << " // Predicate for searching for an opcode.\n";
2916 OS << " struct LessOpcode {\n";
2917 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2918 OS << " return LHS.getMnemonic() < RHS;\n";
2920 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2921 OS << " return LHS < RHS.getMnemonic();\n";
2923 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2924 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2928 OS << "} // end anonymous namespace.\n\n";
2930 unsigned VariantCount = Target.getAsmParserVariantCount();
2931 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2932 Record *AsmVariant = Target.getAsmParserVariant(VC);
2933 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2935 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2937 for (const auto &MI : Info.Matchables) {
2938 if (MI->AsmVariantID != AsmVariantNo)
2941 // Store a pascal-style length byte in the mnemonic.
2942 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2943 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2944 << " /* " << MI->Mnemonic << " */, "
2945 << Target.getName() << "::"
2946 << MI->getResultInst()->TheDef->getName() << ", "
2947 << MI->ConversionFnKind << ", ";
2949 // Write the required features mask.
2950 if (!MI->RequiredFeatures.empty()) {
2951 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2953 OS << MI->RequiredFeatures[i]->getEnumName();
2959 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2960 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2963 OS << Op.Class->Name;
2971 // Finally, build the match function.
2972 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2973 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2974 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2975 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2977 OS << " // Eliminate obvious mismatches.\n";
2978 OS << " if (Operands.size() > "
2979 << (MaxNumOperands + HasMnemonicFirst) << ") {\n";
2980 OS << " ErrorInfo = "
2981 << (MaxNumOperands + HasMnemonicFirst) << ";\n";
2982 OS << " return Match_InvalidOperand;\n";
2985 // Emit code to get the available features.
2986 OS << " // Get the current feature set.\n";
2987 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2989 OS << " // Get the instruction mnemonic, which is the first token.\n";
2990 if (HasMnemonicFirst) {
2991 OS << " StringRef Mnemonic = ((" << Target.getName()
2992 << "Operand&)*Operands[0]).getToken();\n\n";
2994 OS << " StringRef Mnemonic;\n";
2995 OS << " if (Operands[0]->isToken())\n";
2996 OS << " Mnemonic = ((" << Target.getName()
2997 << "Operand&)*Operands[0]).getToken();\n\n";
3000 if (HasMnemonicAliases) {
3001 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3002 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3005 // Emit code to compute the class list for this operand vector.
3006 OS << " // Some state to try to produce better error messages.\n";
3007 OS << " bool HadMatchOtherThanFeatures = false;\n";
3008 OS << " bool HadMatchOtherThanPredicate = false;\n";
3009 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3010 OS << " uint64_t MissingFeatures = ~0ULL;\n";
3011 if (HasOptionalOperands) {
3012 OS << " SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n";
3014 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3015 OS << " // wrong for all instances of the instruction.\n";
3016 OS << " ErrorInfo = ~0ULL;\n";
3018 // Emit code to search the table.
3019 OS << " // Find the appropriate table for this asm variant.\n";
3020 OS << " const MatchEntry *Start, *End;\n";
3021 OS << " switch (VariantID) {\n";
3022 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3023 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3024 Record *AsmVariant = Target.getAsmParserVariant(VC);
3025 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3026 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3027 << "); End = std::end(MatchTable" << VC << "); break;\n";
3031 OS << " // Search the table.\n";
3032 if (HasMnemonicFirst) {
3033 OS << " auto MnemonicRange = "
3034 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3036 OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
3037 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3038 OS << " if (!Mnemonic.empty())\n";
3039 OS << " MnemonicRange = "
3040 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3043 OS << " // Return a more specific error code if no mnemonics match.\n";
3044 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3045 OS << " return Match_MnemonicFail;\n\n";
3047 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3048 << "*ie = MnemonicRange.second;\n";
3049 OS << " it != ie; ++it) {\n";
3051 if (HasMnemonicFirst) {
3052 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3053 OS << " assert(Mnemonic == it->getMnemonic());\n";
3056 // Emit check that the subclasses match.
3057 OS << " bool OperandsValid = true;\n";
3058 if (HasOptionalOperands) {
3059 OS << " OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";
3061 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3062 << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3063 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3064 OS << " auto Formal = "
3065 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3066 OS << " if (ActualIdx >= Operands.size()) {\n";
3067 OS << " OperandsValid = (Formal == " <<"InvalidMatchClass) || "
3068 "isSubclass(Formal, OptionalMatchClass);\n";
3069 OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n";
3070 if (HasOptionalOperands) {
3071 OS << " OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
3076 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
3077 OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n";
3078 OS << " if (Diag == Match_Success) {\n";
3079 OS << " ++ActualIdx;\n";
3080 OS << " continue;\n";
3082 OS << " // If the generic handler indicates an invalid operand\n";
3083 OS << " // failure, check for a special case.\n";
3084 OS << " if (Diag == Match_InvalidOperand) {\n";
3085 OS << " Diag = validateTargetOperandClass(Actual, Formal);\n";
3086 OS << " if (Diag == Match_Success) {\n";
3087 OS << " ++ActualIdx;\n";
3088 OS << " continue;\n";
3091 OS << " // If current formal operand wasn't matched and it is optional\n"
3092 << " // then try to match next formal operand\n";
3093 OS << " if (Diag == Match_InvalidOperand "
3094 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
3095 if (HasOptionalOperands) {
3096 OS << " OptionalOperandsMask.set(FormalIdx);\n";
3098 OS << " continue;\n";
3100 OS << " // If this operand is broken for all of the instances of this\n";
3101 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3102 OS << " // If we already had a match that only failed due to a\n";
3103 OS << " // target predicate, that diagnostic is preferred.\n";
3104 OS << " if (!HadMatchOtherThanPredicate &&\n";
3105 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
3106 OS << " ErrorInfo = ActualIdx;\n";
3107 OS << " // InvalidOperand is the default. Prefer specificity.\n";
3108 OS << " if (Diag != Match_InvalidOperand)\n";
3109 OS << " RetCode = Diag;\n";
3111 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3112 OS << " OperandsValid = false;\n";
3116 OS << " if (!OperandsValid) continue;\n";
3118 // Emit check that the required features are available.
3119 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
3120 << "!= it->RequiredFeatures) {\n";
3121 OS << " HadMatchOtherThanFeatures = true;\n";
3122 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
3123 "~AvailableFeatures;\n";
3124 OS << " if (countPopulation(NewMissingFeatures) <=\n"
3125 " countPopulation(MissingFeatures))\n";
3126 OS << " MissingFeatures = NewMissingFeatures;\n";
3127 OS << " continue;\n";
3130 OS << " Inst.clear();\n\n";
3131 OS << " Inst.setOpcode(it->Opcode);\n";
3132 // Verify the instruction with the target-specific match predicate function.
3133 OS << " // We have a potential match but have not rendered the operands.\n"
3134 << " // Check the target predicate to handle any context sensitive\n"
3135 " // constraints.\n"
3136 << " // For example, Ties that are referenced multiple times must be\n"
3137 " // checked here to ensure the input is the same for each match\n"
3138 " // constraints. If we leave it any later the ties will have been\n"
3139 " // canonicalized\n"
3140 << " unsigned MatchResult;\n"
3141 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
3142 "Operands)) != Match_Success) {\n"
3143 << " Inst.clear();\n"
3144 << " RetCode = MatchResult;\n"
3145 << " HadMatchOtherThanPredicate = true;\n"
3148 OS << " if (matchingInlineAsm) {\n";
3149 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3150 OS << " return Match_Success;\n";
3152 OS << " // We have selected a definite instruction, convert the parsed\n"
3153 << " // operands into the appropriate MCInst.\n";
3154 if (HasOptionalOperands) {
3155 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
3156 << " OptionalOperandsMask);\n";
3158 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3162 // Verify the instruction with the target-specific match predicate function.
3163 OS << " // We have a potential match. Check the target predicate to\n"
3164 << " // handle any context sensitive constraints.\n"
3165 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3166 << " Match_Success) {\n"
3167 << " Inst.clear();\n"
3168 << " RetCode = MatchResult;\n"
3169 << " HadMatchOtherThanPredicate = true;\n"
3173 // Call the post-processing function, if used.
3174 std::string InsnCleanupFn =
3175 AsmParser->getValueAsString("AsmParserInstCleanup");
3176 if (!InsnCleanupFn.empty())
3177 OS << " " << InsnCleanupFn << "(Inst);\n";
3179 if (HasDeprecation) {
3180 OS << " std::string Info;\n";
3181 OS << " if (!getParser().getTargetParser().\n";
3182 OS << " getTargetOptions().MCNoDeprecatedWarn &&\n";
3183 OS << " MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
3184 OS << " SMLoc Loc = ((" << Target.getName()
3185 << "Operand&)*Operands[0]).getStartLoc();\n";
3186 OS << " getParser().Warning(Loc, Info, None);\n";
3190 OS << " return Match_Success;\n";
3193 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3194 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3195 OS << " return RetCode;\n\n";
3196 OS << " // Missing feature matches return which features were missing\n";
3197 OS << " ErrorInfo = MissingFeatures;\n";
3198 OS << " return Match_MissingFeature;\n";
3201 if (!Info.OperandMatchInfo.empty())
3202 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3203 MaxMnemonicIndex, HasMnemonicFirst);
3205 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3210 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3211 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3212 AsmMatcherEmitter(RK).run(OS);
3215 } // end namespace llvm