1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "SubtargetFeatureInfo.h"
102 #include "llvm/ADT/CachedHashString.h"
103 #include "llvm/ADT/PointerUnion.h"
104 #include "llvm/ADT/STLExtras.h"
105 #include "llvm/ADT/SmallPtrSet.h"
106 #include "llvm/ADT/SmallVector.h"
107 #include "llvm/ADT/StringExtras.h"
108 #include "llvm/Support/CommandLine.h"
109 #include "llvm/Support/Debug.h"
110 #include "llvm/Support/ErrorHandling.h"
111 #include "llvm/TableGen/Error.h"
112 #include "llvm/TableGen/Record.h"
113 #include "llvm/TableGen/StringMatcher.h"
114 #include "llvm/TableGen/StringToOffsetTable.h"
115 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
122 using namespace llvm;
124 #define DEBUG_TYPE "asm-matcher-emitter"
126 cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
128 static cl::opt<std::string>
129 MatchPrefix("match-prefix", cl::init(""),
130 cl::desc("Only match instructions with the given prefix"),
131 cl::cat(AsmMatcherEmitterCat));
134 class AsmMatcherInfo;
136 // Register sets are used as keys in some second-order sets TableGen creates
137 // when generating its data structures. This means that the order of two
138 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
139 // can even affect compiler output (at least seen in diagnostics produced when
140 // all matches fail). So we use a type that sorts them consistently.
141 typedef std::set<Record*, LessRecordByID> RegisterSet;
143 class AsmMatcherEmitter {
144 RecordKeeper &Records;
146 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
148 void run(raw_ostream &o);
151 /// ClassInfo - Helper class for storing the information about a particular
152 /// class of operands which can be matched.
155 /// Invalid kind, for use as a sentinel value.
158 /// The class for a particular token.
161 /// The (first) register class, subsequent register classes are
162 /// RegisterClass0+1, and so on.
165 /// The (first) user defined class, subsequent user defined classes are
166 /// UserClass0+1, and so on.
170 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
171 /// N) for the Nth user defined class.
174 /// SuperClasses - The super classes of this class. Note that for simplicities
175 /// sake user operands only record their immediate super class, while register
176 /// operands include all superclasses.
177 std::vector<ClassInfo*> SuperClasses;
179 /// Name - The full class name, suitable for use in an enum.
182 /// ClassName - The unadorned generic name for this class (e.g., Token).
183 std::string ClassName;
185 /// ValueName - The name of the value this class represents; for a token this
186 /// is the literal token string, for an operand it is the TableGen class (or
187 /// empty if this is a derived class).
188 std::string ValueName;
190 /// PredicateMethod - The name of the operand method to test whether the
191 /// operand matches this class; this is not valid for Token or register kinds.
192 std::string PredicateMethod;
194 /// RenderMethod - The name of the operand method to add this operand to an
195 /// MCInst; this is not valid for Token or register kinds.
196 std::string RenderMethod;
198 /// ParserMethod - The name of the operand method to do a target specific
199 /// parsing on the operand.
200 std::string ParserMethod;
202 /// For register classes: the records for all the registers in this class.
203 RegisterSet Registers;
205 /// For custom match classes: the diagnostic kind for when the predicate fails.
206 std::string DiagnosticType;
208 /// For custom match classes: the diagnostic string for when the predicate fails.
209 std::string DiagnosticString;
211 /// Is this operand optional and not always required.
214 /// DefaultMethod - The name of the method that returns the default operand
215 /// for optional operand
216 std::string DefaultMethod;
219 /// isRegisterClass() - Check if this is a register class.
220 bool isRegisterClass() const {
221 return Kind >= RegisterClass0 && Kind < UserClass0;
224 /// isUserClass() - Check if this is a user defined class.
225 bool isUserClass() const {
226 return Kind >= UserClass0;
229 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
230 /// are related if they are in the same class hierarchy.
231 bool isRelatedTo(const ClassInfo &RHS) const {
232 // Tokens are only related to tokens.
233 if (Kind == Token || RHS.Kind == Token)
234 return Kind == Token && RHS.Kind == Token;
236 // Registers classes are only related to registers classes, and only if
237 // their intersection is non-empty.
238 if (isRegisterClass() || RHS.isRegisterClass()) {
239 if (!isRegisterClass() || !RHS.isRegisterClass())
243 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
244 std::set_intersection(Registers.begin(), Registers.end(),
245 RHS.Registers.begin(), RHS.Registers.end(),
246 II, LessRecordByID());
251 // Otherwise we have two users operands; they are related if they are in the
252 // same class hierarchy.
254 // FIXME: This is an oversimplification, they should only be related if they
255 // intersect, however we don't have that information.
256 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
257 const ClassInfo *Root = this;
258 while (!Root->SuperClasses.empty())
259 Root = Root->SuperClasses.front();
261 const ClassInfo *RHSRoot = &RHS;
262 while (!RHSRoot->SuperClasses.empty())
263 RHSRoot = RHSRoot->SuperClasses.front();
265 return Root == RHSRoot;
268 /// isSubsetOf - Test whether this class is a subset of \p RHS.
269 bool isSubsetOf(const ClassInfo &RHS) const {
270 // This is a subset of RHS if it is the same class...
274 // ... or if any of its super classes are a subset of RHS.
275 for (const ClassInfo *CI : SuperClasses)
276 if (CI->isSubsetOf(RHS))
282 int getTreeDepth() const {
284 const ClassInfo *Root = this;
285 while (!Root->SuperClasses.empty()) {
287 Root = Root->SuperClasses.front();
292 const ClassInfo *findRoot() const {
293 const ClassInfo *Root = this;
294 while (!Root->SuperClasses.empty())
295 Root = Root->SuperClasses.front();
299 /// Compare two classes. This does not produce a total ordering, but does
300 /// guarantee that subclasses are sorted before their parents, and that the
301 /// ordering is transitive.
302 bool operator<(const ClassInfo &RHS) const {
306 // First, enforce the ordering between the three different types of class.
307 // Tokens sort before registers, which sort before user classes.
309 if (RHS.Kind != Token)
311 assert(RHS.Kind == Token);
312 } else if (isRegisterClass()) {
313 if (RHS.Kind == Token)
315 else if (RHS.isUserClass())
317 assert(RHS.isRegisterClass());
318 } else if (isUserClass()) {
319 if (!RHS.isUserClass())
321 assert(RHS.isUserClass());
323 llvm_unreachable("Unknown ClassInfoKind");
326 if (Kind == Token || isUserClass()) {
327 // Related tokens and user classes get sorted by depth in the inheritence
328 // tree (so that subclasses are before their parents).
329 if (isRelatedTo(RHS)) {
330 if (getTreeDepth() > RHS.getTreeDepth())
332 if (getTreeDepth() < RHS.getTreeDepth())
335 // Unrelated tokens and user classes are ordered by the name of their
336 // root nodes, so that there is a consistent ordering between
337 // unconnected trees.
338 return findRoot()->ValueName < RHS.findRoot()->ValueName;
340 } else if (isRegisterClass()) {
341 // For register sets, sort by number of registers. This guarantees that
342 // a set will always sort before all of it's strict supersets.
343 if (Registers.size() != RHS.Registers.size())
344 return Registers.size() < RHS.Registers.size();
346 llvm_unreachable("Unknown ClassInfoKind");
349 // FIXME: We should be able to just return false here, as we only need a
350 // partial order (we use stable sorts, so this is deterministic) and the
351 // name of a class shouldn't be significant. However, some of the backends
352 // accidentally rely on this behaviour, so it will have to stay like this
353 // until they are fixed.
354 return ValueName < RHS.ValueName;
358 class AsmVariantInfo {
360 StringRef RegisterPrefix;
361 StringRef TokenizingCharacters;
362 StringRef SeparatorCharacters;
363 StringRef BreakCharacters;
368 /// MatchableInfo - Helper class for storing the necessary information for an
369 /// instruction or alias which is capable of being matched.
370 struct MatchableInfo {
372 /// Token - This is the token that the operand came from.
375 /// The unique class instance this operand should match.
378 /// The operand name this is, if anything.
381 /// The suboperand index within SrcOpName, or -1 for the entire operand.
384 /// Whether the token is "isolated", i.e., it is preceded and followed
386 bool IsIsolatedToken;
388 /// Register record if this token is singleton register.
389 Record *SingletonReg;
391 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
392 : Token(T), Class(nullptr), SubOpIdx(-1),
393 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
396 /// ResOperand - This represents a single operand in the result instruction
397 /// generated by the match. In cases (like addressing modes) where a single
398 /// assembler operand expands to multiple MCOperands, this represents the
399 /// single assembler operand, not the MCOperand.
402 /// RenderAsmOperand - This represents an operand result that is
403 /// generated by calling the render method on the assembly operand. The
404 /// corresponding AsmOperand is specified by AsmOperandNum.
407 /// TiedOperand - This represents a result operand that is a duplicate of
408 /// a previous result operand.
411 /// ImmOperand - This represents an immediate value that is dumped into
415 /// RegOperand - This represents a fixed register that is dumped in.
420 /// This is the operand # in the AsmOperands list that this should be
422 unsigned AsmOperandNum;
424 /// TiedOperandNum - This is the (earlier) result operand that should be
426 unsigned TiedOperandNum;
428 /// ImmVal - This is the immediate value added to the instruction.
431 /// Register - This is the register record.
435 /// MINumOperands - The number of MCInst operands populated by this
437 unsigned MINumOperands;
439 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
441 X.Kind = RenderAsmOperand;
442 X.AsmOperandNum = AsmOpNum;
443 X.MINumOperands = NumOperands;
447 static ResOperand getTiedOp(unsigned TiedOperandNum) {
449 X.Kind = TiedOperand;
450 X.TiedOperandNum = TiedOperandNum;
455 static ResOperand getImmOp(int64_t Val) {
463 static ResOperand getRegOp(Record *Reg) {
472 /// AsmVariantID - Target's assembly syntax variant no.
475 /// AsmString - The assembly string for this instruction (with variants
476 /// removed), e.g. "movsx $src, $dst".
477 std::string AsmString;
479 /// TheDef - This is the definition of the instruction or InstAlias that this
480 /// matchable came from.
481 Record *const TheDef;
483 /// DefRec - This is the definition that it came from.
484 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
486 const CodeGenInstruction *getResultInst() const {
487 if (DefRec.is<const CodeGenInstruction*>())
488 return DefRec.get<const CodeGenInstruction*>();
489 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
492 /// ResOperands - This is the operand list that should be built for the result
494 SmallVector<ResOperand, 8> ResOperands;
496 /// Mnemonic - This is the first token of the matched instruction, its
500 /// AsmOperands - The textual operands that this instruction matches,
501 /// annotated with a class and where in the OperandList they were defined.
502 /// This directly corresponds to the tokenized AsmString after the mnemonic is
504 SmallVector<AsmOperand, 8> AsmOperands;
506 /// Predicates - The required subtarget features to match this instruction.
507 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
509 /// ConversionFnKind - The enum value which is passed to the generated
510 /// convertToMCInst to convert parsed operands into an MCInst for this
512 std::string ConversionFnKind;
514 /// If this instruction is deprecated in some form.
517 /// If this is an alias, this is use to determine whether or not to using
518 /// the conversion function defined by the instruction's AsmMatchConverter
519 /// or to use the function generated by the alias.
520 bool UseInstAsmMatchConverter;
522 MatchableInfo(const CodeGenInstruction &CGI)
523 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
524 UseInstAsmMatchConverter(true) {
527 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
528 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
529 DefRec(Alias.release()),
530 UseInstAsmMatchConverter(
531 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
534 // Could remove this and the dtor if PointerUnion supported unique_ptr
535 // elements with a dynamic failure/assertion (like the one below) in the case
536 // where it was copied while being in an owning state.
537 MatchableInfo(const MatchableInfo &RHS)
538 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
539 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
540 Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
541 RequiredFeatures(RHS.RequiredFeatures),
542 ConversionFnKind(RHS.ConversionFnKind),
543 HasDeprecation(RHS.HasDeprecation),
544 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
545 assert(!DefRec.is<const CodeGenInstAlias *>());
549 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
552 // Two-operand aliases clone from the main matchable, but mark the second
553 // operand as a tied operand of the first for purposes of the assembler.
554 void formTwoOperandAlias(StringRef Constraint);
556 void initialize(const AsmMatcherInfo &Info,
557 SmallPtrSetImpl<Record*> &SingletonRegisters,
558 AsmVariantInfo const &Variant,
559 bool HasMnemonicFirst);
561 /// validate - Return true if this matchable is a valid thing to match against
562 /// and perform a bunch of validity checking.
563 bool validate(StringRef CommentDelimiter, bool Hack) const;
565 /// findAsmOperand - Find the AsmOperand with the specified name and
566 /// suboperand index.
567 int findAsmOperand(StringRef N, int SubOpIdx) const {
568 auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {
569 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
571 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
574 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
575 /// This does not check the suboperand index.
576 int findAsmOperandNamed(StringRef N) const {
577 auto I = find_if(AsmOperands,
578 [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
579 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
582 void buildInstructionResultOperands();
583 void buildAliasResultOperands();
585 /// operator< - Compare two matchables.
586 bool operator<(const MatchableInfo &RHS) const {
587 // The primary comparator is the instruction mnemonic.
588 if (int Cmp = Mnemonic.compare(RHS.Mnemonic))
591 if (AsmOperands.size() != RHS.AsmOperands.size())
592 return AsmOperands.size() < RHS.AsmOperands.size();
594 // Compare lexicographically by operand. The matcher validates that other
595 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
596 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
597 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
599 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
603 // Give matches that require more features higher precedence. This is useful
604 // because we cannot define AssemblerPredicates with the negation of
605 // processor features. For example, ARM v6 "nop" may be either a HINT or
606 // MOV. With v6, we want to match HINT. The assembler has no way to
607 // predicate MOV under "NoV6", but HINT will always match first because it
608 // requires V6 while MOV does not.
609 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
610 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
615 /// couldMatchAmbiguouslyWith - Check whether this matchable could
616 /// ambiguously match the same set of operands as \p RHS (without being a
617 /// strictly superior match).
618 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
619 // The primary comparator is the instruction mnemonic.
620 if (Mnemonic != RHS.Mnemonic)
623 // The number of operands is unambiguous.
624 if (AsmOperands.size() != RHS.AsmOperands.size())
627 // Otherwise, make sure the ordering of the two instructions is unambiguous
628 // by checking that either (a) a token or operand kind discriminates them,
629 // or (b) the ordering among equivalent kinds is consistent.
631 // Tokens and operand kinds are unambiguous (assuming a correct target
633 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
634 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
635 AsmOperands[i].Class->Kind == ClassInfo::Token)
636 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
637 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
640 // Otherwise, this operand could commute if all operands are equivalent, or
641 // there is a pair of operands that compare less than and a pair that
642 // compare greater than.
643 bool HasLT = false, HasGT = false;
644 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
645 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
647 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
651 return HasLT == HasGT;
657 void tokenizeAsmString(AsmMatcherInfo const &Info,
658 AsmVariantInfo const &Variant);
659 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
662 struct OperandMatchEntry {
663 unsigned OperandMask;
664 const MatchableInfo* MI;
667 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
670 X.OperandMask = opMask;
677 class AsmMatcherInfo {
680 RecordKeeper &Records;
682 /// The tablegen AsmParser record.
685 /// Target - The target information.
686 CodeGenTarget &Target;
688 /// The classes which are needed for matching.
689 std::forward_list<ClassInfo> Classes;
691 /// The information on the matchables to match.
692 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
694 /// Info for custom matching operands by user defined methods.
695 std::vector<OperandMatchEntry> OperandMatchInfo;
697 /// Map of Register records to their class information.
698 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
699 RegisterClassesTy RegisterClasses;
701 /// Map of Predicate records to their subtarget information.
702 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
704 /// Map of AsmOperandClass records to their class information.
705 std::map<Record*, ClassInfo*> AsmOperandClasses;
707 /// Map of RegisterClass records to their class information.
708 std::map<Record*, ClassInfo*> RegisterClassClasses;
711 /// Map of token to class information which has already been constructed.
712 std::map<std::string, ClassInfo*> TokenClasses;
715 /// getTokenClass - Lookup or create the class for the given token.
716 ClassInfo *getTokenClass(StringRef Token);
718 /// getOperandClass - Lookup or create the class for the given operand.
719 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
721 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
723 /// buildRegisterClasses - Build the ClassInfo* instances for register
725 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
727 /// buildOperandClasses - Build the ClassInfo* instances for user defined
729 void buildOperandClasses();
731 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
733 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
734 MatchableInfo::AsmOperand &Op);
737 AsmMatcherInfo(Record *AsmParser,
738 CodeGenTarget &Target,
739 RecordKeeper &Records);
741 /// Construct the various tables used during matching.
744 /// buildOperandMatchInfo - Build the necessary information to handle user
745 /// defined operand parsing methods.
746 void buildOperandMatchInfo();
748 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
750 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
751 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
752 const auto &I = SubtargetFeatures.find(Def);
753 return I == SubtargetFeatures.end() ? nullptr : &I->second;
756 RecordKeeper &getRecords() const {
760 bool hasOptionalOperands() const {
761 return find_if(Classes, [](const ClassInfo &Class) {
762 return Class.IsOptional;
767 } // end anonymous namespace
769 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
770 LLVM_DUMP_METHOD void MatchableInfo::dump() const {
771 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
773 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
774 const AsmOperand &Op = AsmOperands[i];
775 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
776 errs() << '\"' << Op.Token << "\"\n";
781 static std::pair<StringRef, StringRef>
782 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
783 // Split via the '='.
784 std::pair<StringRef, StringRef> Ops = S.split('=');
785 if (Ops.second == "")
786 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
787 // Trim whitespace and the leading '$' on the operand names.
788 size_t start = Ops.first.find_first_of('$');
789 if (start == std::string::npos)
790 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
791 Ops.first = Ops.first.slice(start + 1, std::string::npos);
792 size_t end = Ops.first.find_last_of(" \t");
793 Ops.first = Ops.first.slice(0, end);
794 // Now the second operand.
795 start = Ops.second.find_first_of('$');
796 if (start == std::string::npos)
797 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
798 Ops.second = Ops.second.slice(start + 1, std::string::npos);
799 end = Ops.second.find_last_of(" \t");
800 Ops.first = Ops.first.slice(0, end);
804 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
805 // Figure out which operands are aliased and mark them as tied.
806 std::pair<StringRef, StringRef> Ops =
807 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
809 // Find the AsmOperands that refer to the operands we're aliasing.
810 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
811 int DstAsmOperand = findAsmOperandNamed(Ops.second);
812 if (SrcAsmOperand == -1)
813 PrintFatalError(TheDef->getLoc(),
814 "unknown source two-operand alias operand '" + Ops.first +
816 if (DstAsmOperand == -1)
817 PrintFatalError(TheDef->getLoc(),
818 "unknown destination two-operand alias operand '" +
821 // Find the ResOperand that refers to the operand we're aliasing away
822 // and update it to refer to the combined operand instead.
823 for (ResOperand &Op : ResOperands) {
824 if (Op.Kind == ResOperand::RenderAsmOperand &&
825 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
826 Op.AsmOperandNum = DstAsmOperand;
830 // Remove the AsmOperand for the alias operand.
831 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
832 // Adjust the ResOperand references to any AsmOperands that followed
833 // the one we just deleted.
834 for (ResOperand &Op : ResOperands) {
837 // Nothing to do for operands that don't reference AsmOperands.
839 case ResOperand::RenderAsmOperand:
840 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
843 case ResOperand::TiedOperand:
844 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
851 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
852 /// if present, from specified token.
854 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
855 const AsmMatcherInfo &Info,
856 StringRef RegisterPrefix) {
857 StringRef Tok = Op.Token;
859 // If this token is not an isolated token, i.e., it isn't separated from
860 // other tokens (e.g. with whitespace), don't interpret it as a register name.
861 if (!Op.IsIsolatedToken)
864 if (RegisterPrefix.empty()) {
865 std::string LoweredTok = Tok.lower();
866 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
867 Op.SingletonReg = Reg->TheDef;
871 if (!Tok.startswith(RegisterPrefix))
874 StringRef RegName = Tok.substr(RegisterPrefix.size());
875 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
876 Op.SingletonReg = Reg->TheDef;
878 // If there is no register prefix (i.e. "%" in "%eax"), then this may
879 // be some random non-register token, just ignore it.
882 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
883 SmallPtrSetImpl<Record*> &SingletonRegisters,
884 AsmVariantInfo const &Variant,
885 bool HasMnemonicFirst) {
886 AsmVariantID = Variant.AsmVariantNo;
888 CodeGenInstruction::FlattenAsmStringVariants(AsmString,
889 Variant.AsmVariantNo);
891 tokenizeAsmString(Info, Variant);
893 // The first token of the instruction is the mnemonic, which must be a
894 // simple string, not a $foo variable or a singleton register.
895 if (AsmOperands.empty())
896 PrintFatalError(TheDef->getLoc(),
897 "Instruction '" + TheDef->getName() + "' has no tokens");
899 assert(!AsmOperands[0].Token.empty());
900 if (HasMnemonicFirst) {
901 Mnemonic = AsmOperands[0].Token;
902 if (Mnemonic[0] == '$')
903 PrintFatalError(TheDef->getLoc(),
904 "Invalid instruction mnemonic '" + Mnemonic + "'!");
906 // Remove the first operand, it is tracked in the mnemonic field.
907 AsmOperands.erase(AsmOperands.begin());
908 } else if (AsmOperands[0].Token[0] != '$')
909 Mnemonic = AsmOperands[0].Token;
911 // Compute the require features.
912 for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
913 if (const SubtargetFeatureInfo *Feature =
914 Info.getSubtargetFeature(Predicate))
915 RequiredFeatures.push_back(Feature);
917 // Collect singleton registers, if used.
918 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
919 extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
920 if (Record *Reg = Op.SingletonReg)
921 SingletonRegisters.insert(Reg);
924 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
926 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
929 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
932 /// Append an AsmOperand for the given substring of AsmString.
933 void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
934 AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));
937 /// tokenizeAsmString - Tokenize a simplified assembly string.
938 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
939 AsmVariantInfo const &Variant) {
940 StringRef String = AsmString;
943 bool IsIsolatedToken = true;
944 for (size_t i = 0, e = String.size(); i != e; ++i) {
945 char Char = String[i];
946 if (Variant.BreakCharacters.find(Char) != std::string::npos) {
948 addAsmOperand(String.slice(Prev, i), false);
950 IsIsolatedToken = false;
955 if (Variant.TokenizingCharacters.find(Char) != std::string::npos) {
957 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
959 IsIsolatedToken = false;
961 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
963 IsIsolatedToken = true;
966 if (Variant.SeparatorCharacters.find(Char) != std::string::npos) {
968 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
972 IsIsolatedToken = true;
979 addAsmOperand(String.slice(Prev, i), false);
981 IsIsolatedToken = false;
984 assert(i != String.size() && "Invalid quoted character");
985 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
987 IsIsolatedToken = false;
992 addAsmOperand(String.slice(Prev, i), false);
994 IsIsolatedToken = false;
997 // If this isn't "${", start new identifier looking like "$xxx"
998 if (i + 1 == String.size() || String[i + 1] != '{') {
1003 size_t EndPos = String.find('}', i);
1004 assert(EndPos != StringRef::npos &&
1005 "Missing brace in operand reference!");
1006 addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
1009 IsIsolatedToken = false;
1018 if (InTok && Prev != String.size())
1019 addAsmOperand(String.substr(Prev), IsIsolatedToken);
1022 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
1023 // Reject matchables with no .s string.
1024 if (AsmString.empty())
1025 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
1027 // Reject any matchables with a newline in them, they should be marked
1028 // isCodeGenOnly if they are pseudo instructions.
1029 if (AsmString.find('\n') != std::string::npos)
1030 PrintFatalError(TheDef->getLoc(),
1031 "multiline instruction is not valid for the asmparser, "
1032 "mark it isCodeGenOnly");
1034 // Remove comments from the asm string. We know that the asmstring only
1036 if (!CommentDelimiter.empty() &&
1037 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
1038 PrintFatalError(TheDef->getLoc(),
1039 "asmstring for instruction has comment character in it, "
1040 "mark it isCodeGenOnly");
1042 // Reject matchables with operand modifiers, these aren't something we can
1043 // handle, the target should be refactored to use operands instead of
1046 // Also, check for instructions which reference the operand multiple times;
1047 // this implies a constraint we would not honor.
1048 std::set<std::string> OperandNames;
1049 for (const AsmOperand &Op : AsmOperands) {
1050 StringRef Tok = Op.Token;
1051 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
1052 PrintFatalError(TheDef->getLoc(),
1053 "matchable with operand modifier '" + Tok +
1054 "' not supported by asm matcher. Mark isCodeGenOnly!");
1056 // Verify that any operand is only mentioned once.
1057 // We reject aliases and ignore instructions for now.
1058 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1060 PrintFatalError(TheDef->getLoc(),
1061 "ERROR: matchable with tied operand '" + Tok +
1062 "' can never be matched!");
1063 // FIXME: Should reject these. The ARM backend hits this with $lane in a
1064 // bunch of instructions. It is unclear what the right answer is.
1066 errs() << "warning: '" << TheDef->getName() << "': "
1067 << "ignoring instruction with tied operand '"
1077 static std::string getEnumNameForToken(StringRef Str) {
1080 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1082 case '*': Res += "_STAR_"; break;
1083 case '%': Res += "_PCT_"; break;
1084 case ':': Res += "_COLON_"; break;
1085 case '!': Res += "_EXCLAIM_"; break;
1086 case '.': Res += "_DOT_"; break;
1087 case '<': Res += "_LT_"; break;
1088 case '>': Res += "_GT_"; break;
1089 case '-': Res += "_MINUS_"; break;
1091 if ((*it >= 'A' && *it <= 'Z') ||
1092 (*it >= 'a' && *it <= 'z') ||
1093 (*it >= '0' && *it <= '9'))
1096 Res += "_" + utostr((unsigned) *it) + "_";
1103 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1104 ClassInfo *&Entry = TokenClasses[Token];
1107 Classes.emplace_front();
1108 Entry = &Classes.front();
1109 Entry->Kind = ClassInfo::Token;
1110 Entry->ClassName = "Token";
1111 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1112 Entry->ValueName = Token;
1113 Entry->PredicateMethod = "<invalid>";
1114 Entry->RenderMethod = "<invalid>";
1115 Entry->ParserMethod = "";
1116 Entry->DiagnosticType = "";
1117 Entry->IsOptional = false;
1118 Entry->DefaultMethod = "<invalid>";
1125 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1127 Record *Rec = OI.Rec;
1129 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1130 return getOperandClass(Rec, SubOpIdx);
1134 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1135 if (Rec->isSubClassOf("RegisterOperand")) {
1136 // RegisterOperand may have an associated ParserMatchClass. If it does,
1137 // use it, else just fall back to the underlying register class.
1138 const RecordVal *R = Rec->getValue("ParserMatchClass");
1139 if (!R || !R->getValue())
1140 PrintFatalError("Record `" + Rec->getName() +
1141 "' does not have a ParserMatchClass!\n");
1143 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1144 Record *MatchClass = DI->getDef();
1145 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1149 // No custom match class. Just use the register class.
1150 Record *ClassRec = Rec->getValueAsDef("RegClass");
1152 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1153 "' has no associated register class!\n");
1154 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1156 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1159 if (Rec->isSubClassOf("RegisterClass")) {
1160 if (ClassInfo *CI = RegisterClassClasses[Rec])
1162 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1165 if (!Rec->isSubClassOf("Operand"))
1166 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1167 "' does not derive from class Operand!\n");
1168 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1169 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1172 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1175 struct LessRegisterSet {
1176 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1177 // std::set<T> defines its own compariso "operator<", but it
1178 // performs a lexicographical comparison by T's innate comparison
1179 // for some reason. We don't want non-deterministic pointer
1180 // comparisons so use this instead.
1181 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1182 RHS.begin(), RHS.end(),
1187 void AsmMatcherInfo::
1188 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1189 const auto &Registers = Target.getRegBank().getRegisters();
1190 auto &RegClassList = Target.getRegBank().getRegClasses();
1192 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1194 // The register sets used for matching.
1195 RegisterSetSet RegisterSets;
1197 // Gather the defined sets.
1198 for (const CodeGenRegisterClass &RC : RegClassList)
1199 RegisterSets.insert(
1200 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1202 // Add any required singleton sets.
1203 for (Record *Rec : SingletonRegisters) {
1204 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1207 // Introduce derived sets where necessary (when a register does not determine
1208 // a unique register set class), and build the mapping of registers to the set
1209 // they should classify to.
1210 std::map<Record*, RegisterSet> RegisterMap;
1211 for (const CodeGenRegister &CGR : Registers) {
1212 // Compute the intersection of all sets containing this register.
1213 RegisterSet ContainingSet;
1215 for (const RegisterSet &RS : RegisterSets) {
1216 if (!RS.count(CGR.TheDef))
1219 if (ContainingSet.empty()) {
1225 std::swap(Tmp, ContainingSet);
1226 std::insert_iterator<RegisterSet> II(ContainingSet,
1227 ContainingSet.begin());
1228 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1232 if (!ContainingSet.empty()) {
1233 RegisterSets.insert(ContainingSet);
1234 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1238 // Construct the register classes.
1239 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1241 for (const RegisterSet &RS : RegisterSets) {
1242 Classes.emplace_front();
1243 ClassInfo *CI = &Classes.front();
1244 CI->Kind = ClassInfo::RegisterClass0 + Index;
1245 CI->ClassName = "Reg" + utostr(Index);
1246 CI->Name = "MCK_Reg" + utostr(Index);
1248 CI->PredicateMethod = ""; // unused
1249 CI->RenderMethod = "addRegOperands";
1251 // FIXME: diagnostic type.
1252 CI->DiagnosticType = "";
1253 CI->IsOptional = false;
1254 CI->DefaultMethod = ""; // unused
1255 RegisterSetClasses.insert(std::make_pair(RS, CI));
1259 // Find the superclasses; we could compute only the subgroup lattice edges,
1260 // but there isn't really a point.
1261 for (const RegisterSet &RS : RegisterSets) {
1262 ClassInfo *CI = RegisterSetClasses[RS];
1263 for (const RegisterSet &RS2 : RegisterSets)
1265 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1267 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1270 // Name the register classes which correspond to a user defined RegisterClass.
1271 for (const CodeGenRegisterClass &RC : RegClassList) {
1272 // Def will be NULL for non-user defined register classes.
1273 Record *Def = RC.getDef();
1276 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1277 RC.getOrder().end())];
1278 if (CI->ValueName.empty()) {
1279 CI->ClassName = RC.getName();
1280 CI->Name = "MCK_" + RC.getName();
1281 CI->ValueName = RC.getName();
1283 CI->ValueName = CI->ValueName + "," + RC.getName();
1285 Init *DiagnosticType = Def->getValueInit("DiagnosticType");
1286 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1287 CI->DiagnosticType = SI->getValue();
1289 Init *DiagnosticString = Def->getValueInit("DiagnosticString");
1290 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticString))
1291 CI->DiagnosticString = SI->getValue();
1293 // If we have a diagnostic string but the diagnostic type is not specified
1294 // explicitly, create an anonymous diagnostic type.
1295 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1296 CI->DiagnosticType = RC.getName();
1298 RegisterClassClasses.insert(std::make_pair(Def, CI));
1301 // Populate the map for individual registers.
1302 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1303 ie = RegisterMap.end(); it != ie; ++it)
1304 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1306 // Name the register classes which correspond to singleton registers.
1307 for (Record *Rec : SingletonRegisters) {
1308 ClassInfo *CI = RegisterClasses[Rec];
1309 assert(CI && "Missing singleton register class info!");
1311 if (CI->ValueName.empty()) {
1312 CI->ClassName = Rec->getName();
1313 CI->Name = "MCK_" + Rec->getName().str();
1314 CI->ValueName = Rec->getName();
1316 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1320 void AsmMatcherInfo::buildOperandClasses() {
1321 std::vector<Record*> AsmOperands =
1322 Records.getAllDerivedDefinitions("AsmOperandClass");
1324 // Pre-populate AsmOperandClasses map.
1325 for (Record *Rec : AsmOperands) {
1326 Classes.emplace_front();
1327 AsmOperandClasses[Rec] = &Classes.front();
1331 for (Record *Rec : AsmOperands) {
1332 ClassInfo *CI = AsmOperandClasses[Rec];
1333 CI->Kind = ClassInfo::UserClass0 + Index;
1335 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1336 for (Init *I : Supers->getValues()) {
1337 DefInit *DI = dyn_cast<DefInit>(I);
1339 PrintError(Rec->getLoc(), "Invalid super class reference!");
1343 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1345 PrintError(Rec->getLoc(), "Invalid super class reference!");
1347 CI->SuperClasses.push_back(SC);
1349 CI->ClassName = Rec->getValueAsString("Name");
1350 CI->Name = "MCK_" + CI->ClassName;
1351 CI->ValueName = Rec->getName();
1353 // Get or construct the predicate method name.
1354 Init *PMName = Rec->getValueInit("PredicateMethod");
1355 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1356 CI->PredicateMethod = SI->getValue();
1358 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1359 CI->PredicateMethod = "is" + CI->ClassName;
1362 // Get or construct the render method name.
1363 Init *RMName = Rec->getValueInit("RenderMethod");
1364 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1365 CI->RenderMethod = SI->getValue();
1367 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1368 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1371 // Get the parse method name or leave it as empty.
1372 Init *PRMName = Rec->getValueInit("ParserMethod");
1373 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1374 CI->ParserMethod = SI->getValue();
1376 // Get the diagnostic type and string or leave them as empty.
1377 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1378 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1379 CI->DiagnosticType = SI->getValue();
1380 Init *DiagnosticString = Rec->getValueInit("DiagnosticString");
1381 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticString))
1382 CI->DiagnosticString = SI->getValue();
1383 // If we have a DiagnosticString, we need a DiagnosticType for use within
1385 if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1386 CI->DiagnosticType = CI->ClassName;
1388 Init *IsOptional = Rec->getValueInit("IsOptional");
1389 if (BitInit *BI = dyn_cast<BitInit>(IsOptional))
1390 CI->IsOptional = BI->getValue();
1392 // Get or construct the default method name.
1393 Init *DMName = Rec->getValueInit("DefaultMethod");
1394 if (StringInit *SI = dyn_cast<StringInit>(DMName)) {
1395 CI->DefaultMethod = SI->getValue();
1397 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1398 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1405 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1406 CodeGenTarget &target,
1407 RecordKeeper &records)
1408 : Records(records), AsmParser(asmParser), Target(target) {
1411 /// buildOperandMatchInfo - Build the necessary information to handle user
1412 /// defined operand parsing methods.
1413 void AsmMatcherInfo::buildOperandMatchInfo() {
1415 /// Map containing a mask with all operands indices that can be found for
1416 /// that class inside a instruction.
1417 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1418 OpClassMaskTy OpClassMask;
1420 for (const auto &MI : Matchables) {
1421 OpClassMask.clear();
1423 // Keep track of all operands of this instructions which belong to the
1425 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1426 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1427 if (Op.Class->ParserMethod.empty())
1429 unsigned &OperandMask = OpClassMask[Op.Class];
1430 OperandMask |= (1 << i);
1433 // Generate operand match info for each mnemonic/operand class pair.
1434 for (const auto &OCM : OpClassMask) {
1435 unsigned OpMask = OCM.second;
1436 ClassInfo *CI = OCM.first;
1437 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1443 void AsmMatcherInfo::buildInfo() {
1444 // Build information about all of the AssemblerPredicates.
1445 const std::vector<std::pair<Record *, SubtargetFeatureInfo>>
1446 &SubtargetFeaturePairs = SubtargetFeatureInfo::getAll(Records);
1447 SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),
1448 SubtargetFeaturePairs.end());
1450 for (const auto &Pair : SubtargetFeatures)
1451 DEBUG(Pair.second.dump());
1453 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1455 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
1457 // Parse the instructions; we need to do this first so that we can gather the
1458 // singleton register classes.
1459 SmallPtrSet<Record*, 16> SingletonRegisters;
1460 unsigned VariantCount = Target.getAsmParserVariantCount();
1461 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1462 Record *AsmVariant = Target.getAsmParserVariant(VC);
1463 StringRef CommentDelimiter =
1464 AsmVariant->getValueAsString("CommentDelimiter");
1465 AsmVariantInfo Variant;
1466 Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1467 Variant.TokenizingCharacters =
1468 AsmVariant->getValueAsString("TokenizingCharacters");
1469 Variant.SeparatorCharacters =
1470 AsmVariant->getValueAsString("SeparatorCharacters");
1471 Variant.BreakCharacters =
1472 AsmVariant->getValueAsString("BreakCharacters");
1473 Variant.Name = AsmVariant->getValueAsString("Name");
1474 Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1476 for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
1478 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1479 // filter the set of instructions we consider.
1480 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1483 // Ignore "codegen only" instructions.
1484 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1487 // Ignore instructions for different instructions
1488 StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
1489 if (!V.empty() && V != Variant.Name)
1492 auto II = llvm::make_unique<MatchableInfo>(*CGI);
1494 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1496 // Ignore instructions which shouldn't be matched and diagnose invalid
1497 // instruction definitions with an error.
1498 if (!II->validate(CommentDelimiter, true))
1501 Matchables.push_back(std::move(II));
1504 // Parse all of the InstAlias definitions and stick them in the list of
1506 std::vector<Record*> AllInstAliases =
1507 Records.getAllDerivedDefinitions("InstAlias");
1508 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1509 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1510 Variant.AsmVariantNo,
1513 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1514 // filter the set of instruction aliases we consider, based on the target
1516 if (!StringRef(Alias->ResultInst->TheDef->getName())
1517 .startswith( MatchPrefix))
1520 StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");
1521 if (!V.empty() && V != Variant.Name)
1524 auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
1526 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1528 // Validate the alias definitions.
1529 II->validate(CommentDelimiter, false);
1531 Matchables.push_back(std::move(II));
1535 // Build info for the register classes.
1536 buildRegisterClasses(SingletonRegisters);
1538 // Build info for the user defined assembly operand classes.
1539 buildOperandClasses();
1541 // Build the information about matchables, now that we have fully formed
1543 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1544 for (auto &II : Matchables) {
1545 // Parse the tokens after the mnemonic.
1546 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1547 // don't precompute the loop bound.
1548 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1549 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1550 StringRef Token = Op.Token;
1552 // Check for singleton registers.
1553 if (Record *RegRecord = Op.SingletonReg) {
1554 Op.Class = RegisterClasses[RegRecord];
1555 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1556 "Unexpected class for singleton register");
1560 // Check for simple tokens.
1561 if (Token[0] != '$') {
1562 Op.Class = getTokenClass(Token);
1566 if (Token.size() > 1 && isdigit(Token[1])) {
1567 Op.Class = getTokenClass(Token);
1571 // Otherwise this is an operand reference.
1572 StringRef OperandName;
1573 if (Token[1] == '{')
1574 OperandName = Token.substr(2, Token.size() - 3);
1576 OperandName = Token.substr(1);
1578 if (II->DefRec.is<const CodeGenInstruction*>())
1579 buildInstructionOperandReference(II.get(), OperandName, i);
1581 buildAliasOperandReference(II.get(), OperandName, Op);
1584 if (II->DefRec.is<const CodeGenInstruction*>()) {
1585 II->buildInstructionResultOperands();
1586 // If the instruction has a two-operand alias, build up the
1587 // matchable here. We'll add them in bulk at the end to avoid
1588 // confusing this loop.
1589 StringRef Constraint =
1590 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1591 if (Constraint != "") {
1592 // Start by making a copy of the original matchable.
1593 auto AliasII = llvm::make_unique<MatchableInfo>(*II);
1595 // Adjust it to be a two-operand alias.
1596 AliasII->formTwoOperandAlias(Constraint);
1598 // Add the alias to the matchables list.
1599 NewMatchables.push_back(std::move(AliasII));
1602 II->buildAliasResultOperands();
1604 if (!NewMatchables.empty())
1605 Matchables.insert(Matchables.end(),
1606 std::make_move_iterator(NewMatchables.begin()),
1607 std::make_move_iterator(NewMatchables.end()));
1609 // Process token alias definitions and set up the associated superclass
1611 std::vector<Record*> AllTokenAliases =
1612 Records.getAllDerivedDefinitions("TokenAlias");
1613 for (Record *Rec : AllTokenAliases) {
1614 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1615 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1616 if (FromClass == ToClass)
1617 PrintFatalError(Rec->getLoc(),
1618 "error: Destination value identical to source value.");
1619 FromClass->SuperClasses.push_back(ToClass);
1622 // Reorder classes so that classes precede super classes.
1625 #ifdef EXPENSIVE_CHECKS
1626 // Verify that the table is sorted and operator < works transitively.
1627 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1628 for (auto J = I; J != E; ++J) {
1630 assert(I == J || !J->isSubsetOf(*I));
1636 /// buildInstructionOperandReference - The specified operand is a reference to a
1637 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1638 void AsmMatcherInfo::
1639 buildInstructionOperandReference(MatchableInfo *II,
1640 StringRef OperandName,
1641 unsigned AsmOpIdx) {
1642 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1643 const CGIOperandList &Operands = CGI.Operands;
1644 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1646 // Map this token to an operand.
1648 if (!Operands.hasOperandNamed(OperandName, Idx))
1649 PrintFatalError(II->TheDef->getLoc(),
1650 "error: unable to find operand: '" + OperandName + "'");
1652 // If the instruction operand has multiple suboperands, but the parser
1653 // match class for the asm operand is still the default "ImmAsmOperand",
1654 // then handle each suboperand separately.
1655 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1656 Record *Rec = Operands[Idx].Rec;
1657 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1658 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1659 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1660 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1661 StringRef Token = Op->Token; // save this in case Op gets moved
1662 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1663 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1664 NewAsmOp.SubOpIdx = SI;
1665 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1667 // Replace Op with first suboperand.
1668 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1673 // Set up the operand class.
1674 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1676 // If the named operand is tied, canonicalize it to the untied operand.
1677 // For example, something like:
1678 // (outs GPR:$dst), (ins GPR:$src)
1679 // with an asmstring of
1681 // we want to canonicalize to:
1683 // so that we know how to provide the $dst operand when filling in the result.
1685 if (Operands[Idx].MINumOperands == 1)
1686 OITied = Operands[Idx].getTiedRegister();
1688 // The tied operand index is an MIOperand index, find the operand that
1690 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1691 OperandName = Operands[Idx.first].Name;
1692 Op->SubOpIdx = Idx.second;
1695 Op->SrcOpName = OperandName;
1698 /// buildAliasOperandReference - When parsing an operand reference out of the
1699 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1700 /// operand reference is by looking it up in the result pattern definition.
1701 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1702 StringRef OperandName,
1703 MatchableInfo::AsmOperand &Op) {
1704 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1706 // Set up the operand class.
1707 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1708 if (CGA.ResultOperands[i].isRecord() &&
1709 CGA.ResultOperands[i].getName() == OperandName) {
1710 // It's safe to go with the first one we find, because CodeGenInstAlias
1711 // validates that all operands with the same name have the same record.
1712 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1713 // Use the match class from the Alias definition, not the
1714 // destination instruction, as we may have an immediate that's
1715 // being munged by the match class.
1716 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1718 Op.SrcOpName = OperandName;
1722 PrintFatalError(II->TheDef->getLoc(),
1723 "error: unable to find operand: '" + OperandName + "'");
1726 void MatchableInfo::buildInstructionResultOperands() {
1727 const CodeGenInstruction *ResultInst = getResultInst();
1729 // Loop over all operands of the result instruction, determining how to
1731 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1732 // If this is a tied operand, just copy from the previously handled operand.
1734 if (OpInfo.MINumOperands == 1)
1735 TiedOp = OpInfo.getTiedRegister();
1737 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1741 // Find out what operand from the asmparser this MCInst operand comes from.
1742 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1743 if (OpInfo.Name.empty() || SrcOperand == -1) {
1744 // This may happen for operands that are tied to a suboperand of a
1745 // complex operand. Simply use a dummy value here; nobody should
1746 // use this operand slot.
1747 // FIXME: The long term goal is for the MCOperand list to not contain
1748 // tied operands at all.
1749 ResOperands.push_back(ResOperand::getImmOp(0));
1753 // Check if the one AsmOperand populates the entire operand.
1754 unsigned NumOperands = OpInfo.MINumOperands;
1755 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1756 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1760 // Add a separate ResOperand for each suboperand.
1761 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1762 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1763 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1764 "unexpected AsmOperands for suboperands");
1765 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1770 void MatchableInfo::buildAliasResultOperands() {
1771 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1772 const CodeGenInstruction *ResultInst = getResultInst();
1774 // Loop over all operands of the result instruction, determining how to
1776 unsigned AliasOpNo = 0;
1777 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1778 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1779 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1781 // If this is a tied operand, just copy from the previously handled operand.
1783 if (OpInfo->MINumOperands == 1)
1784 TiedOp = OpInfo->getTiedRegister();
1786 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1790 // Handle all the suboperands for this operand.
1791 const std::string &OpName = OpInfo->Name;
1792 for ( ; AliasOpNo < LastOpNo &&
1793 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1794 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1796 // Find out what operand from the asmparser that this MCInst operand
1798 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1799 case CodeGenInstAlias::ResultOperand::K_Record: {
1800 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1801 int SrcOperand = findAsmOperand(Name, SubIdx);
1802 if (SrcOperand == -1)
1803 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1804 TheDef->getName() + "' has operand '" + OpName +
1805 "' that doesn't appear in asm string!");
1806 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1807 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1811 case CodeGenInstAlias::ResultOperand::K_Imm: {
1812 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1813 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1816 case CodeGenInstAlias::ResultOperand::K_Reg: {
1817 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1818 ResOperands.push_back(ResOperand::getRegOp(Reg));
1827 getConverterOperandID(const std::string &Name,
1828 SmallSetVector<CachedHashString, 16> &Table,
1830 IsNew = Table.insert(CachedHashString(Name));
1832 unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();
1834 assert(ID < Table.size());
1839 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1840 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1841 bool HasMnemonicFirst, bool HasOptionalOperands,
1843 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
1844 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
1845 std::vector<std::vector<uint8_t> > ConversionTable;
1846 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1848 // TargetOperandClass - This is the target's operand class, like X86Operand.
1849 std::string TargetOperandClass = Target.getName().str() + "Operand";
1851 // Write the convert function to a separate stream, so we can drop it after
1852 // the enum. We'll build up the conversion handlers for the individual
1853 // operand types opportunistically as we encounter them.
1854 std::string ConvertFnBody;
1855 raw_string_ostream CvtOS(ConvertFnBody);
1856 // Start the unified conversion function.
1857 if (HasOptionalOperands) {
1858 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1859 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1860 << "unsigned Opcode,\n"
1861 << " const OperandVector &Operands,\n"
1862 << " const SmallBitVector &OptionalOperandsMask) {\n";
1864 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1865 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1866 << "unsigned Opcode,\n"
1867 << " const OperandVector &Operands) {\n";
1869 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
1870 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
1871 if (HasOptionalOperands) {
1872 size_t MaxNumOperands = 0;
1873 for (const auto &MI : Infos) {
1874 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
1876 CvtOS << " unsigned DefaultsOffset[" << (MaxNumOperands + 1)
1878 CvtOS << " assert(OptionalOperandsMask.size() == " << (MaxNumOperands)
1880 CvtOS << " for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)
1882 CvtOS << " DefaultsOffset[i + 1] = NumDefaults;\n";
1883 CvtOS << " NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";
1886 CvtOS << " unsigned OpIdx;\n";
1887 CvtOS << " Inst.setOpcode(Opcode);\n";
1888 CvtOS << " for (const uint8_t *p = Converter; *p; p+= 2) {\n";
1889 if (HasOptionalOperands) {
1890 CvtOS << " OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
1892 CvtOS << " OpIdx = *(p + 1);\n";
1894 CvtOS << " switch (*p) {\n";
1895 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
1896 CvtOS << " case CVT_Reg:\n";
1897 CvtOS << " static_cast<" << TargetOperandClass
1898 << "&>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
1899 CvtOS << " break;\n";
1900 CvtOS << " case CVT_Tied:\n";
1901 CvtOS << " Inst.addOperand(Inst.getOperand(OpIdx));\n";
1902 CvtOS << " break;\n";
1904 std::string OperandFnBody;
1905 raw_string_ostream OpOS(OperandFnBody);
1906 // Start the operand number lookup function.
1907 OpOS << "void " << Target.getName() << ClassName << "::\n"
1908 << "convertToMapAndConstraints(unsigned Kind,\n";
1910 OpOS << "const OperandVector &Operands) {\n"
1911 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1912 << " unsigned NumMCOperands = 0;\n"
1913 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1914 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1915 << " switch (*p) {\n"
1916 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1917 << " case CVT_Reg:\n"
1918 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1919 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1920 << " ++NumMCOperands;\n"
1922 << " case CVT_Tied:\n"
1923 << " ++NumMCOperands;\n"
1926 // Pre-populate the operand conversion kinds with the standard always
1927 // available entries.
1928 OperandConversionKinds.insert(CachedHashString("CVT_Done"));
1929 OperandConversionKinds.insert(CachedHashString("CVT_Reg"));
1930 OperandConversionKinds.insert(CachedHashString("CVT_Tied"));
1931 enum { CVT_Done, CVT_Reg, CVT_Tied };
1933 for (auto &II : Infos) {
1934 // Check if we have a custom match function.
1935 StringRef AsmMatchConverter =
1936 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1937 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1938 std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
1939 II->ConversionFnKind = Signature;
1941 // Check if we have already generated this signature.
1942 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
1945 // Remember this converter for the kind enum.
1946 unsigned KindID = OperandConversionKinds.size();
1947 OperandConversionKinds.insert(
1948 CachedHashString("CVT_" + getEnumNameForToken(AsmMatchConverter)));
1950 // Add the converter row for this instruction.
1951 ConversionTable.emplace_back();
1952 ConversionTable.back().push_back(KindID);
1953 ConversionTable.back().push_back(CVT_Done);
1955 // Add the handler to the conversion driver function.
1956 CvtOS << " case CVT_"
1957 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1958 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1961 // FIXME: Handle the operand number lookup for custom match functions.
1965 // Build the conversion function signature.
1966 std::string Signature = "Convert";
1968 std::vector<uint8_t> ConversionRow;
1970 // Compute the convert enum and the case body.
1971 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1973 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1974 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1976 // Generate code to populate each result operand.
1977 switch (OpInfo.Kind) {
1978 case MatchableInfo::ResOperand::RenderAsmOperand: {
1979 // This comes from something we parsed.
1980 const MatchableInfo::AsmOperand &Op =
1981 II->AsmOperands[OpInfo.AsmOperandNum];
1983 // Registers are always converted the same, don't duplicate the
1984 // conversion function based on them.
1987 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1989 Signature += utostr(OpInfo.MINumOperands);
1990 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1992 // Add the conversion kind, if necessary, and get the associated ID
1993 // the index of its entry in the vector).
1994 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1995 Op.Class->RenderMethod);
1996 if (Op.Class->IsOptional) {
1997 // For optional operands we must also care about DefaultMethod
1998 assert(HasOptionalOperands);
1999 Name += "_" + Op.Class->DefaultMethod;
2001 Name = getEnumNameForToken(Name);
2003 bool IsNewConverter = false;
2004 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2007 // Add the operand entry to the instruction kind conversion row.
2008 ConversionRow.push_back(ID);
2009 ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);
2011 if (!IsNewConverter)
2014 // This is a new operand kind. Add a handler for it to the
2015 // converter driver.
2016 CvtOS << " case " << Name << ":\n";
2017 if (Op.Class->IsOptional) {
2018 // If optional operand is not present in actual instruction then we
2019 // should call its DefaultMethod before RenderMethod
2020 assert(HasOptionalOperands);
2021 CvtOS << " if (OptionalOperandsMask[*(p + 1) - 1]) {\n"
2022 << " " << Op.Class->DefaultMethod << "()"
2023 << "->" << Op.Class->RenderMethod << "(Inst, "
2024 << OpInfo.MINumOperands << ");\n"
2026 << " static_cast<" << TargetOperandClass
2027 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
2028 << "(Inst, " << OpInfo.MINumOperands << ");\n"
2031 CvtOS << " static_cast<" << TargetOperandClass
2032 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
2033 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2035 CvtOS << " break;\n";
2037 // Add a handler for the operand number lookup.
2038 OpOS << " case " << Name << ":\n"
2039 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2041 if (Op.Class->isRegisterClass())
2042 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2044 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2045 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2049 case MatchableInfo::ResOperand::TiedOperand: {
2050 // If this operand is tied to a previous one, just copy the MCInst
2051 // operand from the earlier one.We can only tie single MCOperand values.
2052 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2053 unsigned TiedOp = OpInfo.TiedOperandNum;
2054 assert(i > TiedOp && "Tied operand precedes its target!");
2055 Signature += "__Tie" + utostr(TiedOp);
2056 ConversionRow.push_back(CVT_Tied);
2057 ConversionRow.push_back(TiedOp);
2060 case MatchableInfo::ResOperand::ImmOperand: {
2061 int64_t Val = OpInfo.ImmVal;
2062 std::string Ty = "imm_" + itostr(Val);
2063 Ty = getEnumNameForToken(Ty);
2064 Signature += "__" + Ty;
2066 std::string Name = "CVT_" + Ty;
2067 bool IsNewConverter = false;
2068 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2070 // Add the operand entry to the instruction kind conversion row.
2071 ConversionRow.push_back(ID);
2072 ConversionRow.push_back(0);
2074 if (!IsNewConverter)
2077 CvtOS << " case " << Name << ":\n"
2078 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2081 OpOS << " case " << Name << ":\n"
2082 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2083 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2084 << " ++NumMCOperands;\n"
2088 case MatchableInfo::ResOperand::RegOperand: {
2089 std::string Reg, Name;
2090 if (!OpInfo.Register) {
2094 Reg = getQualifiedName(OpInfo.Register);
2095 Name = "reg" + OpInfo.Register->getName().str();
2097 Signature += "__" + Name;
2098 Name = "CVT_" + Name;
2099 bool IsNewConverter = false;
2100 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2102 // Add the operand entry to the instruction kind conversion row.
2103 ConversionRow.push_back(ID);
2104 ConversionRow.push_back(0);
2106 if (!IsNewConverter)
2108 CvtOS << " case " << Name << ":\n"
2109 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
2112 OpOS << " case " << Name << ":\n"
2113 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2114 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2115 << " ++NumMCOperands;\n"
2121 // If there were no operands, add to the signature to that effect
2122 if (Signature == "Convert")
2123 Signature += "_NoOperands";
2125 II->ConversionFnKind = Signature;
2127 // Save the signature. If we already have it, don't add a new row
2129 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
2132 // Add the row to the table.
2133 ConversionTable.push_back(std::move(ConversionRow));
2136 // Finish up the converter driver function.
2137 CvtOS << " }\n }\n}\n\n";
2139 // Finish up the operand number lookup function.
2140 OpOS << " }\n }\n}\n\n";
2142 OS << "namespace {\n";
2144 // Output the operand conversion kind enum.
2145 OS << "enum OperatorConversionKind {\n";
2146 for (const auto &Converter : OperandConversionKinds)
2147 OS << " " << Converter << ",\n";
2148 OS << " CVT_NUM_CONVERTERS\n";
2151 // Output the instruction conversion kind enum.
2152 OS << "enum InstructionConversionKind {\n";
2153 for (const auto &Signature : InstructionConversionKinds)
2154 OS << " " << Signature << ",\n";
2155 OS << " CVT_NUM_SIGNATURES\n";
2158 OS << "} // end anonymous namespace\n\n";
2160 // Output the conversion table.
2161 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2162 << MaxRowLength << "] = {\n";
2164 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2165 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2166 OS << " // " << InstructionConversionKinds[Row] << "\n";
2168 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2169 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2170 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2171 OS << "CVT_Done },\n";
2176 // Spit out the conversion driver function.
2179 // Spit out the operand number lookup function.
2183 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2184 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2185 std::forward_list<ClassInfo> &Infos,
2187 OS << "namespace {\n\n";
2189 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2190 << "/// instruction matching.\n";
2191 OS << "enum MatchClassKind {\n";
2192 OS << " InvalidMatchClass = 0,\n";
2193 OS << " OptionalMatchClass = 1,\n";
2194 ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;
2195 StringRef LastName = "OptionalMatchClass";
2196 for (const auto &CI : Infos) {
2197 if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {
2198 OS << " MCK_LAST_TOKEN = " << LastName << ",\n";
2199 } else if (LastKind < ClassInfo::UserClass0 &&
2200 CI.Kind >= ClassInfo::UserClass0) {
2201 OS << " MCK_LAST_REGISTER = " << LastName << ",\n";
2203 LastKind = (ClassInfo::ClassInfoKind)CI.Kind;
2206 OS << " " << CI.Name << ", // ";
2207 if (CI.Kind == ClassInfo::Token) {
2208 OS << "'" << CI.ValueName << "'\n";
2209 } else if (CI.isRegisterClass()) {
2210 if (!CI.ValueName.empty())
2211 OS << "register class '" << CI.ValueName << "'\n";
2213 OS << "derived register class\n";
2215 OS << "user defined class '" << CI.ValueName << "'\n";
2218 OS << " NumMatchClassKinds\n";
2224 /// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be
2225 /// used when an assembly operand does not match the expected operand class.
2226 static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &OS) {
2227 // If the target does not use DiagnosticString for any operands, don't emit
2228 // an unused function.
2230 Info.Classes.begin(), Info.Classes.end(),
2231 [](const ClassInfo &CI) { return CI.DiagnosticString.empty(); }))
2234 OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
2235 << "AsmParser::" << Info.Target.getName()
2236 << "MatchResultTy MatchResult) {\n";
2237 OS << " switch (MatchResult) {\n";
2239 for (const auto &CI: Info.Classes) {
2240 if (!CI.DiagnosticString.empty()) {
2241 assert(!CI.DiagnosticType.empty() &&
2242 "DiagnosticString set without DiagnosticType");
2243 OS << " case " << Info.Target.getName()
2244 << "AsmParser::Match_" << CI.DiagnosticType << ":\n";
2245 OS << " return \"" << CI.DiagnosticString << "\";\n";
2249 OS << " default:\n";
2250 OS << " return nullptr;\n";
2256 static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
2257 OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
2258 "RegisterClass) {\n";
2259 if (std::none_of(Info.Classes.begin(), Info.Classes.end(),
2260 [](const ClassInfo &CI) {
2261 return CI.isRegisterClass() && !CI.DiagnosticType.empty();
2263 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2265 OS << " switch (RegisterClass) {\n";
2266 for (const auto &CI: Info.Classes) {
2267 if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {
2268 OS << " case " << CI.Name << ":\n";
2269 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2270 << CI.DiagnosticType << ";\n";
2274 OS << " default:\n";
2275 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2282 /// emitValidateOperandClass - Emit the function to validate an operand class.
2283 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2285 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2286 << "MatchClassKind Kind) {\n";
2287 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2288 << Info.Target.getName() << "Operand&)GOp;\n";
2290 // The InvalidMatchClass is not to match any operand.
2291 OS << " if (Kind == InvalidMatchClass)\n";
2292 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2294 // Check for Token operands first.
2295 // FIXME: Use a more specific diagnostic type.
2296 OS << " if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)\n";
2297 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2298 << " MCTargetAsmParser::Match_Success :\n"
2299 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2301 // Check the user classes. We don't care what order since we're only
2302 // actually matching against one of them.
2303 OS << " switch (Kind) {\n"
2304 " default: break;\n";
2305 for (const auto &CI : Info.Classes) {
2306 if (!CI.isUserClass())
2309 OS << " // '" << CI.ClassName << "' class\n";
2310 OS << " case " << CI.Name << ":\n";
2311 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2312 OS << " return MCTargetAsmParser::Match_Success;\n";
2313 if (!CI.DiagnosticType.empty())
2314 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2315 << CI.DiagnosticType << ";\n";
2319 OS << " } // end switch (Kind)\n\n";
2321 // Check for register operands, including sub-classes.
2322 OS << " if (Operand.isReg()) {\n";
2323 OS << " MatchClassKind OpKind;\n";
2324 OS << " switch (Operand.getReg()) {\n";
2325 OS << " default: OpKind = InvalidMatchClass; break;\n";
2326 for (const auto &RC : Info.RegisterClasses)
2327 OS << " case " << RC.first->getValueAsString("Namespace") << "::"
2328 << RC.first->getName() << ": OpKind = " << RC.second->Name
2331 OS << " return isSubclass(OpKind, Kind) ? "
2332 << "(unsigned)MCTargetAsmParser::Match_Success :\n "
2333 << " getDiagKindFromRegisterClass(Kind);\n }\n\n";
2335 // Expected operand is a register, but actual is not.
2336 OS << " if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";
2337 OS << " return getDiagKindFromRegisterClass(Kind);\n\n";
2339 // Generic fallthrough match failure case for operands that don't have
2340 // specialized diagnostic types.
2341 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2345 /// emitIsSubclass - Emit the subclass predicate function.
2346 static void emitIsSubclass(CodeGenTarget &Target,
2347 std::forward_list<ClassInfo> &Infos,
2349 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2350 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2351 OS << " if (A == B)\n";
2352 OS << " return true;\n\n";
2354 bool EmittedSwitch = false;
2355 for (const auto &A : Infos) {
2356 std::vector<StringRef> SuperClasses;
2358 SuperClasses.push_back("OptionalMatchClass");
2359 for (const auto &B : Infos) {
2360 if (&A != &B && A.isSubsetOf(B))
2361 SuperClasses.push_back(B.Name);
2364 if (SuperClasses.empty())
2367 // If this is the first SuperClass, emit the switch header.
2368 if (!EmittedSwitch) {
2369 OS << " switch (A) {\n";
2370 OS << " default:\n";
2371 OS << " return false;\n";
2372 EmittedSwitch = true;
2375 OS << "\n case " << A.Name << ":\n";
2377 if (SuperClasses.size() == 1) {
2378 OS << " return B == " << SuperClasses.back() << ";\n";
2382 if (!SuperClasses.empty()) {
2383 OS << " switch (B) {\n";
2384 OS << " default: return false;\n";
2385 for (StringRef SC : SuperClasses)
2386 OS << " case " << SC << ": return true;\n";
2389 // No case statement to emit
2390 OS << " return false;\n";
2394 // If there were case statements emitted into the string stream write the
2399 OS << " return false;\n";
2404 /// emitMatchTokenString - Emit the function to match a token string to the
2405 /// appropriate match class value.
2406 static void emitMatchTokenString(CodeGenTarget &Target,
2407 std::forward_list<ClassInfo> &Infos,
2409 // Construct the match list.
2410 std::vector<StringMatcher::StringPair> Matches;
2411 for (const auto &CI : Infos) {
2412 if (CI.Kind == ClassInfo::Token)
2413 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2416 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2418 StringMatcher("Name", Matches, OS).Emit();
2420 OS << " return InvalidMatchClass;\n";
2424 /// emitMatchRegisterName - Emit the function to match a string to the target
2425 /// specific register enum.
2426 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2428 // Construct the match list.
2429 std::vector<StringMatcher::StringPair> Matches;
2430 const auto &Regs = Target.getRegBank().getRegisters();
2431 for (const CodeGenRegister &Reg : Regs) {
2432 if (Reg.TheDef->getValueAsString("AsmName").empty())
2435 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2436 "return " + utostr(Reg.EnumValue) + ";");
2439 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2441 bool IgnoreDuplicates =
2442 AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
2443 StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
2445 OS << " return 0;\n";
2449 /// Emit the function to match a string to the target
2450 /// specific register enum.
2451 static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
2453 // Construct the match list.
2454 std::vector<StringMatcher::StringPair> Matches;
2455 const auto &Regs = Target.getRegBank().getRegisters();
2456 for (const CodeGenRegister &Reg : Regs) {
2458 auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
2460 for (auto AltName : AltNames) {
2461 AltName = StringRef(AltName).trim();
2463 // don't handle empty alternative names
2464 if (AltName.empty())
2467 Matches.emplace_back(AltName,
2468 "return " + utostr(Reg.EnumValue) + ";");
2472 OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
2474 bool IgnoreDuplicates =
2475 AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
2476 StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
2478 OS << " return 0;\n";
2482 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2483 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2484 // Get the set of diagnostic types from all of the operand classes.
2485 std::set<StringRef> Types;
2486 for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2487 if (!OpClassEntry.second->DiagnosticType.empty())
2488 Types.insert(OpClassEntry.second->DiagnosticType);
2490 for (const auto &OpClassEntry : Info.RegisterClassClasses) {
2491 if (!OpClassEntry.second->DiagnosticType.empty())
2492 Types.insert(OpClassEntry.second->DiagnosticType);
2495 if (Types.empty()) return;
2497 // Now emit the enum entries.
2498 for (StringRef Type : Types)
2499 OS << " Match_" << Type << ",\n";
2500 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2503 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2504 /// user-level name for a subtarget feature.
2505 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2506 OS << "// User-level names for subtarget features that participate in\n"
2507 << "// instruction matching.\n"
2508 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2509 if (!Info.SubtargetFeatures.empty()) {
2510 OS << " switch(Val) {\n";
2511 for (const auto &SF : Info.SubtargetFeatures) {
2512 const SubtargetFeatureInfo &SFI = SF.second;
2513 // FIXME: Totally just a placeholder name to get the algorithm working.
2514 OS << " case " << SFI.getEnumName() << ": return \""
2515 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2517 OS << " default: return \"(unknown)\";\n";
2520 // Nothing to emit, so skip the switch
2521 OS << " return \"(unknown)\";\n";
2526 static std::string GetAliasRequiredFeatures(Record *R,
2527 const AsmMatcherInfo &Info) {
2528 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2530 unsigned NumFeatures = 0;
2531 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2532 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2535 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2536 "' is not marked as an AssemblerPredicate!");
2541 Result += F->getEnumName();
2545 if (NumFeatures > 1)
2546 Result = '(' + Result + ')';
2550 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2551 std::vector<Record*> &Aliases,
2552 unsigned Indent = 0,
2553 StringRef AsmParserVariantName = StringRef()){
2554 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2555 // iteration order of the map is stable.
2556 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2558 for (Record *R : Aliases) {
2559 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2560 StringRef AsmVariantName = R->getValueAsString("AsmVariantName");
2561 if (AsmVariantName != AsmParserVariantName)
2563 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2565 if (AliasesFromMnemonic.empty())
2568 // Process each alias a "from" mnemonic at a time, building the code executed
2569 // by the string remapper.
2570 std::vector<StringMatcher::StringPair> Cases;
2571 for (const auto &AliasEntry : AliasesFromMnemonic) {
2572 const std::vector<Record*> &ToVec = AliasEntry.second;
2574 // Loop through each alias and emit code that handles each case. If there
2575 // are two instructions without predicates, emit an error. If there is one,
2577 std::string MatchCode;
2578 int AliasWithNoPredicate = -1;
2580 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2581 Record *R = ToVec[i];
2582 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2584 // If this unconditionally matches, remember it for later and diagnose
2586 if (FeatureMask.empty()) {
2587 if (AliasWithNoPredicate != -1) {
2588 // We can't have two aliases from the same mnemonic with no predicate.
2589 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2590 "two MnemonicAliases with the same 'from' mnemonic!");
2591 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2594 AliasWithNoPredicate = i;
2597 if (R->getValueAsString("ToMnemonic") == AliasEntry.first)
2598 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2600 if (!MatchCode.empty())
2601 MatchCode += "else ";
2602 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2603 MatchCode += " Mnemonic = \"";
2604 MatchCode += R->getValueAsString("ToMnemonic");
2605 MatchCode += "\";\n";
2608 if (AliasWithNoPredicate != -1) {
2609 Record *R = ToVec[AliasWithNoPredicate];
2610 if (!MatchCode.empty())
2611 MatchCode += "else\n ";
2612 MatchCode += "Mnemonic = \"";
2613 MatchCode += R->getValueAsString("ToMnemonic");
2614 MatchCode += "\";\n";
2617 MatchCode += "return;";
2619 Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
2621 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2624 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2625 /// emit a function for them and return true, otherwise return false.
2626 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2627 CodeGenTarget &Target) {
2628 // Ignore aliases when match-prefix is set.
2629 if (!MatchPrefix.empty())
2632 std::vector<Record*> Aliases =
2633 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2634 if (Aliases.empty()) return false;
2636 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2637 "uint64_t Features, unsigned VariantID) {\n";
2638 OS << " switch (VariantID) {\n";
2639 unsigned VariantCount = Target.getAsmParserVariantCount();
2640 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2641 Record *AsmVariant = Target.getAsmParserVariant(VC);
2642 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2643 StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name");
2644 OS << " case " << AsmParserVariantNo << ":\n";
2645 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2646 AsmParserVariantName);
2651 // Emit aliases that apply to all variants.
2652 emitMnemonicAliasVariant(OS, Info, Aliases);
2659 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2660 const AsmMatcherInfo &Info, StringRef ClassName,
2661 StringToOffsetTable &StringTable,
2662 unsigned MaxMnemonicIndex, bool HasMnemonicFirst) {
2663 unsigned MaxMask = 0;
2664 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2665 MaxMask |= OMI.OperandMask;
2668 // Emit the static custom operand parsing table;
2669 OS << "namespace {\n";
2670 OS << " struct OperandMatchEntry {\n";
2671 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
2672 << " RequiredFeatures;\n";
2673 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2675 OS << " " << getMinimalTypeForRange(std::distance(
2676 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2677 OS << " " << getMinimalTypeForRange(MaxMask)
2678 << " OperandMask;\n\n";
2679 OS << " StringRef getMnemonic() const {\n";
2680 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2681 OS << " MnemonicTable[Mnemonic]);\n";
2685 OS << " // Predicate for searching for an opcode.\n";
2686 OS << " struct LessOpcodeOperand {\n";
2687 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2688 OS << " return LHS.getMnemonic() < RHS;\n";
2690 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2691 OS << " return LHS < RHS.getMnemonic();\n";
2693 OS << " bool operator()(const OperandMatchEntry &LHS,";
2694 OS << " const OperandMatchEntry &RHS) {\n";
2695 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2699 OS << "} // end anonymous namespace.\n\n";
2701 OS << "static const OperandMatchEntry OperandMatchTable["
2702 << Info.OperandMatchInfo.size() << "] = {\n";
2704 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2705 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2706 const MatchableInfo &II = *OMI.MI;
2710 // Write the required features mask.
2711 if (!II.RequiredFeatures.empty()) {
2712 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2714 OS << II.RequiredFeatures[i]->getEnumName();
2719 // Store a pascal-style length byte in the mnemonic.
2720 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2721 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2722 << " /* " << II.Mnemonic << " */, ";
2726 OS << ", " << OMI.OperandMask;
2728 bool printComma = false;
2729 for (int i = 0, e = 31; i !=e; ++i)
2730 if (OMI.OperandMask & (1 << i)) {
2742 // Emit the operand class switch to call the correct custom parser for
2743 // the found operand class.
2744 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2745 << "tryCustomParseOperand(OperandVector"
2746 << " &Operands,\n unsigned MCK) {\n\n"
2747 << " switch(MCK) {\n";
2749 for (const auto &CI : Info.Classes) {
2750 if (CI.ParserMethod.empty())
2752 OS << " case " << CI.Name << ":\n"
2753 << " return " << CI.ParserMethod << "(Operands);\n";
2756 OS << " default:\n";
2757 OS << " return MatchOperand_NoMatch;\n";
2759 OS << " return MatchOperand_NoMatch;\n";
2762 // Emit the static custom operand parser. This code is very similar with
2763 // the other matcher. Also use MatchResultTy here just in case we go for
2764 // a better error handling.
2765 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2766 << "MatchOperandParserImpl(OperandVector"
2767 << " &Operands,\n StringRef Mnemonic,\n"
2768 << " bool ParseForAllFeatures) {\n";
2770 // Emit code to get the available features.
2771 OS << " // Get the current feature set.\n";
2772 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2774 OS << " // Get the next operand index.\n";
2775 OS << " unsigned NextOpNum = Operands.size()"
2776 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
2778 // Emit code to search the table.
2779 OS << " // Search the table.\n";
2780 if (HasMnemonicFirst) {
2781 OS << " auto MnemonicRange =\n";
2782 OS << " std::equal_range(std::begin(OperandMatchTable), "
2783 "std::end(OperandMatchTable),\n";
2784 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2786 OS << " auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
2787 " std::end(OperandMatchTable));\n";
2788 OS << " if (!Mnemonic.empty())\n";
2789 OS << " MnemonicRange =\n";
2790 OS << " std::equal_range(std::begin(OperandMatchTable), "
2791 "std::end(OperandMatchTable),\n";
2792 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2795 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2796 OS << " return MatchOperand_NoMatch;\n\n";
2798 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2799 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2801 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2802 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2804 // Emit check that the required features are available.
2805 OS << " // check if the available features match\n";
2806 OS << " if (!ParseForAllFeatures && (AvailableFeatures & "
2807 "it->RequiredFeatures) != it->RequiredFeatures)\n";
2808 OS << " continue;\n\n";
2810 // Emit check to ensure the operand number matches.
2811 OS << " // check if the operand in question has a custom parser.\n";
2812 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2813 OS << " continue;\n\n";
2815 // Emit call to the custom parser method
2816 OS << " // call custom parse method to handle the operand\n";
2817 OS << " OperandMatchResultTy Result = ";
2818 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2819 OS << " if (Result != MatchOperand_NoMatch)\n";
2820 OS << " return Result;\n";
2823 OS << " // Okay, we had no match.\n";
2824 OS << " return MatchOperand_NoMatch;\n";
2828 static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
2829 unsigned VariantCount) {
2830 OS << "static std::string " << Target.getName()
2831 << "MnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {\n";
2833 OS << " return \"\";";
2835 OS << " const unsigned MaxEditDist = 2;\n";
2836 OS << " std::vector<StringRef> Candidates;\n";
2837 OS << " StringRef Prev = \"\";\n\n";
2839 OS << " // Find the appropriate table for this asm variant.\n";
2840 OS << " const MatchEntry *Start, *End;\n";
2841 OS << " switch (VariantID) {\n";
2842 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2843 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2844 Record *AsmVariant = Target.getAsmParserVariant(VC);
2845 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2846 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2847 << "); End = std::end(MatchTable" << VC << "); break;\n";
2850 OS << " for (auto I = Start; I < End; I++) {\n";
2851 OS << " // Ignore unsupported instructions.\n";
2852 OS << " if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)\n";
2853 OS << " continue;\n";
2855 OS << " StringRef T = I->getMnemonic();\n";
2856 OS << " // Avoid recomputing the edit distance for the same string.\n";
2857 OS << " if (T.equals(Prev))\n";
2858 OS << " continue;\n";
2860 OS << " Prev = T;\n";
2861 OS << " unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";
2862 OS << " if (Dist <= MaxEditDist)\n";
2863 OS << " Candidates.push_back(T);\n";
2866 OS << " if (Candidates.empty())\n";
2867 OS << " return \"\";\n";
2869 OS << " std::string Res = \", did you mean: \";\n";
2870 OS << " unsigned i = 0;\n";
2871 OS << " for( ; i < Candidates.size() - 1; i++)\n";
2872 OS << " Res += Candidates[i].str() + \", \";\n";
2873 OS << " return Res + Candidates[i].str() + \"?\";\n";
2880 // Emit a function mapping match classes to strings, for debugging.
2881 static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
2883 OS << "#ifndef NDEBUG\n";
2884 OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";
2885 OS << " switch (Kind) {\n";
2887 OS << " case InvalidMatchClass: return \"InvalidMatchClass\";\n";
2888 OS << " case OptionalMatchClass: return \"OptionalMatchClass\";\n";
2889 for (const auto &CI : Infos) {
2890 OS << " case " << CI.Name << ": return \"" << CI.Name << "\";\n";
2892 OS << " case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";
2895 OS << " llvm_unreachable(\"unhandled MatchClassKind!\");\n";
2897 OS << "#endif // NDEBUG\n";
2900 void AsmMatcherEmitter::run(raw_ostream &OS) {
2901 CodeGenTarget Target(Records);
2902 Record *AsmParser = Target.getAsmParser();
2903 StringRef ClassName = AsmParser->getValueAsString("AsmParserClassName");
2905 // Compute the information on the instructions to match.
2906 AsmMatcherInfo Info(AsmParser, Target, Records);
2909 // Sort the instruction table using the partial order on classes. We use
2910 // stable_sort to ensure that ambiguous instructions are still
2911 // deterministically ordered.
2912 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2913 [](const std::unique_ptr<MatchableInfo> &a,
2914 const std::unique_ptr<MatchableInfo> &b){
2917 #ifdef EXPENSIVE_CHECKS
2918 // Verify that the table is sorted and operator < works transitively.
2919 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2921 for (auto J = I; J != E; ++J) {
2922 assert(!(**J < **I));
2927 DEBUG_WITH_TYPE("instruction_info", {
2928 for (const auto &MI : Info.Matchables)
2932 // Check for ambiguous matchables.
2933 DEBUG_WITH_TYPE("ambiguous_instrs", {
2934 unsigned NumAmbiguous = 0;
2935 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2937 for (auto J = std::next(I); J != E; ++J) {
2938 const MatchableInfo &A = **I;
2939 const MatchableInfo &B = **J;
2941 if (A.couldMatchAmbiguouslyWith(B)) {
2942 errs() << "warning: ambiguous matchables:\n";
2944 errs() << "\nis incomparable with:\n";
2952 errs() << "warning: " << NumAmbiguous
2953 << " ambiguous matchables!\n";
2956 // Compute the information on the custom operand parsing.
2957 Info.buildOperandMatchInfo();
2959 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
2960 bool HasOptionalOperands = Info.hasOptionalOperands();
2961 bool ReportMultipleNearMisses =
2962 AsmParser->getValueAsBit("ReportMultipleNearMisses");
2964 // Write the output.
2966 // Information for the class declaration.
2967 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2968 OS << "#undef GET_ASSEMBLER_HEADER\n";
2969 OS << " // This should be included into the middle of the declaration of\n";
2970 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2971 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2972 if (HasOptionalOperands) {
2973 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2974 << "unsigned Opcode,\n"
2975 << " const OperandVector &Operands,\n"
2976 << " const SmallBitVector &OptionalOperandsMask);\n";
2978 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2979 << "unsigned Opcode,\n"
2980 << " const OperandVector &Operands);\n";
2982 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2983 OS << " const OperandVector &Operands) override;\n";
2984 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2985 << " MCInst &Inst,\n";
2986 if (ReportMultipleNearMisses)
2987 OS << " SmallVectorImpl<NearMissInfo> *NearMisses,\n";
2989 OS << " uint64_t &ErrorInfo,\n";
2990 OS << " bool matchingInlineAsm,\n"
2991 << " unsigned VariantID = 0);\n";
2993 if (!Info.OperandMatchInfo.empty()) {
2994 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2995 OS << " OperandVector &Operands,\n";
2996 OS << " StringRef Mnemonic,\n";
2997 OS << " bool ParseForAllFeatures = false);\n";
2999 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
3000 OS << " OperandVector &Operands,\n";
3001 OS << " unsigned MCK);\n\n";
3004 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
3006 // Emit the operand match diagnostic enum names.
3007 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
3008 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3009 emitOperandDiagnosticTypes(Info, OS);
3010 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3012 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
3013 OS << "#undef GET_REGISTER_MATCHER\n\n";
3015 // Emit the subtarget feature enumeration.
3016 SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
3017 Info.SubtargetFeatures, OS);
3019 // Emit the function to match a register name to number.
3020 // This should be omitted for Mips target
3021 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
3022 emitMatchRegisterName(Target, AsmParser, OS);
3024 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))
3025 emitMatchRegisterAltName(Target, AsmParser, OS);
3027 OS << "#endif // GET_REGISTER_MATCHER\n\n";
3029 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
3030 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
3032 // Generate the helper function to get the names for subtarget features.
3033 emitGetSubtargetFeatureName(Info, OS);
3035 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
3037 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
3038 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
3040 // Generate the function that remaps for mnemonic aliases.
3041 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
3043 // Generate the convertToMCInst function to convert operands into an MCInst.
3044 // Also, generate the convertToMapAndConstraints function for MS-style inline
3045 // assembly. The latter doesn't actually generate a MCInst.
3046 emitConvertFuncs(Target, ClassName, Info.Matchables, HasMnemonicFirst,
3047 HasOptionalOperands, OS);
3049 // Emit the enumeration for classes which participate in matching.
3050 emitMatchClassEnumeration(Target, Info.Classes, OS);
3052 // Emit a function to get the user-visible string to describe an operand
3053 // match failure in diagnostics.
3054 emitOperandMatchErrorDiagStrings(Info, OS);
3056 // Emit a function to map register classes to operand match failure codes.
3057 emitRegisterMatchErrorFunc(Info, OS);
3059 // Emit the routine to match token strings to their match class.
3060 emitMatchTokenString(Target, Info.Classes, OS);
3062 // Emit the subclass predicate routine.
3063 emitIsSubclass(Target, Info.Classes, OS);
3065 // Emit the routine to validate an operand against a match class.
3066 emitValidateOperandClass(Info, OS);
3068 emitMatchClassKindNames(Info.Classes, OS);
3070 // Emit the available features compute function.
3071 SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
3072 Info.Target.getName(), ClassName, "ComputeAvailableFeatures",
3073 Info.SubtargetFeatures, OS);
3075 StringToOffsetTable StringTable;
3077 size_t MaxNumOperands = 0;
3078 unsigned MaxMnemonicIndex = 0;
3079 bool HasDeprecation = false;
3080 for (const auto &MI : Info.Matchables) {
3081 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
3082 HasDeprecation |= MI->HasDeprecation;
3084 // Store a pascal-style length byte in the mnemonic.
3085 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
3086 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
3087 StringTable.GetOrAddStringOffset(LenMnemonic, false));
3090 OS << "static const char *const MnemonicTable =\n";
3091 StringTable.EmitString(OS);
3094 // Emit the static match table; unused classes get initialized to 0 which is
3095 // guaranteed to be InvalidMatchClass.
3097 // FIXME: We can reduce the size of this table very easily. First, we change
3098 // it so that store the kinds in separate bit-fields for each index, which
3099 // only needs to be the max width used for classes at that index (we also need
3100 // to reject based on this during classification). If we then make sure to
3101 // order the match kinds appropriately (putting mnemonics last), then we
3102 // should only end up using a few bits for each class, especially the ones
3103 // following the mnemonic.
3104 OS << "namespace {\n";
3105 OS << " struct MatchEntry {\n";
3106 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
3108 OS << " uint16_t Opcode;\n";
3109 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
3111 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
3112 << " RequiredFeatures;\n";
3113 OS << " " << getMinimalTypeForRange(
3114 std::distance(Info.Classes.begin(), Info.Classes.end()))
3115 << " Classes[" << MaxNumOperands << "];\n";
3116 OS << " StringRef getMnemonic() const {\n";
3117 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
3118 OS << " MnemonicTable[Mnemonic]);\n";
3122 OS << " // Predicate for searching for an opcode.\n";
3123 OS << " struct LessOpcode {\n";
3124 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
3125 OS << " return LHS.getMnemonic() < RHS;\n";
3127 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
3128 OS << " return LHS < RHS.getMnemonic();\n";
3130 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
3131 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
3135 OS << "} // end anonymous namespace.\n\n";
3137 unsigned VariantCount = Target.getAsmParserVariantCount();
3138 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3139 Record *AsmVariant = Target.getAsmParserVariant(VC);
3140 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3142 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
3144 for (const auto &MI : Info.Matchables) {
3145 if (MI->AsmVariantID != AsmVariantNo)
3148 // Store a pascal-style length byte in the mnemonic.
3149 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
3150 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
3151 << " /* " << MI->Mnemonic << " */, "
3152 << Target.getInstNamespace() << "::"
3153 << MI->getResultInst()->TheDef->getName() << ", "
3154 << MI->ConversionFnKind << ", ";
3156 // Write the required features mask.
3157 if (!MI->RequiredFeatures.empty()) {
3158 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
3160 OS << MI->RequiredFeatures[i]->getEnumName();
3166 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
3167 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
3170 OS << Op.Class->Name;
3178 OS << "#include \"llvm/Support/Debug.h\"\n";
3179 OS << "#include \"llvm/Support/Format.h\"\n\n";
3181 // Finally, build the match function.
3182 OS << "unsigned " << Target.getName() << ClassName << "::\n"
3183 << "MatchInstructionImpl(const OperandVector &Operands,\n";
3184 OS << " MCInst &Inst,\n";
3185 if (ReportMultipleNearMisses)
3186 OS << " SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3188 OS << " uint64_t &ErrorInfo,\n";
3189 OS << " bool matchingInlineAsm, unsigned VariantID) {\n";
3191 if (!ReportMultipleNearMisses) {
3192 OS << " // Eliminate obvious mismatches.\n";
3193 OS << " if (Operands.size() > "
3194 << (MaxNumOperands + HasMnemonicFirst) << ") {\n";
3195 OS << " ErrorInfo = "
3196 << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3197 OS << " return Match_InvalidOperand;\n";
3201 // Emit code to get the available features.
3202 OS << " // Get the current feature set.\n";
3203 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
3205 OS << " // Get the instruction mnemonic, which is the first token.\n";
3206 if (HasMnemonicFirst) {
3207 OS << " StringRef Mnemonic = ((" << Target.getName()
3208 << "Operand&)*Operands[0]).getToken();\n\n";
3210 OS << " StringRef Mnemonic;\n";
3211 OS << " if (Operands[0]->isToken())\n";
3212 OS << " Mnemonic = ((" << Target.getName()
3213 << "Operand&)*Operands[0]).getToken();\n\n";
3216 if (HasMnemonicAliases) {
3217 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3218 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3221 // Emit code to compute the class list for this operand vector.
3222 if (!ReportMultipleNearMisses) {
3223 OS << " // Some state to try to produce better error messages.\n";
3224 OS << " bool HadMatchOtherThanFeatures = false;\n";
3225 OS << " bool HadMatchOtherThanPredicate = false;\n";
3226 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3227 OS << " uint64_t MissingFeatures = ~0ULL;\n";
3228 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3229 OS << " // wrong for all instances of the instruction.\n";
3230 OS << " ErrorInfo = ~0ULL;\n";
3233 if (HasOptionalOperands) {
3234 OS << " SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n";
3237 // Emit code to search the table.
3238 OS << " // Find the appropriate table for this asm variant.\n";
3239 OS << " const MatchEntry *Start, *End;\n";
3240 OS << " switch (VariantID) {\n";
3241 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3242 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3243 Record *AsmVariant = Target.getAsmParserVariant(VC);
3244 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3245 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3246 << "); End = std::end(MatchTable" << VC << "); break;\n";
3250 OS << " // Search the table.\n";
3251 if (HasMnemonicFirst) {
3252 OS << " auto MnemonicRange = "
3253 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3255 OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
3256 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3257 OS << " if (!Mnemonic.empty())\n";
3258 OS << " MnemonicRange = "
3259 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3262 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" <<\n"
3263 << " std::distance(MnemonicRange.first, MnemonicRange.second) << \n"
3264 << " \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
3266 OS << " // Return a more specific error code if no mnemonics match.\n";
3267 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3268 OS << " return Match_MnemonicFail;\n\n";
3270 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3271 << "*ie = MnemonicRange.second;\n";
3272 OS << " it != ie; ++it) {\n";
3273 OS << " bool HasRequiredFeatures =\n";
3274 OS << " (AvailableFeatures & it->RequiredFeatures) == "
3275 "it->RequiredFeatures;\n";
3276 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match opcode \"\n";
3277 OS << " << MII.getName(it->Opcode) << \"\\n\");\n";
3279 if (ReportMultipleNearMisses) {
3280 OS << " // Some state to record ways in which this instruction did not match.\n";
3281 OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
3282 OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
3283 OS << " NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n";
3284 OS << " NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n";
3285 OS << " bool MultipleInvalidOperands = false;\n";
3288 if (HasMnemonicFirst) {
3289 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3290 OS << " assert(Mnemonic == it->getMnemonic());\n";
3293 // Emit check that the subclasses match.
3294 if (!ReportMultipleNearMisses)
3295 OS << " bool OperandsValid = true;\n";
3296 if (HasOptionalOperands) {
3297 OS << " OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";
3299 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3300 << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3301 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3302 OS << " auto Formal = "
3303 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3304 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3305 OS << " dbgs() << \" Matching formal operand class \" << getMatchClassName(Formal)\n";
3306 OS << " << \" against actual operand at index \" << ActualIdx);\n";
3307 OS << " if (ActualIdx < Operands.size())\n";
3308 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
3309 OS << " Operands[ActualIdx]->print(dbgs()); dbgs() << \"): \");\n";
3311 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
3312 OS << " if (ActualIdx >= Operands.size()) {\n";
3313 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand index out of range \");\n";
3314 if (ReportMultipleNearMisses) {
3315 OS << " bool ThisOperandValid = (Formal == " <<"InvalidMatchClass) || "
3316 "isSubclass(Formal, OptionalMatchClass);\n";
3317 OS << " if (!ThisOperandValid) {\n";
3318 OS << " if (!OperandNearMiss) {\n";
3319 OS << " // Record info about match failure for later use.\n";
3320 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording too-few-operands near miss\\n\");\n";
3321 OS << " OperandNearMiss =\n";
3322 OS << " NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n";
3323 OS << " } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n";
3324 OS << " // If more than one operand is invalid, give up on this match entry.\n";
3325 OS << " DEBUG_WITH_TYPE(\n";
3326 OS << " \"asm-matcher\",\n";
3327 OS << " dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n";
3328 OS << " MultipleInvalidOperands = true;\n";
3331 OS << " } else {\n";
3332 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal operand not required\\n\");\n";
3335 OS << " continue;\n";
3337 OS << " OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);\n";
3338 OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n";
3339 if (HasOptionalOperands) {
3340 OS << " OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
3346 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
3347 OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n";
3348 OS << " if (Diag == Match_Success) {\n";
3349 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3350 OS << " dbgs() << \"match success using generic matcher\\n\");\n";
3351 OS << " ++ActualIdx;\n";
3352 OS << " continue;\n";
3354 OS << " // If the generic handler indicates an invalid operand\n";
3355 OS << " // failure, check for a special case.\n";
3356 OS << " if (Diag != Match_Success) {\n";
3357 OS << " unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);\n";
3358 OS << " if (TargetDiag == Match_Success) {\n";
3359 OS << " DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3360 OS << " dbgs() << \"match success using target matcher\\n\");\n";
3361 OS << " ++ActualIdx;\n";
3362 OS << " continue;\n";
3364 OS << " // If the target matcher returned a specific error code use\n";
3365 OS << " // that, else use the one from the generic matcher.\n";
3366 OS << " if (TargetDiag != Match_InvalidOperand && "
3367 "HasRequiredFeatures)\n";
3368 OS << " Diag = TargetDiag;\n";
3370 OS << " // If current formal operand wasn't matched and it is optional\n"
3371 << " // then try to match next formal operand\n";
3372 OS << " if (Diag == Match_InvalidOperand "
3373 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
3374 if (HasOptionalOperands) {
3375 OS << " OptionalOperandsMask.set(FormalIdx);\n";
3377 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring optional operand\\n\");\n";
3378 OS << " continue;\n";
3381 if (ReportMultipleNearMisses) {
3382 OS << " if (!OperandNearMiss) {\n";
3383 OS << " // If this is the first invalid operand we have seen, record some\n";
3384 OS << " // information about it.\n";
3385 OS << " DEBUG_WITH_TYPE(\n";
3386 OS << " \"asm-matcher\",\n";
3388 OS << " << \"operand match failed, recording near-miss with diag code \"\n";
3389 OS << " << Diag << \"\\n\");\n";
3390 OS << " OperandNearMiss =\n";
3391 OS << " NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);\n";
3392 OS << " ++ActualIdx;\n";
3393 OS << " } else {\n";
3394 OS << " // If more than one operand is invalid, give up on this match entry.\n";
3395 OS << " DEBUG_WITH_TYPE(\n";
3396 OS << " \"asm-matcher\",\n";
3397 OS << " dbgs() << \"second operand mismatch, skipping this opcode\\n\");\n";
3398 OS << " MultipleInvalidOperands = true;\n";
3403 OS << " // If this operand is broken for all of the instances of this\n";
3404 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3405 OS << " // If we already had a match that only failed due to a\n";
3406 OS << " // target predicate, that diagnostic is preferred.\n";
3407 OS << " if (!HadMatchOtherThanPredicate &&\n";
3408 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
3409 OS << " if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
3410 "!= Match_InvalidOperand))\n";
3411 OS << " RetCode = Diag;\n";
3412 OS << " ErrorInfo = ActualIdx;\n";
3414 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3415 OS << " OperandsValid = false;\n";
3420 if (ReportMultipleNearMisses)
3421 OS << " if (MultipleInvalidOperands) {\n";
3423 OS << " if (!OperandsValid) {\n";
3424 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3425 OS << " \"operand mismatches, ignoring \"\n";
3426 OS << " \"this opcode\\n\");\n";
3427 OS << " continue;\n";
3430 // Emit check that the required features are available.
3431 OS << " if (!HasRequiredFeatures) {\n";
3432 if (!ReportMultipleNearMisses)
3433 OS << " HadMatchOtherThanFeatures = true;\n";
3434 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
3435 "~AvailableFeatures;\n";
3436 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target features: \"\n";
3437 OS << " << format_hex(NewMissingFeatures, 18)\n";
3438 OS << " << \"\\n\");\n";
3439 if (ReportMultipleNearMisses) {
3440 OS << " FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
3442 OS << " if (countPopulation(NewMissingFeatures) <=\n"
3443 " countPopulation(MissingFeatures))\n";
3444 OS << " MissingFeatures = NewMissingFeatures;\n";
3445 OS << " continue;\n";
3449 OS << " Inst.clear();\n\n";
3450 OS << " Inst.setOpcode(it->Opcode);\n";
3451 // Verify the instruction with the target-specific match predicate function.
3452 OS << " // We have a potential match but have not rendered the operands.\n"
3453 << " // Check the target predicate to handle any context sensitive\n"
3454 " // constraints.\n"
3455 << " // For example, Ties that are referenced multiple times must be\n"
3456 " // checked here to ensure the input is the same for each match\n"
3457 " // constraints. If we leave it any later the ties will have been\n"
3458 " // canonicalized\n"
3459 << " unsigned MatchResult;\n"
3460 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
3461 "Operands)) != Match_Success) {\n"
3462 << " Inst.clear();\n";
3463 OS << " DEBUG_WITH_TYPE(\n";
3464 OS << " \"asm-matcher\",\n";
3465 OS << " dbgs() << \"Early target match predicate failed with diag code \"\n";
3466 OS << " << MatchResult << \"\\n\");\n";
3467 if (ReportMultipleNearMisses) {
3468 OS << " EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n";
3470 OS << " RetCode = MatchResult;\n"
3471 << " HadMatchOtherThanPredicate = true;\n"
3476 if (ReportMultipleNearMisses) {
3477 OS << " // If we did not successfully match the operands, then we can't convert to\n";
3478 OS << " // an MCInst, so bail out on this instruction variant now.\n";
3479 OS << " if (OperandNearMiss) {\n";
3480 OS << " // If the operand mismatch was the only problem, reprrt it as a near-miss.\n";
3481 OS << " if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {\n";
3482 OS << " DEBUG_WITH_TYPE(\n";
3483 OS << " \"asm-matcher\",\n";
3485 OS << " << \"Opcode result: one mismatched operand, adding near-miss\\n\");\n";
3486 OS << " NearMisses->push_back(OperandNearMiss);\n";
3487 OS << " } else {\n";
3488 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3489 OS << " \"types of mismatch, so not \"\n";
3490 OS << " \"reporting near-miss\\n\");\n";
3492 OS << " continue;\n";
3496 OS << " if (matchingInlineAsm) {\n";
3497 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3498 OS << " return Match_Success;\n";
3500 OS << " // We have selected a definite instruction, convert the parsed\n"
3501 << " // operands into the appropriate MCInst.\n";
3502 if (HasOptionalOperands) {
3503 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
3504 << " OptionalOperandsMask);\n";
3506 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3510 // Verify the instruction with the target-specific match predicate function.
3511 OS << " // We have a potential match. Check the target predicate to\n"
3512 << " // handle any context sensitive constraints.\n"
3513 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3514 << " Match_Success) {\n"
3515 << " DEBUG_WITH_TYPE(\"asm-matcher\",\n"
3516 << " dbgs() << \"Target match predicate failed with diag code \"\n"
3517 << " << MatchResult << \"\\n\");\n"
3518 << " Inst.clear();\n";
3519 if (ReportMultipleNearMisses) {
3520 OS << " LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n";
3522 OS << " RetCode = MatchResult;\n"
3523 << " HadMatchOtherThanPredicate = true;\n"
3528 if (ReportMultipleNearMisses) {
3529 OS << " int NumNearMisses = ((int)(bool)OperandNearMiss +\n";
3530 OS << " (int)(bool)FeaturesNearMiss +\n";
3531 OS << " (int)(bool)EarlyPredicateNearMiss +\n";
3532 OS << " (int)(bool)LatePredicateNearMiss);\n";
3533 OS << " if (NumNearMisses == 1) {\n";
3534 OS << " // We had exactly one type of near-miss, so add that to the list.\n";
3535 OS << " assert(!OperandNearMiss && \"OperandNearMiss was handled earlier\");\n";
3536 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: found one type of \"\n";
3537 OS << " \"mismatch, so reporting a \"\n";
3538 OS << " \"near-miss\\n\");\n";
3539 OS << " if (NearMisses && FeaturesNearMiss)\n";
3540 OS << " NearMisses->push_back(FeaturesNearMiss);\n";
3541 OS << " else if (NearMisses && EarlyPredicateNearMiss)\n";
3542 OS << " NearMisses->push_back(EarlyPredicateNearMiss);\n";
3543 OS << " else if (NearMisses && LatePredicateNearMiss)\n";
3544 OS << " NearMisses->push_back(LatePredicateNearMiss);\n";
3546 OS << " continue;\n";
3547 OS << " } else if (NumNearMisses > 1) {\n";
3548 OS << " // This instruction missed in more than one way, so ignore it.\n";
3549 OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3550 OS << " \"types of mismatch, so not \"\n";
3551 OS << " \"reporting near-miss\\n\");\n";
3552 OS << " continue;\n";
3556 // Call the post-processing function, if used.
3557 StringRef InsnCleanupFn = AsmParser->getValueAsString("AsmParserInstCleanup");
3558 if (!InsnCleanupFn.empty())
3559 OS << " " << InsnCleanupFn << "(Inst);\n";
3561 if (HasDeprecation) {
3562 OS << " std::string Info;\n";
3563 OS << " if (!getParser().getTargetParser().\n";
3564 OS << " getTargetOptions().MCNoDeprecatedWarn &&\n";
3565 OS << " MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
3566 OS << " SMLoc Loc = ((" << Target.getName()
3567 << "Operand&)*Operands[0]).getStartLoc();\n";
3568 OS << " getParser().Warning(Loc, Info, None);\n";
3572 OS << " DEBUG_WITH_TYPE(\n";
3573 OS << " \"asm-matcher\",\n";
3574 OS << " dbgs() << \"Opcode result: complete match, selecting this opcode\\n\");\n";
3575 OS << " return Match_Success;\n";
3578 if (ReportMultipleNearMisses) {
3579 OS << " // No instruction variants matched exactly.\n";
3580 OS << " return Match_NearMisses;\n";
3582 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3583 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3584 OS << " return RetCode;\n\n";
3585 OS << " // Missing feature matches return which features were missing\n";
3586 OS << " ErrorInfo = MissingFeatures;\n";
3587 OS << " return Match_MissingFeature;\n";
3591 if (!Info.OperandMatchInfo.empty())
3592 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3593 MaxMnemonicIndex, HasMnemonicFirst);
3595 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3597 OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";
3598 OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";
3600 emitMnemonicSpellChecker(OS, Target, VariantCount);
3602 OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
3607 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3608 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3609 AsmMatcherEmitter(RK).run(OS);
3612 } // end namespace llvm