1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "SubtargetFeatureInfo.h"
102 #include "llvm/ADT/CachedHashString.h"
103 #include "llvm/ADT/PointerUnion.h"
104 #include "llvm/ADT/STLExtras.h"
105 #include "llvm/ADT/SmallPtrSet.h"
106 #include "llvm/ADT/SmallVector.h"
107 #include "llvm/ADT/StringExtras.h"
108 #include "llvm/Support/CommandLine.h"
109 #include "llvm/Support/Debug.h"
110 #include "llvm/Support/ErrorHandling.h"
111 #include "llvm/TableGen/Error.h"
112 #include "llvm/TableGen/Record.h"
113 #include "llvm/TableGen/StringMatcher.h"
114 #include "llvm/TableGen/StringToOffsetTable.h"
115 #include "llvm/TableGen/TableGenBackend.h"
118 #include <forward_list>
122 using namespace llvm;
124 #define DEBUG_TYPE "asm-matcher-emitter"
126 static cl::opt<std::string>
127 MatchPrefix("match-prefix", cl::init(""),
128 cl::desc("Only match instructions with the given prefix"));
131 class AsmMatcherInfo;
133 // Register sets are used as keys in some second-order sets TableGen creates
134 // when generating its data structures. This means that the order of two
135 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
136 // can even affect compiler output (at least seen in diagnostics produced when
137 // all matches fail). So we use a type that sorts them consistently.
138 typedef std::set<Record*, LessRecordByID> RegisterSet;
140 class AsmMatcherEmitter {
141 RecordKeeper &Records;
143 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
145 void run(raw_ostream &o);
148 /// ClassInfo - Helper class for storing the information about a particular
149 /// class of operands which can be matched.
152 /// Invalid kind, for use as a sentinel value.
155 /// The class for a particular token.
158 /// The (first) register class, subsequent register classes are
159 /// RegisterClass0+1, and so on.
162 /// The (first) user defined class, subsequent user defined classes are
163 /// UserClass0+1, and so on.
167 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
168 /// N) for the Nth user defined class.
171 /// SuperClasses - The super classes of this class. Note that for simplicities
172 /// sake user operands only record their immediate super class, while register
173 /// operands include all superclasses.
174 std::vector<ClassInfo*> SuperClasses;
176 /// Name - The full class name, suitable for use in an enum.
179 /// ClassName - The unadorned generic name for this class (e.g., Token).
180 std::string ClassName;
182 /// ValueName - The name of the value this class represents; for a token this
183 /// is the literal token string, for an operand it is the TableGen class (or
184 /// empty if this is a derived class).
185 std::string ValueName;
187 /// PredicateMethod - The name of the operand method to test whether the
188 /// operand matches this class; this is not valid for Token or register kinds.
189 std::string PredicateMethod;
191 /// RenderMethod - The name of the operand method to add this operand to an
192 /// MCInst; this is not valid for Token or register kinds.
193 std::string RenderMethod;
195 /// ParserMethod - The name of the operand method to do a target specific
196 /// parsing on the operand.
197 std::string ParserMethod;
199 /// For register classes: the records for all the registers in this class.
200 RegisterSet Registers;
202 /// For custom match classes: the diagnostic kind for when the predicate fails.
203 std::string DiagnosticType;
205 /// Is this operand optional and not always required.
208 /// DefaultMethod - The name of the method that returns the default operand
209 /// for optional operand
210 std::string DefaultMethod;
213 /// isRegisterClass() - Check if this is a register class.
214 bool isRegisterClass() const {
215 return Kind >= RegisterClass0 && Kind < UserClass0;
218 /// isUserClass() - Check if this is a user defined class.
219 bool isUserClass() const {
220 return Kind >= UserClass0;
223 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
224 /// are related if they are in the same class hierarchy.
225 bool isRelatedTo(const ClassInfo &RHS) const {
226 // Tokens are only related to tokens.
227 if (Kind == Token || RHS.Kind == Token)
228 return Kind == Token && RHS.Kind == Token;
230 // Registers classes are only related to registers classes, and only if
231 // their intersection is non-empty.
232 if (isRegisterClass() || RHS.isRegisterClass()) {
233 if (!isRegisterClass() || !RHS.isRegisterClass())
237 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
238 std::set_intersection(Registers.begin(), Registers.end(),
239 RHS.Registers.begin(), RHS.Registers.end(),
240 II, LessRecordByID());
245 // Otherwise we have two users operands; they are related if they are in the
246 // same class hierarchy.
248 // FIXME: This is an oversimplification, they should only be related if they
249 // intersect, however we don't have that information.
250 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
251 const ClassInfo *Root = this;
252 while (!Root->SuperClasses.empty())
253 Root = Root->SuperClasses.front();
255 const ClassInfo *RHSRoot = &RHS;
256 while (!RHSRoot->SuperClasses.empty())
257 RHSRoot = RHSRoot->SuperClasses.front();
259 return Root == RHSRoot;
262 /// isSubsetOf - Test whether this class is a subset of \p RHS.
263 bool isSubsetOf(const ClassInfo &RHS) const {
264 // This is a subset of RHS if it is the same class...
268 // ... or if any of its super classes are a subset of RHS.
269 for (const ClassInfo *CI : SuperClasses)
270 if (CI->isSubsetOf(RHS))
276 int getTreeDepth() const {
278 const ClassInfo *Root = this;
279 while (!Root->SuperClasses.empty()) {
281 Root = Root->SuperClasses.front();
286 const ClassInfo *findRoot() const {
287 const ClassInfo *Root = this;
288 while (!Root->SuperClasses.empty())
289 Root = Root->SuperClasses.front();
293 /// Compare two classes. This does not produce a total ordering, but does
294 /// guarantee that subclasses are sorted before their parents, and that the
295 /// ordering is transitive.
296 bool operator<(const ClassInfo &RHS) const {
300 // First, enforce the ordering between the three different types of class.
301 // Tokens sort before registers, which sort before user classes.
303 if (RHS.Kind != Token)
305 assert(RHS.Kind == Token);
306 } else if (isRegisterClass()) {
307 if (RHS.Kind == Token)
309 else if (RHS.isUserClass())
311 assert(RHS.isRegisterClass());
312 } else if (isUserClass()) {
313 if (!RHS.isUserClass())
315 assert(RHS.isUserClass());
317 llvm_unreachable("Unknown ClassInfoKind");
320 if (Kind == Token || isUserClass()) {
321 // Related tokens and user classes get sorted by depth in the inheritence
322 // tree (so that subclasses are before their parents).
323 if (isRelatedTo(RHS)) {
324 if (getTreeDepth() > RHS.getTreeDepth())
326 if (getTreeDepth() < RHS.getTreeDepth())
329 // Unrelated tokens and user classes are ordered by the name of their
330 // root nodes, so that there is a consistent ordering between
331 // unconnected trees.
332 return findRoot()->ValueName < RHS.findRoot()->ValueName;
334 } else if (isRegisterClass()) {
335 // For register sets, sort by number of registers. This guarantees that
336 // a set will always sort before all of it's strict supersets.
337 if (Registers.size() != RHS.Registers.size())
338 return Registers.size() < RHS.Registers.size();
340 llvm_unreachable("Unknown ClassInfoKind");
343 // FIXME: We should be able to just return false here, as we only need a
344 // partial order (we use stable sorts, so this is deterministic) and the
345 // name of a class shouldn't be significant. However, some of the backends
346 // accidentally rely on this behaviour, so it will have to stay like this
347 // until they are fixed.
348 return ValueName < RHS.ValueName;
352 class AsmVariantInfo {
354 std::string RegisterPrefix;
355 std::string TokenizingCharacters;
356 std::string SeparatorCharacters;
357 std::string BreakCharacters;
362 /// MatchableInfo - Helper class for storing the necessary information for an
363 /// instruction or alias which is capable of being matched.
364 struct MatchableInfo {
366 /// Token - This is the token that the operand came from.
369 /// The unique class instance this operand should match.
372 /// The operand name this is, if anything.
375 /// The suboperand index within SrcOpName, or -1 for the entire operand.
378 /// Whether the token is "isolated", i.e., it is preceded and followed
380 bool IsIsolatedToken;
382 /// Register record if this token is singleton register.
383 Record *SingletonReg;
385 explicit AsmOperand(bool IsIsolatedToken, StringRef T)
386 : Token(T), Class(nullptr), SubOpIdx(-1),
387 IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
390 /// ResOperand - This represents a single operand in the result instruction
391 /// generated by the match. In cases (like addressing modes) where a single
392 /// assembler operand expands to multiple MCOperands, this represents the
393 /// single assembler operand, not the MCOperand.
396 /// RenderAsmOperand - This represents an operand result that is
397 /// generated by calling the render method on the assembly operand. The
398 /// corresponding AsmOperand is specified by AsmOperandNum.
401 /// TiedOperand - This represents a result operand that is a duplicate of
402 /// a previous result operand.
405 /// ImmOperand - This represents an immediate value that is dumped into
409 /// RegOperand - This represents a fixed register that is dumped in.
414 /// This is the operand # in the AsmOperands list that this should be
416 unsigned AsmOperandNum;
418 /// TiedOperandNum - This is the (earlier) result operand that should be
420 unsigned TiedOperandNum;
422 /// ImmVal - This is the immediate value added to the instruction.
425 /// Register - This is the register record.
429 /// MINumOperands - The number of MCInst operands populated by this
431 unsigned MINumOperands;
433 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
435 X.Kind = RenderAsmOperand;
436 X.AsmOperandNum = AsmOpNum;
437 X.MINumOperands = NumOperands;
441 static ResOperand getTiedOp(unsigned TiedOperandNum) {
443 X.Kind = TiedOperand;
444 X.TiedOperandNum = TiedOperandNum;
449 static ResOperand getImmOp(int64_t Val) {
457 static ResOperand getRegOp(Record *Reg) {
466 /// AsmVariantID - Target's assembly syntax variant no.
469 /// AsmString - The assembly string for this instruction (with variants
470 /// removed), e.g. "movsx $src, $dst".
471 std::string AsmString;
473 /// TheDef - This is the definition of the instruction or InstAlias that this
474 /// matchable came from.
475 Record *const TheDef;
477 /// DefRec - This is the definition that it came from.
478 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
480 const CodeGenInstruction *getResultInst() const {
481 if (DefRec.is<const CodeGenInstruction*>())
482 return DefRec.get<const CodeGenInstruction*>();
483 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
486 /// ResOperands - This is the operand list that should be built for the result
488 SmallVector<ResOperand, 8> ResOperands;
490 /// Mnemonic - This is the first token of the matched instruction, its
494 /// AsmOperands - The textual operands that this instruction matches,
495 /// annotated with a class and where in the OperandList they were defined.
496 /// This directly corresponds to the tokenized AsmString after the mnemonic is
498 SmallVector<AsmOperand, 8> AsmOperands;
500 /// Predicates - The required subtarget features to match this instruction.
501 SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
503 /// ConversionFnKind - The enum value which is passed to the generated
504 /// convertToMCInst to convert parsed operands into an MCInst for this
506 std::string ConversionFnKind;
508 /// If this instruction is deprecated in some form.
511 /// If this is an alias, this is use to determine whether or not to using
512 /// the conversion function defined by the instruction's AsmMatchConverter
513 /// or to use the function generated by the alias.
514 bool UseInstAsmMatchConverter;
516 MatchableInfo(const CodeGenInstruction &CGI)
517 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
518 UseInstAsmMatchConverter(true) {
521 MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
522 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
523 DefRec(Alias.release()),
524 UseInstAsmMatchConverter(
525 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
528 // Could remove this and the dtor if PointerUnion supported unique_ptr
529 // elements with a dynamic failure/assertion (like the one below) in the case
530 // where it was copied while being in an owning state.
531 MatchableInfo(const MatchableInfo &RHS)
532 : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
533 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
534 Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
535 RequiredFeatures(RHS.RequiredFeatures),
536 ConversionFnKind(RHS.ConversionFnKind),
537 HasDeprecation(RHS.HasDeprecation),
538 UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
539 assert(!DefRec.is<const CodeGenInstAlias *>());
543 delete DefRec.dyn_cast<const CodeGenInstAlias*>();
546 // Two-operand aliases clone from the main matchable, but mark the second
547 // operand as a tied operand of the first for purposes of the assembler.
548 void formTwoOperandAlias(StringRef Constraint);
550 void initialize(const AsmMatcherInfo &Info,
551 SmallPtrSetImpl<Record*> &SingletonRegisters,
552 AsmVariantInfo const &Variant,
553 bool HasMnemonicFirst);
555 /// validate - Return true if this matchable is a valid thing to match against
556 /// and perform a bunch of validity checking.
557 bool validate(StringRef CommentDelimiter, bool Hack) const;
559 /// findAsmOperand - Find the AsmOperand with the specified name and
560 /// suboperand index.
561 int findAsmOperand(StringRef N, int SubOpIdx) const {
562 auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {
563 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
565 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
568 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
569 /// This does not check the suboperand index.
570 int findAsmOperandNamed(StringRef N) const {
571 auto I = find_if(AsmOperands,
572 [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
573 return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
576 void buildInstructionResultOperands();
577 void buildAliasResultOperands();
579 /// operator< - Compare two matchables.
580 bool operator<(const MatchableInfo &RHS) const {
581 // The primary comparator is the instruction mnemonic.
582 if (int Cmp = Mnemonic.compare(RHS.Mnemonic))
585 if (AsmOperands.size() != RHS.AsmOperands.size())
586 return AsmOperands.size() < RHS.AsmOperands.size();
588 // Compare lexicographically by operand. The matcher validates that other
589 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
590 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
591 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
593 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
597 // Give matches that require more features higher precedence. This is useful
598 // because we cannot define AssemblerPredicates with the negation of
599 // processor features. For example, ARM v6 "nop" may be either a HINT or
600 // MOV. With v6, we want to match HINT. The assembler has no way to
601 // predicate MOV under "NoV6", but HINT will always match first because it
602 // requires V6 while MOV does not.
603 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
604 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
609 /// couldMatchAmbiguouslyWith - Check whether this matchable could
610 /// ambiguously match the same set of operands as \p RHS (without being a
611 /// strictly superior match).
612 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
613 // The primary comparator is the instruction mnemonic.
614 if (Mnemonic != RHS.Mnemonic)
617 // The number of operands is unambiguous.
618 if (AsmOperands.size() != RHS.AsmOperands.size())
621 // Otherwise, make sure the ordering of the two instructions is unambiguous
622 // by checking that either (a) a token or operand kind discriminates them,
623 // or (b) the ordering among equivalent kinds is consistent.
625 // Tokens and operand kinds are unambiguous (assuming a correct target
627 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
628 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
629 AsmOperands[i].Class->Kind == ClassInfo::Token)
630 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
631 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
634 // Otherwise, this operand could commute if all operands are equivalent, or
635 // there is a pair of operands that compare less than and a pair that
636 // compare greater than.
637 bool HasLT = false, HasGT = false;
638 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
639 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
641 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
645 return HasLT == HasGT;
651 void tokenizeAsmString(AsmMatcherInfo const &Info,
652 AsmVariantInfo const &Variant);
653 void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
656 struct OperandMatchEntry {
657 unsigned OperandMask;
658 const MatchableInfo* MI;
661 static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
664 X.OperandMask = opMask;
671 class AsmMatcherInfo {
674 RecordKeeper &Records;
676 /// The tablegen AsmParser record.
679 /// Target - The target information.
680 CodeGenTarget &Target;
682 /// The classes which are needed for matching.
683 std::forward_list<ClassInfo> Classes;
685 /// The information on the matchables to match.
686 std::vector<std::unique_ptr<MatchableInfo>> Matchables;
688 /// Info for custom matching operands by user defined methods.
689 std::vector<OperandMatchEntry> OperandMatchInfo;
691 /// Map of Register records to their class information.
692 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
693 RegisterClassesTy RegisterClasses;
695 /// Map of Predicate records to their subtarget information.
696 std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
698 /// Map of AsmOperandClass records to their class information.
699 std::map<Record*, ClassInfo*> AsmOperandClasses;
702 /// Map of token to class information which has already been constructed.
703 std::map<std::string, ClassInfo*> TokenClasses;
705 /// Map of RegisterClass records to their class information.
706 std::map<Record*, ClassInfo*> RegisterClassClasses;
709 /// getTokenClass - Lookup or create the class for the given token.
710 ClassInfo *getTokenClass(StringRef Token);
712 /// getOperandClass - Lookup or create the class for the given operand.
713 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
715 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
717 /// buildRegisterClasses - Build the ClassInfo* instances for register
719 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
721 /// buildOperandClasses - Build the ClassInfo* instances for user defined
723 void buildOperandClasses();
725 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
727 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
728 MatchableInfo::AsmOperand &Op);
731 AsmMatcherInfo(Record *AsmParser,
732 CodeGenTarget &Target,
733 RecordKeeper &Records);
735 /// Construct the various tables used during matching.
738 /// buildOperandMatchInfo - Build the necessary information to handle user
739 /// defined operand parsing methods.
740 void buildOperandMatchInfo();
742 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
744 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
745 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
746 const auto &I = SubtargetFeatures.find(Def);
747 return I == SubtargetFeatures.end() ? nullptr : &I->second;
750 RecordKeeper &getRecords() const {
754 bool hasOptionalOperands() const {
755 return find_if(Classes, [](const ClassInfo &Class) {
756 return Class.IsOptional;
761 } // end anonymous namespace
763 void MatchableInfo::dump() const {
764 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
766 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
767 const AsmOperand &Op = AsmOperands[i];
768 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
769 errs() << '\"' << Op.Token << "\"\n";
773 static std::pair<StringRef, StringRef>
774 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
775 // Split via the '='.
776 std::pair<StringRef, StringRef> Ops = S.split('=');
777 if (Ops.second == "")
778 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
779 // Trim whitespace and the leading '$' on the operand names.
780 size_t start = Ops.first.find_first_of('$');
781 if (start == std::string::npos)
782 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
783 Ops.first = Ops.first.slice(start + 1, std::string::npos);
784 size_t end = Ops.first.find_last_of(" \t");
785 Ops.first = Ops.first.slice(0, end);
786 // Now the second operand.
787 start = Ops.second.find_first_of('$');
788 if (start == std::string::npos)
789 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
790 Ops.second = Ops.second.slice(start + 1, std::string::npos);
791 end = Ops.second.find_last_of(" \t");
792 Ops.first = Ops.first.slice(0, end);
796 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
797 // Figure out which operands are aliased and mark them as tied.
798 std::pair<StringRef, StringRef> Ops =
799 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
801 // Find the AsmOperands that refer to the operands we're aliasing.
802 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
803 int DstAsmOperand = findAsmOperandNamed(Ops.second);
804 if (SrcAsmOperand == -1)
805 PrintFatalError(TheDef->getLoc(),
806 "unknown source two-operand alias operand '" + Ops.first +
808 if (DstAsmOperand == -1)
809 PrintFatalError(TheDef->getLoc(),
810 "unknown destination two-operand alias operand '" +
813 // Find the ResOperand that refers to the operand we're aliasing away
814 // and update it to refer to the combined operand instead.
815 for (ResOperand &Op : ResOperands) {
816 if (Op.Kind == ResOperand::RenderAsmOperand &&
817 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
818 Op.AsmOperandNum = DstAsmOperand;
822 // Remove the AsmOperand for the alias operand.
823 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
824 // Adjust the ResOperand references to any AsmOperands that followed
825 // the one we just deleted.
826 for (ResOperand &Op : ResOperands) {
829 // Nothing to do for operands that don't reference AsmOperands.
831 case ResOperand::RenderAsmOperand:
832 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
835 case ResOperand::TiedOperand:
836 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
843 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
844 /// if present, from specified token.
846 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
847 const AsmMatcherInfo &Info,
848 StringRef RegisterPrefix) {
849 StringRef Tok = Op.Token;
851 // If this token is not an isolated token, i.e., it isn't separated from
852 // other tokens (e.g. with whitespace), don't interpret it as a register name.
853 if (!Op.IsIsolatedToken)
856 if (RegisterPrefix.empty()) {
857 std::string LoweredTok = Tok.lower();
858 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
859 Op.SingletonReg = Reg->TheDef;
863 if (!Tok.startswith(RegisterPrefix))
866 StringRef RegName = Tok.substr(RegisterPrefix.size());
867 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
868 Op.SingletonReg = Reg->TheDef;
870 // If there is no register prefix (i.e. "%" in "%eax"), then this may
871 // be some random non-register token, just ignore it.
874 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
875 SmallPtrSetImpl<Record*> &SingletonRegisters,
876 AsmVariantInfo const &Variant,
877 bool HasMnemonicFirst) {
878 AsmVariantID = Variant.AsmVariantNo;
880 CodeGenInstruction::FlattenAsmStringVariants(AsmString,
881 Variant.AsmVariantNo);
883 tokenizeAsmString(Info, Variant);
885 // The first token of the instruction is the mnemonic, which must be a
886 // simple string, not a $foo variable or a singleton register.
887 if (AsmOperands.empty())
888 PrintFatalError(TheDef->getLoc(),
889 "Instruction '" + TheDef->getName() + "' has no tokens");
891 assert(!AsmOperands[0].Token.empty());
892 if (HasMnemonicFirst) {
893 Mnemonic = AsmOperands[0].Token;
894 if (Mnemonic[0] == '$')
895 PrintFatalError(TheDef->getLoc(),
896 "Invalid instruction mnemonic '" + Mnemonic + "'!");
898 // Remove the first operand, it is tracked in the mnemonic field.
899 AsmOperands.erase(AsmOperands.begin());
900 } else if (AsmOperands[0].Token[0] != '$')
901 Mnemonic = AsmOperands[0].Token;
903 // Compute the require features.
904 for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
905 if (const SubtargetFeatureInfo *Feature =
906 Info.getSubtargetFeature(Predicate))
907 RequiredFeatures.push_back(Feature);
909 // Collect singleton registers, if used.
910 for (MatchableInfo::AsmOperand &Op : AsmOperands) {
911 extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
912 if (Record *Reg = Op.SingletonReg)
913 SingletonRegisters.insert(Reg);
916 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
918 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
921 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
924 /// Append an AsmOperand for the given substring of AsmString.
925 void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
926 AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));
929 /// tokenizeAsmString - Tokenize a simplified assembly string.
930 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
931 AsmVariantInfo const &Variant) {
932 StringRef String = AsmString;
935 bool IsIsolatedToken = true;
936 for (size_t i = 0, e = String.size(); i != e; ++i) {
937 char Char = String[i];
938 if (Variant.BreakCharacters.find(Char) != std::string::npos) {
940 addAsmOperand(String.slice(Prev, i), false);
942 IsIsolatedToken = false;
947 if (Variant.TokenizingCharacters.find(Char) != std::string::npos) {
949 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
951 IsIsolatedToken = false;
953 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
955 IsIsolatedToken = true;
958 if (Variant.SeparatorCharacters.find(Char) != std::string::npos) {
960 addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
964 IsIsolatedToken = true;
971 addAsmOperand(String.slice(Prev, i), false);
973 IsIsolatedToken = false;
976 assert(i != String.size() && "Invalid quoted character");
977 addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
979 IsIsolatedToken = false;
984 addAsmOperand(String.slice(Prev, i), false);
986 IsIsolatedToken = false;
989 // If this isn't "${", start new identifier looking like "$xxx"
990 if (i + 1 == String.size() || String[i + 1] != '{') {
995 size_t EndPos = String.find('}', i);
996 assert(EndPos != StringRef::npos &&
997 "Missing brace in operand reference!");
998 addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
1001 IsIsolatedToken = false;
1010 if (InTok && Prev != String.size())
1011 addAsmOperand(String.substr(Prev), IsIsolatedToken);
1014 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
1015 // Reject matchables with no .s string.
1016 if (AsmString.empty())
1017 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
1019 // Reject any matchables with a newline in them, they should be marked
1020 // isCodeGenOnly if they are pseudo instructions.
1021 if (AsmString.find('\n') != std::string::npos)
1022 PrintFatalError(TheDef->getLoc(),
1023 "multiline instruction is not valid for the asmparser, "
1024 "mark it isCodeGenOnly");
1026 // Remove comments from the asm string. We know that the asmstring only
1028 if (!CommentDelimiter.empty() &&
1029 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
1030 PrintFatalError(TheDef->getLoc(),
1031 "asmstring for instruction has comment character in it, "
1032 "mark it isCodeGenOnly");
1034 // Reject matchables with operand modifiers, these aren't something we can
1035 // handle, the target should be refactored to use operands instead of
1038 // Also, check for instructions which reference the operand multiple times;
1039 // this implies a constraint we would not honor.
1040 std::set<std::string> OperandNames;
1041 for (const AsmOperand &Op : AsmOperands) {
1042 StringRef Tok = Op.Token;
1043 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
1044 PrintFatalError(TheDef->getLoc(),
1045 "matchable with operand modifier '" + Tok +
1046 "' not supported by asm matcher. Mark isCodeGenOnly!");
1048 // Verify that any operand is only mentioned once.
1049 // We reject aliases and ignore instructions for now.
1050 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1052 PrintFatalError(TheDef->getLoc(),
1053 "ERROR: matchable with tied operand '" + Tok +
1054 "' can never be matched!");
1055 // FIXME: Should reject these. The ARM backend hits this with $lane in a
1056 // bunch of instructions. It is unclear what the right answer is.
1058 errs() << "warning: '" << TheDef->getName() << "': "
1059 << "ignoring instruction with tied operand '"
1069 static std::string getEnumNameForToken(StringRef Str) {
1072 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1074 case '*': Res += "_STAR_"; break;
1075 case '%': Res += "_PCT_"; break;
1076 case ':': Res += "_COLON_"; break;
1077 case '!': Res += "_EXCLAIM_"; break;
1078 case '.': Res += "_DOT_"; break;
1079 case '<': Res += "_LT_"; break;
1080 case '>': Res += "_GT_"; break;
1081 case '-': Res += "_MINUS_"; break;
1083 if ((*it >= 'A' && *it <= 'Z') ||
1084 (*it >= 'a' && *it <= 'z') ||
1085 (*it >= '0' && *it <= '9'))
1088 Res += "_" + utostr((unsigned) *it) + "_";
1095 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1096 ClassInfo *&Entry = TokenClasses[Token];
1099 Classes.emplace_front();
1100 Entry = &Classes.front();
1101 Entry->Kind = ClassInfo::Token;
1102 Entry->ClassName = "Token";
1103 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1104 Entry->ValueName = Token;
1105 Entry->PredicateMethod = "<invalid>";
1106 Entry->RenderMethod = "<invalid>";
1107 Entry->ParserMethod = "";
1108 Entry->DiagnosticType = "";
1109 Entry->IsOptional = false;
1110 Entry->DefaultMethod = "<invalid>";
1117 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1119 Record *Rec = OI.Rec;
1121 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1122 return getOperandClass(Rec, SubOpIdx);
1126 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1127 if (Rec->isSubClassOf("RegisterOperand")) {
1128 // RegisterOperand may have an associated ParserMatchClass. If it does,
1129 // use it, else just fall back to the underlying register class.
1130 const RecordVal *R = Rec->getValue("ParserMatchClass");
1131 if (!R || !R->getValue())
1132 PrintFatalError("Record `" + Rec->getName() +
1133 "' does not have a ParserMatchClass!\n");
1135 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1136 Record *MatchClass = DI->getDef();
1137 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1141 // No custom match class. Just use the register class.
1142 Record *ClassRec = Rec->getValueAsDef("RegClass");
1144 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1145 "' has no associated register class!\n");
1146 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1148 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1151 if (Rec->isSubClassOf("RegisterClass")) {
1152 if (ClassInfo *CI = RegisterClassClasses[Rec])
1154 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1157 if (!Rec->isSubClassOf("Operand"))
1158 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1159 "' does not derive from class Operand!\n");
1160 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1161 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1164 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1167 struct LessRegisterSet {
1168 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1169 // std::set<T> defines its own compariso "operator<", but it
1170 // performs a lexicographical comparison by T's innate comparison
1171 // for some reason. We don't want non-deterministic pointer
1172 // comparisons so use this instead.
1173 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1174 RHS.begin(), RHS.end(),
1179 void AsmMatcherInfo::
1180 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1181 const auto &Registers = Target.getRegBank().getRegisters();
1182 auto &RegClassList = Target.getRegBank().getRegClasses();
1184 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1186 // The register sets used for matching.
1187 RegisterSetSet RegisterSets;
1189 // Gather the defined sets.
1190 for (const CodeGenRegisterClass &RC : RegClassList)
1191 RegisterSets.insert(
1192 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1194 // Add any required singleton sets.
1195 for (Record *Rec : SingletonRegisters) {
1196 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1199 // Introduce derived sets where necessary (when a register does not determine
1200 // a unique register set class), and build the mapping of registers to the set
1201 // they should classify to.
1202 std::map<Record*, RegisterSet> RegisterMap;
1203 for (const CodeGenRegister &CGR : Registers) {
1204 // Compute the intersection of all sets containing this register.
1205 RegisterSet ContainingSet;
1207 for (const RegisterSet &RS : RegisterSets) {
1208 if (!RS.count(CGR.TheDef))
1211 if (ContainingSet.empty()) {
1217 std::swap(Tmp, ContainingSet);
1218 std::insert_iterator<RegisterSet> II(ContainingSet,
1219 ContainingSet.begin());
1220 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1224 if (!ContainingSet.empty()) {
1225 RegisterSets.insert(ContainingSet);
1226 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1230 // Construct the register classes.
1231 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1233 for (const RegisterSet &RS : RegisterSets) {
1234 Classes.emplace_front();
1235 ClassInfo *CI = &Classes.front();
1236 CI->Kind = ClassInfo::RegisterClass0 + Index;
1237 CI->ClassName = "Reg" + utostr(Index);
1238 CI->Name = "MCK_Reg" + utostr(Index);
1240 CI->PredicateMethod = ""; // unused
1241 CI->RenderMethod = "addRegOperands";
1243 // FIXME: diagnostic type.
1244 CI->DiagnosticType = "";
1245 CI->IsOptional = false;
1246 CI->DefaultMethod = ""; // unused
1247 RegisterSetClasses.insert(std::make_pair(RS, CI));
1251 // Find the superclasses; we could compute only the subgroup lattice edges,
1252 // but there isn't really a point.
1253 for (const RegisterSet &RS : RegisterSets) {
1254 ClassInfo *CI = RegisterSetClasses[RS];
1255 for (const RegisterSet &RS2 : RegisterSets)
1257 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1259 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1262 // Name the register classes which correspond to a user defined RegisterClass.
1263 for (const CodeGenRegisterClass &RC : RegClassList) {
1264 // Def will be NULL for non-user defined register classes.
1265 Record *Def = RC.getDef();
1268 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1269 RC.getOrder().end())];
1270 if (CI->ValueName.empty()) {
1271 CI->ClassName = RC.getName();
1272 CI->Name = "MCK_" + RC.getName();
1273 CI->ValueName = RC.getName();
1275 CI->ValueName = CI->ValueName + "," + RC.getName();
1277 RegisterClassClasses.insert(std::make_pair(Def, CI));
1280 // Populate the map for individual registers.
1281 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1282 ie = RegisterMap.end(); it != ie; ++it)
1283 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1285 // Name the register classes which correspond to singleton registers.
1286 for (Record *Rec : SingletonRegisters) {
1287 ClassInfo *CI = RegisterClasses[Rec];
1288 assert(CI && "Missing singleton register class info!");
1290 if (CI->ValueName.empty()) {
1291 CI->ClassName = Rec->getName();
1292 CI->Name = "MCK_" + Rec->getName().str();
1293 CI->ValueName = Rec->getName();
1295 CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1299 void AsmMatcherInfo::buildOperandClasses() {
1300 std::vector<Record*> AsmOperands =
1301 Records.getAllDerivedDefinitions("AsmOperandClass");
1303 // Pre-populate AsmOperandClasses map.
1304 for (Record *Rec : AsmOperands) {
1305 Classes.emplace_front();
1306 AsmOperandClasses[Rec] = &Classes.front();
1310 for (Record *Rec : AsmOperands) {
1311 ClassInfo *CI = AsmOperandClasses[Rec];
1312 CI->Kind = ClassInfo::UserClass0 + Index;
1314 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1315 for (Init *I : Supers->getValues()) {
1316 DefInit *DI = dyn_cast<DefInit>(I);
1318 PrintError(Rec->getLoc(), "Invalid super class reference!");
1322 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1324 PrintError(Rec->getLoc(), "Invalid super class reference!");
1326 CI->SuperClasses.push_back(SC);
1328 CI->ClassName = Rec->getValueAsString("Name");
1329 CI->Name = "MCK_" + CI->ClassName;
1330 CI->ValueName = Rec->getName();
1332 // Get or construct the predicate method name.
1333 Init *PMName = Rec->getValueInit("PredicateMethod");
1334 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1335 CI->PredicateMethod = SI->getValue();
1337 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1338 CI->PredicateMethod = "is" + CI->ClassName;
1341 // Get or construct the render method name.
1342 Init *RMName = Rec->getValueInit("RenderMethod");
1343 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1344 CI->RenderMethod = SI->getValue();
1346 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1347 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1350 // Get the parse method name or leave it as empty.
1351 Init *PRMName = Rec->getValueInit("ParserMethod");
1352 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1353 CI->ParserMethod = SI->getValue();
1355 // Get the diagnostic type or leave it as empty.
1356 // Get the parse method name or leave it as empty.
1357 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1358 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1359 CI->DiagnosticType = SI->getValue();
1361 Init *IsOptional = Rec->getValueInit("IsOptional");
1362 if (BitInit *BI = dyn_cast<BitInit>(IsOptional))
1363 CI->IsOptional = BI->getValue();
1365 // Get or construct the default method name.
1366 Init *DMName = Rec->getValueInit("DefaultMethod");
1367 if (StringInit *SI = dyn_cast<StringInit>(DMName)) {
1368 CI->DefaultMethod = SI->getValue();
1370 assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1371 CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1378 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1379 CodeGenTarget &target,
1380 RecordKeeper &records)
1381 : Records(records), AsmParser(asmParser), Target(target) {
1384 /// buildOperandMatchInfo - Build the necessary information to handle user
1385 /// defined operand parsing methods.
1386 void AsmMatcherInfo::buildOperandMatchInfo() {
1388 /// Map containing a mask with all operands indices that can be found for
1389 /// that class inside a instruction.
1390 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1391 OpClassMaskTy OpClassMask;
1393 for (const auto &MI : Matchables) {
1394 OpClassMask.clear();
1396 // Keep track of all operands of this instructions which belong to the
1398 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1399 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1400 if (Op.Class->ParserMethod.empty())
1402 unsigned &OperandMask = OpClassMask[Op.Class];
1403 OperandMask |= (1 << i);
1406 // Generate operand match info for each mnemonic/operand class pair.
1407 for (const auto &OCM : OpClassMask) {
1408 unsigned OpMask = OCM.second;
1409 ClassInfo *CI = OCM.first;
1410 OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1416 void AsmMatcherInfo::buildInfo() {
1417 // Build information about all of the AssemblerPredicates.
1418 const std::vector<std::pair<Record *, SubtargetFeatureInfo>>
1419 &SubtargetFeaturePairs = SubtargetFeatureInfo::getAll(Records);
1420 SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),
1421 SubtargetFeaturePairs.end());
1423 for (const auto &Pair : SubtargetFeatures)
1424 DEBUG(Pair.second.dump());
1426 assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
1428 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
1430 // Parse the instructions; we need to do this first so that we can gather the
1431 // singleton register classes.
1432 SmallPtrSet<Record*, 16> SingletonRegisters;
1433 unsigned VariantCount = Target.getAsmParserVariantCount();
1434 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1435 Record *AsmVariant = Target.getAsmParserVariant(VC);
1436 std::string CommentDelimiter =
1437 AsmVariant->getValueAsString("CommentDelimiter");
1438 AsmVariantInfo Variant;
1439 Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1440 Variant.TokenizingCharacters =
1441 AsmVariant->getValueAsString("TokenizingCharacters");
1442 Variant.SeparatorCharacters =
1443 AsmVariant->getValueAsString("SeparatorCharacters");
1444 Variant.BreakCharacters =
1445 AsmVariant->getValueAsString("BreakCharacters");
1446 Variant.Name = AsmVariant->getValueAsString("Name");
1447 Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1449 for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
1451 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1452 // filter the set of instructions we consider.
1453 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1456 // Ignore "codegen only" instructions.
1457 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1460 // Ignore instructions for different instructions
1461 const std::string V = CGI->TheDef->getValueAsString("AsmVariantName");
1462 if (!V.empty() && V != Variant.Name)
1465 auto II = llvm::make_unique<MatchableInfo>(*CGI);
1467 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1469 // Ignore instructions which shouldn't be matched and diagnose invalid
1470 // instruction definitions with an error.
1471 if (!II->validate(CommentDelimiter, true))
1474 Matchables.push_back(std::move(II));
1477 // Parse all of the InstAlias definitions and stick them in the list of
1479 std::vector<Record*> AllInstAliases =
1480 Records.getAllDerivedDefinitions("InstAlias");
1481 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1482 auto Alias = llvm::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1483 Variant.AsmVariantNo,
1486 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1487 // filter the set of instruction aliases we consider, based on the target
1489 if (!StringRef(Alias->ResultInst->TheDef->getName())
1490 .startswith( MatchPrefix))
1493 const std::string V = Alias->TheDef->getValueAsString("AsmVariantName");
1494 if (!V.empty() && V != Variant.Name)
1497 auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
1499 II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1501 // Validate the alias definitions.
1502 II->validate(CommentDelimiter, false);
1504 Matchables.push_back(std::move(II));
1508 // Build info for the register classes.
1509 buildRegisterClasses(SingletonRegisters);
1511 // Build info for the user defined assembly operand classes.
1512 buildOperandClasses();
1514 // Build the information about matchables, now that we have fully formed
1516 std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1517 for (auto &II : Matchables) {
1518 // Parse the tokens after the mnemonic.
1519 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1520 // don't precompute the loop bound.
1521 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1522 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1523 StringRef Token = Op.Token;
1525 // Check for singleton registers.
1526 if (Record *RegRecord = Op.SingletonReg) {
1527 Op.Class = RegisterClasses[RegRecord];
1528 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1529 "Unexpected class for singleton register");
1533 // Check for simple tokens.
1534 if (Token[0] != '$') {
1535 Op.Class = getTokenClass(Token);
1539 if (Token.size() > 1 && isdigit(Token[1])) {
1540 Op.Class = getTokenClass(Token);
1544 // Otherwise this is an operand reference.
1545 StringRef OperandName;
1546 if (Token[1] == '{')
1547 OperandName = Token.substr(2, Token.size() - 3);
1549 OperandName = Token.substr(1);
1551 if (II->DefRec.is<const CodeGenInstruction*>())
1552 buildInstructionOperandReference(II.get(), OperandName, i);
1554 buildAliasOperandReference(II.get(), OperandName, Op);
1557 if (II->DefRec.is<const CodeGenInstruction*>()) {
1558 II->buildInstructionResultOperands();
1559 // If the instruction has a two-operand alias, build up the
1560 // matchable here. We'll add them in bulk at the end to avoid
1561 // confusing this loop.
1562 std::string Constraint =
1563 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1564 if (Constraint != "") {
1565 // Start by making a copy of the original matchable.
1566 auto AliasII = llvm::make_unique<MatchableInfo>(*II);
1568 // Adjust it to be a two-operand alias.
1569 AliasII->formTwoOperandAlias(Constraint);
1571 // Add the alias to the matchables list.
1572 NewMatchables.push_back(std::move(AliasII));
1575 II->buildAliasResultOperands();
1577 if (!NewMatchables.empty())
1578 Matchables.insert(Matchables.end(),
1579 std::make_move_iterator(NewMatchables.begin()),
1580 std::make_move_iterator(NewMatchables.end()));
1582 // Process token alias definitions and set up the associated superclass
1584 std::vector<Record*> AllTokenAliases =
1585 Records.getAllDerivedDefinitions("TokenAlias");
1586 for (Record *Rec : AllTokenAliases) {
1587 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1588 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1589 if (FromClass == ToClass)
1590 PrintFatalError(Rec->getLoc(),
1591 "error: Destination value identical to source value.");
1592 FromClass->SuperClasses.push_back(ToClass);
1595 // Reorder classes so that classes precede super classes.
1598 #ifdef EXPENSIVE_CHECKS
1599 // Verify that the table is sorted and operator < works transitively.
1600 for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1601 for (auto J = I; J != E; ++J) {
1603 assert(I == J || !J->isSubsetOf(*I));
1609 /// buildInstructionOperandReference - The specified operand is a reference to a
1610 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1611 void AsmMatcherInfo::
1612 buildInstructionOperandReference(MatchableInfo *II,
1613 StringRef OperandName,
1614 unsigned AsmOpIdx) {
1615 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1616 const CGIOperandList &Operands = CGI.Operands;
1617 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1619 // Map this token to an operand.
1621 if (!Operands.hasOperandNamed(OperandName, Idx))
1622 PrintFatalError(II->TheDef->getLoc(),
1623 "error: unable to find operand: '" + OperandName + "'");
1625 // If the instruction operand has multiple suboperands, but the parser
1626 // match class for the asm operand is still the default "ImmAsmOperand",
1627 // then handle each suboperand separately.
1628 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1629 Record *Rec = Operands[Idx].Rec;
1630 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1631 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1632 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1633 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1634 StringRef Token = Op->Token; // save this in case Op gets moved
1635 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1636 MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1637 NewAsmOp.SubOpIdx = SI;
1638 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1640 // Replace Op with first suboperand.
1641 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1646 // Set up the operand class.
1647 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1649 // If the named operand is tied, canonicalize it to the untied operand.
1650 // For example, something like:
1651 // (outs GPR:$dst), (ins GPR:$src)
1652 // with an asmstring of
1654 // we want to canonicalize to:
1656 // so that we know how to provide the $dst operand when filling in the result.
1658 if (Operands[Idx].MINumOperands == 1)
1659 OITied = Operands[Idx].getTiedRegister();
1661 // The tied operand index is an MIOperand index, find the operand that
1663 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1664 OperandName = Operands[Idx.first].Name;
1665 Op->SubOpIdx = Idx.second;
1668 Op->SrcOpName = OperandName;
1671 /// buildAliasOperandReference - When parsing an operand reference out of the
1672 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1673 /// operand reference is by looking it up in the result pattern definition.
1674 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1675 StringRef OperandName,
1676 MatchableInfo::AsmOperand &Op) {
1677 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1679 // Set up the operand class.
1680 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1681 if (CGA.ResultOperands[i].isRecord() &&
1682 CGA.ResultOperands[i].getName() == OperandName) {
1683 // It's safe to go with the first one we find, because CodeGenInstAlias
1684 // validates that all operands with the same name have the same record.
1685 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1686 // Use the match class from the Alias definition, not the
1687 // destination instruction, as we may have an immediate that's
1688 // being munged by the match class.
1689 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1691 Op.SrcOpName = OperandName;
1695 PrintFatalError(II->TheDef->getLoc(),
1696 "error: unable to find operand: '" + OperandName + "'");
1699 void MatchableInfo::buildInstructionResultOperands() {
1700 const CodeGenInstruction *ResultInst = getResultInst();
1702 // Loop over all operands of the result instruction, determining how to
1704 for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1705 // If this is a tied operand, just copy from the previously handled operand.
1707 if (OpInfo.MINumOperands == 1)
1708 TiedOp = OpInfo.getTiedRegister();
1710 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1714 // Find out what operand from the asmparser this MCInst operand comes from.
1715 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1716 if (OpInfo.Name.empty() || SrcOperand == -1) {
1717 // This may happen for operands that are tied to a suboperand of a
1718 // complex operand. Simply use a dummy value here; nobody should
1719 // use this operand slot.
1720 // FIXME: The long term goal is for the MCOperand list to not contain
1721 // tied operands at all.
1722 ResOperands.push_back(ResOperand::getImmOp(0));
1726 // Check if the one AsmOperand populates the entire operand.
1727 unsigned NumOperands = OpInfo.MINumOperands;
1728 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1729 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1733 // Add a separate ResOperand for each suboperand.
1734 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1735 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1736 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1737 "unexpected AsmOperands for suboperands");
1738 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1743 void MatchableInfo::buildAliasResultOperands() {
1744 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1745 const CodeGenInstruction *ResultInst = getResultInst();
1747 // Loop over all operands of the result instruction, determining how to
1749 unsigned AliasOpNo = 0;
1750 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1751 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1752 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1754 // If this is a tied operand, just copy from the previously handled operand.
1756 if (OpInfo->MINumOperands == 1)
1757 TiedOp = OpInfo->getTiedRegister();
1759 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1763 // Handle all the suboperands for this operand.
1764 const std::string &OpName = OpInfo->Name;
1765 for ( ; AliasOpNo < LastOpNo &&
1766 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1767 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1769 // Find out what operand from the asmparser that this MCInst operand
1771 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1772 case CodeGenInstAlias::ResultOperand::K_Record: {
1773 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1774 int SrcOperand = findAsmOperand(Name, SubIdx);
1775 if (SrcOperand == -1)
1776 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1777 TheDef->getName() + "' has operand '" + OpName +
1778 "' that doesn't appear in asm string!");
1779 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1780 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1784 case CodeGenInstAlias::ResultOperand::K_Imm: {
1785 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1786 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1789 case CodeGenInstAlias::ResultOperand::K_Reg: {
1790 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1791 ResOperands.push_back(ResOperand::getRegOp(Reg));
1800 getConverterOperandID(const std::string &Name,
1801 SmallSetVector<CachedHashString, 16> &Table,
1803 IsNew = Table.insert(CachedHashString(Name));
1805 unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();
1807 assert(ID < Table.size());
1812 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1813 std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1814 bool HasMnemonicFirst, bool HasOptionalOperands,
1816 SmallSetVector<CachedHashString, 16> OperandConversionKinds;
1817 SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
1818 std::vector<std::vector<uint8_t> > ConversionTable;
1819 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1821 // TargetOperandClass - This is the target's operand class, like X86Operand.
1822 std::string TargetOperandClass = Target.getName().str() + "Operand";
1824 // Write the convert function to a separate stream, so we can drop it after
1825 // the enum. We'll build up the conversion handlers for the individual
1826 // operand types opportunistically as we encounter them.
1827 std::string ConvertFnBody;
1828 raw_string_ostream CvtOS(ConvertFnBody);
1829 // Start the unified conversion function.
1830 if (HasOptionalOperands) {
1831 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1832 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1833 << "unsigned Opcode,\n"
1834 << " const OperandVector &Operands,\n"
1835 << " const SmallBitVector &OptionalOperandsMask) {\n";
1837 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1838 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1839 << "unsigned Opcode,\n"
1840 << " const OperandVector &Operands) {\n";
1842 CvtOS << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
1843 CvtOS << " const uint8_t *Converter = ConversionTable[Kind];\n";
1844 if (HasOptionalOperands) {
1845 CvtOS << " unsigned NumDefaults = 0;\n";
1847 CvtOS << " unsigned OpIdx;\n";
1848 CvtOS << " Inst.setOpcode(Opcode);\n";
1849 CvtOS << " for (const uint8_t *p = Converter; *p; p+= 2) {\n";
1850 if (HasOptionalOperands) {
1851 CvtOS << " OpIdx = *(p + 1) - NumDefaults;\n";
1853 CvtOS << " OpIdx = *(p + 1);\n";
1855 CvtOS << " switch (*p) {\n";
1856 CvtOS << " default: llvm_unreachable(\"invalid conversion entry!\");\n";
1857 CvtOS << " case CVT_Reg:\n";
1858 CvtOS << " static_cast<" << TargetOperandClass
1859 << "&>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
1860 CvtOS << " break;\n";
1861 CvtOS << " case CVT_Tied:\n";
1862 CvtOS << " Inst.addOperand(Inst.getOperand(OpIdx));\n";
1863 CvtOS << " break;\n";
1865 std::string OperandFnBody;
1866 raw_string_ostream OpOS(OperandFnBody);
1867 // Start the operand number lookup function.
1868 OpOS << "void " << Target.getName() << ClassName << "::\n"
1869 << "convertToMapAndConstraints(unsigned Kind,\n";
1871 OpOS << "const OperandVector &Operands) {\n"
1872 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1873 << " unsigned NumMCOperands = 0;\n"
1874 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1875 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1876 << " switch (*p) {\n"
1877 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1878 << " case CVT_Reg:\n"
1879 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1880 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1881 << " ++NumMCOperands;\n"
1883 << " case CVT_Tied:\n"
1884 << " ++NumMCOperands;\n"
1887 // Pre-populate the operand conversion kinds with the standard always
1888 // available entries.
1889 OperandConversionKinds.insert(CachedHashString("CVT_Done"));
1890 OperandConversionKinds.insert(CachedHashString("CVT_Reg"));
1891 OperandConversionKinds.insert(CachedHashString("CVT_Tied"));
1892 enum { CVT_Done, CVT_Reg, CVT_Tied };
1894 for (auto &II : Infos) {
1895 // Check if we have a custom match function.
1896 std::string AsmMatchConverter =
1897 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1898 if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
1899 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1900 II->ConversionFnKind = Signature;
1902 // Check if we have already generated this signature.
1903 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
1906 // Remember this converter for the kind enum.
1907 unsigned KindID = OperandConversionKinds.size();
1908 OperandConversionKinds.insert(
1909 CachedHashString("CVT_" + getEnumNameForToken(AsmMatchConverter)));
1911 // Add the converter row for this instruction.
1912 ConversionTable.emplace_back();
1913 ConversionTable.back().push_back(KindID);
1914 ConversionTable.back().push_back(CVT_Done);
1916 // Add the handler to the conversion driver function.
1917 CvtOS << " case CVT_"
1918 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1919 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1922 // FIXME: Handle the operand number lookup for custom match functions.
1926 // Build the conversion function signature.
1927 std::string Signature = "Convert";
1929 std::vector<uint8_t> ConversionRow;
1931 // Compute the convert enum and the case body.
1932 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1934 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1935 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1937 // Generate code to populate each result operand.
1938 switch (OpInfo.Kind) {
1939 case MatchableInfo::ResOperand::RenderAsmOperand: {
1940 // This comes from something we parsed.
1941 const MatchableInfo::AsmOperand &Op =
1942 II->AsmOperands[OpInfo.AsmOperandNum];
1944 // Registers are always converted the same, don't duplicate the
1945 // conversion function based on them.
1948 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1950 Signature += utostr(OpInfo.MINumOperands);
1951 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1953 // Add the conversion kind, if necessary, and get the associated ID
1954 // the index of its entry in the vector).
1955 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1956 Op.Class->RenderMethod);
1957 if (Op.Class->IsOptional) {
1958 // For optional operands we must also care about DefaultMethod
1959 assert(HasOptionalOperands);
1960 Name += "_" + Op.Class->DefaultMethod;
1962 Name = getEnumNameForToken(Name);
1964 bool IsNewConverter = false;
1965 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1968 // Add the operand entry to the instruction kind conversion row.
1969 ConversionRow.push_back(ID);
1970 ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);
1972 if (!IsNewConverter)
1975 // This is a new operand kind. Add a handler for it to the
1976 // converter driver.
1977 CvtOS << " case " << Name << ":\n";
1978 if (Op.Class->IsOptional) {
1979 // If optional operand is not present in actual instruction then we
1980 // should call its DefaultMethod before RenderMethod
1981 assert(HasOptionalOperands);
1982 CvtOS << " if (OptionalOperandsMask[*(p + 1) - 1]) {\n"
1983 << " " << Op.Class->DefaultMethod << "()"
1984 << "->" << Op.Class->RenderMethod << "(Inst, "
1985 << OpInfo.MINumOperands << ");\n"
1986 << " ++NumDefaults;\n"
1988 << " static_cast<" << TargetOperandClass
1989 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
1990 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1993 CvtOS << " static_cast<" << TargetOperandClass
1994 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
1995 << "(Inst, " << OpInfo.MINumOperands << ");\n";
1997 CvtOS << " break;\n";
1999 // Add a handler for the operand number lookup.
2000 OpOS << " case " << Name << ":\n"
2001 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2003 if (Op.Class->isRegisterClass())
2004 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
2006 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
2007 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2011 case MatchableInfo::ResOperand::TiedOperand: {
2012 // If this operand is tied to a previous one, just copy the MCInst
2013 // operand from the earlier one.We can only tie single MCOperand values.
2014 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2015 unsigned TiedOp = OpInfo.TiedOperandNum;
2016 assert(i > TiedOp && "Tied operand precedes its target!");
2017 Signature += "__Tie" + utostr(TiedOp);
2018 ConversionRow.push_back(CVT_Tied);
2019 ConversionRow.push_back(TiedOp);
2022 case MatchableInfo::ResOperand::ImmOperand: {
2023 int64_t Val = OpInfo.ImmVal;
2024 std::string Ty = "imm_" + itostr(Val);
2025 Ty = getEnumNameForToken(Ty);
2026 Signature += "__" + Ty;
2028 std::string Name = "CVT_" + Ty;
2029 bool IsNewConverter = false;
2030 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2032 // Add the operand entry to the instruction kind conversion row.
2033 ConversionRow.push_back(ID);
2034 ConversionRow.push_back(0);
2036 if (!IsNewConverter)
2039 CvtOS << " case " << Name << ":\n"
2040 << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2043 OpOS << " case " << Name << ":\n"
2044 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2045 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
2046 << " ++NumMCOperands;\n"
2050 case MatchableInfo::ResOperand::RegOperand: {
2051 std::string Reg, Name;
2052 if (!OpInfo.Register) {
2056 Reg = getQualifiedName(OpInfo.Register);
2057 Name = "reg" + OpInfo.Register->getName().str();
2059 Signature += "__" + Name;
2060 Name = "CVT_" + Name;
2061 bool IsNewConverter = false;
2062 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2064 // Add the operand entry to the instruction kind conversion row.
2065 ConversionRow.push_back(ID);
2066 ConversionRow.push_back(0);
2068 if (!IsNewConverter)
2070 CvtOS << " case " << Name << ":\n"
2071 << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
2074 OpOS << " case " << Name << ":\n"
2075 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2076 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
2077 << " ++NumMCOperands;\n"
2083 // If there were no operands, add to the signature to that effect
2084 if (Signature == "Convert")
2085 Signature += "_NoOperands";
2087 II->ConversionFnKind = Signature;
2089 // Save the signature. If we already have it, don't add a new row
2091 if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
2094 // Add the row to the table.
2095 ConversionTable.push_back(std::move(ConversionRow));
2098 // Finish up the converter driver function.
2099 CvtOS << " }\n }\n}\n\n";
2101 // Finish up the operand number lookup function.
2102 OpOS << " }\n }\n}\n\n";
2104 OS << "namespace {\n";
2106 // Output the operand conversion kind enum.
2107 OS << "enum OperatorConversionKind {\n";
2108 for (const auto &Converter : OperandConversionKinds)
2109 OS << " " << Converter << ",\n";
2110 OS << " CVT_NUM_CONVERTERS\n";
2113 // Output the instruction conversion kind enum.
2114 OS << "enum InstructionConversionKind {\n";
2115 for (const auto &Signature : InstructionConversionKinds)
2116 OS << " " << Signature << ",\n";
2117 OS << " CVT_NUM_SIGNATURES\n";
2120 OS << "} // end anonymous namespace\n\n";
2122 // Output the conversion table.
2123 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2124 << MaxRowLength << "] = {\n";
2126 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2127 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2128 OS << " // " << InstructionConversionKinds[Row] << "\n";
2130 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
2131 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
2132 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2133 OS << "CVT_Done },\n";
2138 // Spit out the conversion driver function.
2141 // Spit out the operand number lookup function.
2145 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2146 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2147 std::forward_list<ClassInfo> &Infos,
2149 OS << "namespace {\n\n";
2151 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2152 << "/// instruction matching.\n";
2153 OS << "enum MatchClassKind {\n";
2154 OS << " InvalidMatchClass = 0,\n";
2155 OS << " OptionalMatchClass = 1,\n";
2156 for (const auto &CI : Infos) {
2157 OS << " " << CI.Name << ", // ";
2158 if (CI.Kind == ClassInfo::Token) {
2159 OS << "'" << CI.ValueName << "'\n";
2160 } else if (CI.isRegisterClass()) {
2161 if (!CI.ValueName.empty())
2162 OS << "register class '" << CI.ValueName << "'\n";
2164 OS << "derived register class\n";
2166 OS << "user defined class '" << CI.ValueName << "'\n";
2169 OS << " NumMatchClassKinds\n";
2175 /// emitValidateOperandClass - Emit the function to validate an operand class.
2176 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2178 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2179 << "MatchClassKind Kind) {\n";
2180 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2181 << Info.Target.getName() << "Operand&)GOp;\n";
2183 // The InvalidMatchClass is not to match any operand.
2184 OS << " if (Kind == InvalidMatchClass)\n";
2185 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2187 // Check for Token operands first.
2188 // FIXME: Use a more specific diagnostic type.
2189 OS << " if (Operand.isToken())\n";
2190 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2191 << " MCTargetAsmParser::Match_Success :\n"
2192 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2194 // Check the user classes. We don't care what order since we're only
2195 // actually matching against one of them.
2196 OS << " switch (Kind) {\n"
2197 " default: break;\n";
2198 for (const auto &CI : Info.Classes) {
2199 if (!CI.isUserClass())
2202 OS << " // '" << CI.ClassName << "' class\n";
2203 OS << " case " << CI.Name << ":\n";
2204 OS << " if (Operand." << CI.PredicateMethod << "())\n";
2205 OS << " return MCTargetAsmParser::Match_Success;\n";
2206 if (!CI.DiagnosticType.empty())
2207 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2208 << CI.DiagnosticType << ";\n";
2212 OS << " } // end switch (Kind)\n\n";
2214 // Check for register operands, including sub-classes.
2215 OS << " if (Operand.isReg()) {\n";
2216 OS << " MatchClassKind OpKind;\n";
2217 OS << " switch (Operand.getReg()) {\n";
2218 OS << " default: OpKind = InvalidMatchClass; break;\n";
2219 for (const auto &RC : Info.RegisterClasses)
2220 OS << " case " << Info.Target.getName() << "::"
2221 << RC.first->getName() << ": OpKind = " << RC.second->Name
2224 OS << " return isSubclass(OpKind, Kind) ? "
2225 << "MCTargetAsmParser::Match_Success :\n "
2226 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2228 // Generic fallthrough match failure case for operands that don't have
2229 // specialized diagnostic types.
2230 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2234 /// emitIsSubclass - Emit the subclass predicate function.
2235 static void emitIsSubclass(CodeGenTarget &Target,
2236 std::forward_list<ClassInfo> &Infos,
2238 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2239 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2240 OS << " if (A == B)\n";
2241 OS << " return true;\n\n";
2243 bool EmittedSwitch = false;
2244 for (const auto &A : Infos) {
2245 std::vector<StringRef> SuperClasses;
2247 SuperClasses.push_back("OptionalMatchClass");
2248 for (const auto &B : Infos) {
2249 if (&A != &B && A.isSubsetOf(B))
2250 SuperClasses.push_back(B.Name);
2253 if (SuperClasses.empty())
2256 // If this is the first SuperClass, emit the switch header.
2257 if (!EmittedSwitch) {
2258 OS << " switch (A) {\n";
2259 OS << " default:\n";
2260 OS << " return false;\n";
2261 EmittedSwitch = true;
2264 OS << "\n case " << A.Name << ":\n";
2266 if (SuperClasses.size() == 1) {
2267 OS << " return B == " << SuperClasses.back() << ";\n";
2271 if (!SuperClasses.empty()) {
2272 OS << " switch (B) {\n";
2273 OS << " default: return false;\n";
2274 for (StringRef SC : SuperClasses)
2275 OS << " case " << SC << ": return true;\n";
2278 // No case statement to emit
2279 OS << " return false;\n";
2283 // If there were case statements emitted into the string stream write the
2288 OS << " return false;\n";
2293 /// emitMatchTokenString - Emit the function to match a token string to the
2294 /// appropriate match class value.
2295 static void emitMatchTokenString(CodeGenTarget &Target,
2296 std::forward_list<ClassInfo> &Infos,
2298 // Construct the match list.
2299 std::vector<StringMatcher::StringPair> Matches;
2300 for (const auto &CI : Infos) {
2301 if (CI.Kind == ClassInfo::Token)
2302 Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2305 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2307 StringMatcher("Name", Matches, OS).Emit();
2309 OS << " return InvalidMatchClass;\n";
2313 /// emitMatchRegisterName - Emit the function to match a string to the target
2314 /// specific register enum.
2315 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2317 // Construct the match list.
2318 std::vector<StringMatcher::StringPair> Matches;
2319 const auto &Regs = Target.getRegBank().getRegisters();
2320 for (const CodeGenRegister &Reg : Regs) {
2321 if (Reg.TheDef->getValueAsString("AsmName").empty())
2324 Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2325 "return " + utostr(Reg.EnumValue) + ";");
2328 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2330 StringMatcher("Name", Matches, OS).Emit();
2332 OS << " return 0;\n";
2336 /// Emit the function to match a string to the target
2337 /// specific register enum.
2338 static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
2340 // Construct the match list.
2341 std::vector<StringMatcher::StringPair> Matches;
2342 const auto &Regs = Target.getRegBank().getRegisters();
2343 for (const CodeGenRegister &Reg : Regs) {
2345 auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
2347 for (auto AltName : AltNames) {
2348 AltName = StringRef(AltName).trim();
2350 // don't handle empty alternative names
2351 if (AltName.empty())
2354 Matches.emplace_back(AltName,
2355 "return " + utostr(Reg.EnumValue) + ";");
2359 OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
2361 StringMatcher("Name", Matches, OS).Emit();
2363 OS << " return 0;\n";
2367 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2368 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2369 // Get the set of diagnostic types from all of the operand classes.
2370 std::set<StringRef> Types;
2371 for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2372 if (!OpClassEntry.second->DiagnosticType.empty())
2373 Types.insert(OpClassEntry.second->DiagnosticType);
2376 if (Types.empty()) return;
2378 // Now emit the enum entries.
2379 for (StringRef Type : Types)
2380 OS << " Match_" << Type << ",\n";
2381 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2384 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2385 /// user-level name for a subtarget feature.
2386 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2387 OS << "// User-level names for subtarget features that participate in\n"
2388 << "// instruction matching.\n"
2389 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2390 if (!Info.SubtargetFeatures.empty()) {
2391 OS << " switch(Val) {\n";
2392 for (const auto &SF : Info.SubtargetFeatures) {
2393 const SubtargetFeatureInfo &SFI = SF.second;
2394 // FIXME: Totally just a placeholder name to get the algorithm working.
2395 OS << " case " << SFI.getEnumName() << ": return \""
2396 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2398 OS << " default: return \"(unknown)\";\n";
2401 // Nothing to emit, so skip the switch
2402 OS << " return \"(unknown)\";\n";
2407 static std::string GetAliasRequiredFeatures(Record *R,
2408 const AsmMatcherInfo &Info) {
2409 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2411 unsigned NumFeatures = 0;
2412 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2413 const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2416 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2417 "' is not marked as an AssemblerPredicate!");
2422 Result += F->getEnumName();
2426 if (NumFeatures > 1)
2427 Result = '(' + Result + ')';
2431 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2432 std::vector<Record*> &Aliases,
2433 unsigned Indent = 0,
2434 StringRef AsmParserVariantName = StringRef()){
2435 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2436 // iteration order of the map is stable.
2437 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2439 for (Record *R : Aliases) {
2440 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2441 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2442 if (AsmVariantName != AsmParserVariantName)
2444 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2446 if (AliasesFromMnemonic.empty())
2449 // Process each alias a "from" mnemonic at a time, building the code executed
2450 // by the string remapper.
2451 std::vector<StringMatcher::StringPair> Cases;
2452 for (const auto &AliasEntry : AliasesFromMnemonic) {
2453 const std::vector<Record*> &ToVec = AliasEntry.second;
2455 // Loop through each alias and emit code that handles each case. If there
2456 // are two instructions without predicates, emit an error. If there is one,
2458 std::string MatchCode;
2459 int AliasWithNoPredicate = -1;
2461 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2462 Record *R = ToVec[i];
2463 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2465 // If this unconditionally matches, remember it for later and diagnose
2467 if (FeatureMask.empty()) {
2468 if (AliasWithNoPredicate != -1) {
2469 // We can't have two aliases from the same mnemonic with no predicate.
2470 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2471 "two MnemonicAliases with the same 'from' mnemonic!");
2472 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2475 AliasWithNoPredicate = i;
2478 if (R->getValueAsString("ToMnemonic") == AliasEntry.first)
2479 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2481 if (!MatchCode.empty())
2482 MatchCode += "else ";
2483 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2484 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2487 if (AliasWithNoPredicate != -1) {
2488 Record *R = ToVec[AliasWithNoPredicate];
2489 if (!MatchCode.empty())
2490 MatchCode += "else\n ";
2491 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2494 MatchCode += "return;";
2496 Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
2498 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2501 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2502 /// emit a function for them and return true, otherwise return false.
2503 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2504 CodeGenTarget &Target) {
2505 // Ignore aliases when match-prefix is set.
2506 if (!MatchPrefix.empty())
2509 std::vector<Record*> Aliases =
2510 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2511 if (Aliases.empty()) return false;
2513 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2514 "uint64_t Features, unsigned VariantID) {\n";
2515 OS << " switch (VariantID) {\n";
2516 unsigned VariantCount = Target.getAsmParserVariantCount();
2517 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2518 Record *AsmVariant = Target.getAsmParserVariant(VC);
2519 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2520 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2521 OS << " case " << AsmParserVariantNo << ":\n";
2522 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2523 AsmParserVariantName);
2528 // Emit aliases that apply to all variants.
2529 emitMnemonicAliasVariant(OS, Info, Aliases);
2536 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2537 const AsmMatcherInfo &Info, StringRef ClassName,
2538 StringToOffsetTable &StringTable,
2539 unsigned MaxMnemonicIndex, bool HasMnemonicFirst) {
2540 unsigned MaxMask = 0;
2541 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2542 MaxMask |= OMI.OperandMask;
2545 // Emit the static custom operand parsing table;
2546 OS << "namespace {\n";
2547 OS << " struct OperandMatchEntry {\n";
2548 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
2549 << " RequiredFeatures;\n";
2550 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2552 OS << " " << getMinimalTypeForRange(std::distance(
2553 Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2554 OS << " " << getMinimalTypeForRange(MaxMask)
2555 << " OperandMask;\n\n";
2556 OS << " StringRef getMnemonic() const {\n";
2557 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2558 OS << " MnemonicTable[Mnemonic]);\n";
2562 OS << " // Predicate for searching for an opcode.\n";
2563 OS << " struct LessOpcodeOperand {\n";
2564 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2565 OS << " return LHS.getMnemonic() < RHS;\n";
2567 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2568 OS << " return LHS < RHS.getMnemonic();\n";
2570 OS << " bool operator()(const OperandMatchEntry &LHS,";
2571 OS << " const OperandMatchEntry &RHS) {\n";
2572 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2576 OS << "} // end anonymous namespace.\n\n";
2578 OS << "static const OperandMatchEntry OperandMatchTable["
2579 << Info.OperandMatchInfo.size() << "] = {\n";
2581 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2582 for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2583 const MatchableInfo &II = *OMI.MI;
2587 // Write the required features mask.
2588 if (!II.RequiredFeatures.empty()) {
2589 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2591 OS << II.RequiredFeatures[i]->getEnumName();
2596 // Store a pascal-style length byte in the mnemonic.
2597 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2598 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2599 << " /* " << II.Mnemonic << " */, ";
2603 OS << ", " << OMI.OperandMask;
2605 bool printComma = false;
2606 for (int i = 0, e = 31; i !=e; ++i)
2607 if (OMI.OperandMask & (1 << i)) {
2619 // Emit the operand class switch to call the correct custom parser for
2620 // the found operand class.
2621 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2622 << "tryCustomParseOperand(OperandVector"
2623 << " &Operands,\n unsigned MCK) {\n\n"
2624 << " switch(MCK) {\n";
2626 for (const auto &CI : Info.Classes) {
2627 if (CI.ParserMethod.empty())
2629 OS << " case " << CI.Name << ":\n"
2630 << " return " << CI.ParserMethod << "(Operands);\n";
2633 OS << " default:\n";
2634 OS << " return MatchOperand_NoMatch;\n";
2636 OS << " return MatchOperand_NoMatch;\n";
2639 // Emit the static custom operand parser. This code is very similar with
2640 // the other matcher. Also use MatchResultTy here just in case we go for
2641 // a better error handling.
2642 OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2643 << "MatchOperandParserImpl(OperandVector"
2644 << " &Operands,\n StringRef Mnemonic) {\n";
2646 // Emit code to get the available features.
2647 OS << " // Get the current feature set.\n";
2648 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2650 OS << " // Get the next operand index.\n";
2651 OS << " unsigned NextOpNum = Operands.size()"
2652 << (HasMnemonicFirst ? " - 1" : "") << ";\n";
2654 // Emit code to search the table.
2655 OS << " // Search the table.\n";
2656 if (HasMnemonicFirst) {
2657 OS << " auto MnemonicRange =\n";
2658 OS << " std::equal_range(std::begin(OperandMatchTable), "
2659 "std::end(OperandMatchTable),\n";
2660 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2662 OS << " auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
2663 " std::end(OperandMatchTable));\n";
2664 OS << " if (!Mnemonic.empty())\n";
2665 OS << " MnemonicRange =\n";
2666 OS << " std::equal_range(std::begin(OperandMatchTable), "
2667 "std::end(OperandMatchTable),\n";
2668 OS << " Mnemonic, LessOpcodeOperand());\n\n";
2671 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2672 OS << " return MatchOperand_NoMatch;\n\n";
2674 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2675 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2677 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2678 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2680 // Emit check that the required features are available.
2681 OS << " // check if the available features match\n";
2682 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2683 << "!= it->RequiredFeatures) {\n";
2684 OS << " continue;\n";
2687 // Emit check to ensure the operand number matches.
2688 OS << " // check if the operand in question has a custom parser.\n";
2689 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2690 OS << " continue;\n\n";
2692 // Emit call to the custom parser method
2693 OS << " // call custom parse method to handle the operand\n";
2694 OS << " OperandMatchResultTy Result = ";
2695 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2696 OS << " if (Result != MatchOperand_NoMatch)\n";
2697 OS << " return Result;\n";
2700 OS << " // Okay, we had no match.\n";
2701 OS << " return MatchOperand_NoMatch;\n";
2705 void AsmMatcherEmitter::run(raw_ostream &OS) {
2706 CodeGenTarget Target(Records);
2707 Record *AsmParser = Target.getAsmParser();
2708 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2710 // Compute the information on the instructions to match.
2711 AsmMatcherInfo Info(AsmParser, Target, Records);
2714 // Sort the instruction table using the partial order on classes. We use
2715 // stable_sort to ensure that ambiguous instructions are still
2716 // deterministically ordered.
2717 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2718 [](const std::unique_ptr<MatchableInfo> &a,
2719 const std::unique_ptr<MatchableInfo> &b){
2722 #ifdef EXPENSIVE_CHECKS
2723 // Verify that the table is sorted and operator < works transitively.
2724 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2726 for (auto J = I; J != E; ++J) {
2727 assert(!(**J < **I));
2732 DEBUG_WITH_TYPE("instruction_info", {
2733 for (const auto &MI : Info.Matchables)
2737 // Check for ambiguous matchables.
2738 DEBUG_WITH_TYPE("ambiguous_instrs", {
2739 unsigned NumAmbiguous = 0;
2740 for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
2742 for (auto J = std::next(I); J != E; ++J) {
2743 const MatchableInfo &A = **I;
2744 const MatchableInfo &B = **J;
2746 if (A.couldMatchAmbiguouslyWith(B)) {
2747 errs() << "warning: ambiguous matchables:\n";
2749 errs() << "\nis incomparable with:\n";
2757 errs() << "warning: " << NumAmbiguous
2758 << " ambiguous matchables!\n";
2761 // Compute the information on the custom operand parsing.
2762 Info.buildOperandMatchInfo();
2764 bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
2765 bool HasOptionalOperands = Info.hasOptionalOperands();
2767 // Write the output.
2769 // Information for the class declaration.
2770 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2771 OS << "#undef GET_ASSEMBLER_HEADER\n";
2772 OS << " // This should be included into the middle of the declaration of\n";
2773 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2774 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2775 if (HasOptionalOperands) {
2776 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2777 << "unsigned Opcode,\n"
2778 << " const OperandVector &Operands,\n"
2779 << " const SmallBitVector &OptionalOperandsMask);\n";
2781 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2782 << "unsigned Opcode,\n"
2783 << " const OperandVector &Operands);\n";
2785 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2786 OS << " const OperandVector &Operands) override;\n";
2787 if (HasMnemonicFirst)
2788 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2789 OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
2790 << " MCInst &Inst,\n"
2791 << " uint64_t &ErrorInfo,"
2792 << " bool matchingInlineAsm,\n"
2793 << " unsigned VariantID = 0);\n";
2795 if (!Info.OperandMatchInfo.empty()) {
2796 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2797 OS << " OperandVector &Operands,\n";
2798 OS << " StringRef Mnemonic);\n";
2800 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2801 OS << " OperandVector &Operands,\n";
2802 OS << " unsigned MCK);\n\n";
2805 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2807 // Emit the operand match diagnostic enum names.
2808 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2809 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2810 emitOperandDiagnosticTypes(Info, OS);
2811 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2813 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2814 OS << "#undef GET_REGISTER_MATCHER\n\n";
2816 // Emit the subtarget feature enumeration.
2817 SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
2818 Info.SubtargetFeatures, OS);
2820 // Emit the function to match a register name to number.
2821 // This should be omitted for Mips target
2822 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2823 emitMatchRegisterName(Target, AsmParser, OS);
2825 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))
2826 emitMatchRegisterAltName(Target, AsmParser, OS);
2828 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2830 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2831 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2833 // Generate the helper function to get the names for subtarget features.
2834 emitGetSubtargetFeatureName(Info, OS);
2836 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2838 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2839 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2841 // Generate the function that remaps for mnemonic aliases.
2842 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2844 // Generate the convertToMCInst function to convert operands into an MCInst.
2845 // Also, generate the convertToMapAndConstraints function for MS-style inline
2846 // assembly. The latter doesn't actually generate a MCInst.
2847 emitConvertFuncs(Target, ClassName, Info.Matchables, HasMnemonicFirst,
2848 HasOptionalOperands, OS);
2850 // Emit the enumeration for classes which participate in matching.
2851 emitMatchClassEnumeration(Target, Info.Classes, OS);
2853 // Emit the routine to match token strings to their match class.
2854 emitMatchTokenString(Target, Info.Classes, OS);
2856 // Emit the subclass predicate routine.
2857 emitIsSubclass(Target, Info.Classes, OS);
2859 // Emit the routine to validate an operand against a match class.
2860 emitValidateOperandClass(Info, OS);
2862 // Emit the available features compute function.
2863 SubtargetFeatureInfo::emitComputeAvailableFeatures(
2864 Info.Target.getName(), ClassName, "ComputeAvailableFeatures",
2865 Info.SubtargetFeatures, OS);
2867 StringToOffsetTable StringTable;
2869 size_t MaxNumOperands = 0;
2870 unsigned MaxMnemonicIndex = 0;
2871 bool HasDeprecation = false;
2872 for (const auto &MI : Info.Matchables) {
2873 MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
2874 HasDeprecation |= MI->HasDeprecation;
2876 // Store a pascal-style length byte in the mnemonic.
2877 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2878 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2879 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2882 OS << "static const char *const MnemonicTable =\n";
2883 StringTable.EmitString(OS);
2886 // Emit the static match table; unused classes get initalized to 0 which is
2887 // guaranteed to be InvalidMatchClass.
2889 // FIXME: We can reduce the size of this table very easily. First, we change
2890 // it so that store the kinds in separate bit-fields for each index, which
2891 // only needs to be the max width used for classes at that index (we also need
2892 // to reject based on this during classification). If we then make sure to
2893 // order the match kinds appropriately (putting mnemonics last), then we
2894 // should only end up using a few bits for each class, especially the ones
2895 // following the mnemonic.
2896 OS << "namespace {\n";
2897 OS << " struct MatchEntry {\n";
2898 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2900 OS << " uint16_t Opcode;\n";
2901 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2903 OS << " " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
2904 << " RequiredFeatures;\n";
2905 OS << " " << getMinimalTypeForRange(
2906 std::distance(Info.Classes.begin(), Info.Classes.end()))
2907 << " Classes[" << MaxNumOperands << "];\n";
2908 OS << " StringRef getMnemonic() const {\n";
2909 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2910 OS << " MnemonicTable[Mnemonic]);\n";
2914 OS << " // Predicate for searching for an opcode.\n";
2915 OS << " struct LessOpcode {\n";
2916 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2917 OS << " return LHS.getMnemonic() < RHS;\n";
2919 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2920 OS << " return LHS < RHS.getMnemonic();\n";
2922 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2923 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2927 OS << "} // end anonymous namespace.\n\n";
2929 unsigned VariantCount = Target.getAsmParserVariantCount();
2930 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2931 Record *AsmVariant = Target.getAsmParserVariant(VC);
2932 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2934 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2936 for (const auto &MI : Info.Matchables) {
2937 if (MI->AsmVariantID != AsmVariantNo)
2940 // Store a pascal-style length byte in the mnemonic.
2941 std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
2942 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2943 << " /* " << MI->Mnemonic << " */, "
2944 << Target.getName() << "::"
2945 << MI->getResultInst()->TheDef->getName() << ", "
2946 << MI->ConversionFnKind << ", ";
2948 // Write the required features mask.
2949 if (!MI->RequiredFeatures.empty()) {
2950 for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i) {
2952 OS << MI->RequiredFeatures[i]->getEnumName();
2958 for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
2959 const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
2962 OS << Op.Class->Name;
2970 // A method to determine if a mnemonic is in the list.
2971 if (HasMnemonicFirst) {
2972 OS << "bool " << Target.getName() << ClassName << "::\n"
2973 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2974 OS << " // Find the appropriate table for this asm variant.\n";
2975 OS << " const MatchEntry *Start, *End;\n";
2976 OS << " switch (VariantID) {\n";
2977 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
2978 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2979 Record *AsmVariant = Target.getAsmParserVariant(VC);
2980 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2981 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2982 << "); End = std::end(MatchTable" << VC << "); break;\n";
2985 OS << " // Search the table.\n";
2986 OS << " auto MnemonicRange = ";
2987 OS << "std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2988 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2992 // Finally, build the match function.
2993 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2994 << "MatchInstructionImpl(const OperandVector &Operands,\n";
2995 OS << " MCInst &Inst, uint64_t &ErrorInfo,\n"
2996 << " bool matchingInlineAsm, unsigned VariantID) {\n";
2998 OS << " // Eliminate obvious mismatches.\n";
2999 OS << " if (Operands.size() > "
3000 << (MaxNumOperands + HasMnemonicFirst) << ") {\n";
3001 OS << " ErrorInfo = "
3002 << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3003 OS << " return Match_InvalidOperand;\n";
3006 // Emit code to get the available features.
3007 OS << " // Get the current feature set.\n";
3008 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
3010 OS << " // Get the instruction mnemonic, which is the first token.\n";
3011 if (HasMnemonicFirst) {
3012 OS << " StringRef Mnemonic = ((" << Target.getName()
3013 << "Operand&)*Operands[0]).getToken();\n\n";
3015 OS << " StringRef Mnemonic;\n";
3016 OS << " if (Operands[0]->isToken())\n";
3017 OS << " Mnemonic = ((" << Target.getName()
3018 << "Operand&)*Operands[0]).getToken();\n\n";
3021 if (HasMnemonicAliases) {
3022 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
3023 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3026 // Emit code to compute the class list for this operand vector.
3027 OS << " // Some state to try to produce better error messages.\n";
3028 OS << " bool HadMatchOtherThanFeatures = false;\n";
3029 OS << " bool HadMatchOtherThanPredicate = false;\n";
3030 OS << " unsigned RetCode = Match_InvalidOperand;\n";
3031 OS << " uint64_t MissingFeatures = ~0ULL;\n";
3032 if (HasOptionalOperands) {
3033 OS << " SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n";
3035 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
3036 OS << " // wrong for all instances of the instruction.\n";
3037 OS << " ErrorInfo = ~0ULL;\n";
3039 // Emit code to search the table.
3040 OS << " // Find the appropriate table for this asm variant.\n";
3041 OS << " const MatchEntry *Start, *End;\n";
3042 OS << " switch (VariantID) {\n";
3043 OS << " default: llvm_unreachable(\"invalid variant!\");\n";
3044 for (unsigned VC = 0; VC != VariantCount; ++VC) {
3045 Record *AsmVariant = Target.getAsmParserVariant(VC);
3046 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3047 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3048 << "); End = std::end(MatchTable" << VC << "); break;\n";
3052 OS << " // Search the table.\n";
3053 if (HasMnemonicFirst) {
3054 OS << " auto MnemonicRange = "
3055 "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3057 OS << " auto MnemonicRange = std::make_pair(Start, End);\n";
3058 OS << " unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3059 OS << " if (!Mnemonic.empty())\n";
3060 OS << " MnemonicRange = "
3061 "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3064 OS << " // Return a more specific error code if no mnemonics match.\n";
3065 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
3066 OS << " return Match_MnemonicFail;\n\n";
3068 OS << " for (const MatchEntry *it = MnemonicRange.first, "
3069 << "*ie = MnemonicRange.second;\n";
3070 OS << " it != ie; ++it) {\n";
3072 if (HasMnemonicFirst) {
3073 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
3074 OS << " assert(Mnemonic == it->getMnemonic());\n";
3077 // Emit check that the subclasses match.
3078 OS << " bool OperandsValid = true;\n";
3079 if (HasOptionalOperands) {
3080 OS << " OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";
3082 OS << " for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3083 << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3084 << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3085 OS << " auto Formal = "
3086 << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3087 OS << " if (ActualIdx >= Operands.size()) {\n";
3088 OS << " OperandsValid = (Formal == " <<"InvalidMatchClass) || "
3089 "isSubclass(Formal, OptionalMatchClass);\n";
3090 OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n";
3091 if (HasOptionalOperands) {
3092 OS << " OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
3097 OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
3098 OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n";
3099 OS << " if (Diag == Match_Success) {\n";
3100 OS << " ++ActualIdx;\n";
3101 OS << " continue;\n";
3103 OS << " // If the generic handler indicates an invalid operand\n";
3104 OS << " // failure, check for a special case.\n";
3105 OS << " if (Diag == Match_InvalidOperand) {\n";
3106 OS << " Diag = validateTargetOperandClass(Actual, Formal);\n";
3107 OS << " if (Diag == Match_Success) {\n";
3108 OS << " ++ActualIdx;\n";
3109 OS << " continue;\n";
3112 OS << " // If current formal operand wasn't matched and it is optional\n"
3113 << " // then try to match next formal operand\n";
3114 OS << " if (Diag == Match_InvalidOperand "
3115 << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
3116 if (HasOptionalOperands) {
3117 OS << " OptionalOperandsMask.set(FormalIdx);\n";
3119 OS << " continue;\n";
3121 OS << " // If this operand is broken for all of the instances of this\n";
3122 OS << " // mnemonic, keep track of it so we can report loc info.\n";
3123 OS << " // If we already had a match that only failed due to a\n";
3124 OS << " // target predicate, that diagnostic is preferred.\n";
3125 OS << " if (!HadMatchOtherThanPredicate &&\n";
3126 OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
3127 OS << " ErrorInfo = ActualIdx;\n";
3128 OS << " // InvalidOperand is the default. Prefer specificity.\n";
3129 OS << " if (Diag != Match_InvalidOperand)\n";
3130 OS << " RetCode = Diag;\n";
3132 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
3133 OS << " OperandsValid = false;\n";
3137 OS << " if (!OperandsValid) continue;\n";
3139 // Emit check that the required features are available.
3140 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
3141 << "!= it->RequiredFeatures) {\n";
3142 OS << " HadMatchOtherThanFeatures = true;\n";
3143 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
3144 "~AvailableFeatures;\n";
3145 OS << " if (countPopulation(NewMissingFeatures) <=\n"
3146 " countPopulation(MissingFeatures))\n";
3147 OS << " MissingFeatures = NewMissingFeatures;\n";
3148 OS << " continue;\n";
3151 OS << " Inst.clear();\n\n";
3152 OS << " Inst.setOpcode(it->Opcode);\n";
3153 // Verify the instruction with the target-specific match predicate function.
3154 OS << " // We have a potential match but have not rendered the operands.\n"
3155 << " // Check the target predicate to handle any context sensitive\n"
3156 " // constraints.\n"
3157 << " // For example, Ties that are referenced multiple times must be\n"
3158 " // checked here to ensure the input is the same for each match\n"
3159 " // constraints. If we leave it any later the ties will have been\n"
3160 " // canonicalized\n"
3161 << " unsigned MatchResult;\n"
3162 << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
3163 "Operands)) != Match_Success) {\n"
3164 << " Inst.clear();\n"
3165 << " RetCode = MatchResult;\n"
3166 << " HadMatchOtherThanPredicate = true;\n"
3169 OS << " if (matchingInlineAsm) {\n";
3170 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3171 OS << " return Match_Success;\n";
3173 OS << " // We have selected a definite instruction, convert the parsed\n"
3174 << " // operands into the appropriate MCInst.\n";
3175 if (HasOptionalOperands) {
3176 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
3177 << " OptionalOperandsMask);\n";
3179 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3183 // Verify the instruction with the target-specific match predicate function.
3184 OS << " // We have a potential match. Check the target predicate to\n"
3185 << " // handle any context sensitive constraints.\n"
3186 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3187 << " Match_Success) {\n"
3188 << " Inst.clear();\n"
3189 << " RetCode = MatchResult;\n"
3190 << " HadMatchOtherThanPredicate = true;\n"
3194 // Call the post-processing function, if used.
3195 std::string InsnCleanupFn =
3196 AsmParser->getValueAsString("AsmParserInstCleanup");
3197 if (!InsnCleanupFn.empty())
3198 OS << " " << InsnCleanupFn << "(Inst);\n";
3200 if (HasDeprecation) {
3201 OS << " std::string Info;\n";
3202 OS << " if (!getParser().getTargetParser().\n";
3203 OS << " getTargetOptions().MCNoDeprecatedWarn &&\n";
3204 OS << " MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
3205 OS << " SMLoc Loc = ((" << Target.getName()
3206 << "Operand&)*Operands[0]).getStartLoc();\n";
3207 OS << " getParser().Warning(Loc, Info, None);\n";
3211 OS << " return Match_Success;\n";
3214 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3215 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3216 OS << " return RetCode;\n\n";
3217 OS << " // Missing feature matches return which features were missing\n";
3218 OS << " ErrorInfo = MissingFeatures;\n";
3219 OS << " return Match_MissingFeature;\n";
3222 if (!Info.OperandMatchInfo.empty())
3223 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3224 MaxMnemonicIndex, HasMnemonicFirst);
3226 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3231 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3232 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3233 AsmMatcherEmitter(RK).run(OS);
3236 } // end namespace llvm