1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits an assembly printer for the current target.
11 // Note that this is currently fairly skeletal, but will grow over time.
13 //===----------------------------------------------------------------------===//
15 #include "AsmWriterInst.h"
16 #include "CodeGenTarget.h"
17 #include "SequenceToOffsetTable.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
34 #define DEBUG_TYPE "asm-writer-emitter"
37 class AsmWriterEmitter {
38 RecordKeeper &Records;
40 ArrayRef<const CodeGenInstruction *> NumberedInstructions;
41 std::vector<AsmWriterInst> Instructions;
43 AsmWriterEmitter(RecordKeeper &R);
45 void run(raw_ostream &o);
48 void EmitPrintInstruction(raw_ostream &o);
49 void EmitGetRegisterName(raw_ostream &o);
50 void EmitPrintAliasInstruction(raw_ostream &O);
52 void FindUniqueOperandCommands(std::vector<std::string> &UOC,
53 std::vector<std::vector<unsigned>> &InstIdxs,
54 std::vector<unsigned> &InstOpsUsed,
55 bool PassSubtarget) const;
57 } // end anonymous namespace
59 static void PrintCases(std::vector<std::pair<std::string,
60 AsmWriterOperand> > &OpsToPrint, raw_ostream &O,
62 O << " case " << OpsToPrint.back().first << ":";
63 AsmWriterOperand TheOp = OpsToPrint.back().second;
64 OpsToPrint.pop_back();
66 // Check to see if any other operands are identical in this list, and if so,
67 // emit a case label for them.
68 for (unsigned i = OpsToPrint.size(); i != 0; --i)
69 if (OpsToPrint[i-1].second == TheOp) {
70 O << "\n case " << OpsToPrint[i-1].first << ":";
71 OpsToPrint.erase(OpsToPrint.begin()+i-1);
74 // Finally, emit the code.
75 O << "\n " << TheOp.getCode(PassSubtarget);
80 /// EmitInstructions - Emit the last instruction in the vector and any other
81 /// instructions that are suitably similar to it.
82 static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
83 raw_ostream &O, bool PassSubtarget) {
84 AsmWriterInst FirstInst = Insts.back();
87 std::vector<AsmWriterInst> SimilarInsts;
88 unsigned DifferingOperand = ~0;
89 for (unsigned i = Insts.size(); i != 0; --i) {
90 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
92 if (DifferingOperand == ~0U) // First match!
93 DifferingOperand = DiffOp;
95 // If this differs in the same operand as the rest of the instructions in
96 // this class, move it to the SimilarInsts list.
97 if (DifferingOperand == DiffOp || DiffOp == ~0U) {
98 SimilarInsts.push_back(Insts[i-1]);
99 Insts.erase(Insts.begin()+i-1);
104 O << " case " << FirstInst.CGI->Namespace << "::"
105 << FirstInst.CGI->TheDef->getName() << ":\n";
106 for (const AsmWriterInst &AWI : SimilarInsts)
107 O << " case " << AWI.CGI->Namespace << "::"
108 << AWI.CGI->TheDef->getName() << ":\n";
109 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
110 if (i != DifferingOperand) {
111 // If the operand is the same for all instructions, just print it.
112 O << " " << FirstInst.Operands[i].getCode(PassSubtarget);
114 // If this is the operand that varies between all of the instructions,
115 // emit a switch for just this operand now.
116 O << " switch (MI->getOpcode()) {\n";
117 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
118 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
119 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
120 FirstInst.CGI->TheDef->getName(),
121 FirstInst.Operands[i]));
123 for (const AsmWriterInst &AWI : SimilarInsts) {
124 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
125 AWI.CGI->TheDef->getName(),
128 std::reverse(OpsToPrint.begin(), OpsToPrint.end());
129 while (!OpsToPrint.empty())
130 PrintCases(OpsToPrint, O, PassSubtarget);
138 void AsmWriterEmitter::
139 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
140 std::vector<std::vector<unsigned>> &InstIdxs,
141 std::vector<unsigned> &InstOpsUsed,
142 bool PassSubtarget) const {
144 // This vector parallels UniqueOperandCommands, keeping track of which
145 // instructions each case are used for. It is a comma separated string of
147 std::vector<std::string> InstrsForCase;
148 InstrsForCase.resize(UniqueOperandCommands.size());
149 InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
151 for (size_t i = 0, e = Instructions.size(); i != e; ++i) {
152 const AsmWriterInst &Inst = Instructions[i];
153 if (Inst.Operands.empty())
154 continue; // Instruction already done.
156 std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n";
158 // Check to see if we already have 'Command' in UniqueOperandCommands.
160 auto I = std::find(UniqueOperandCommands.begin(),
161 UniqueOperandCommands.end(), Command);
162 if (I != UniqueOperandCommands.end()) {
163 size_t idx = I - UniqueOperandCommands.begin();
164 InstrsForCase[idx] += ", ";
165 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
166 InstIdxs[idx].push_back(i);
168 UniqueOperandCommands.push_back(std::move(Command));
169 InstrsForCase.push_back(Inst.CGI->TheDef->getName());
170 InstIdxs.emplace_back();
171 InstIdxs.back().push_back(i);
173 // This command matches one operand so far.
174 InstOpsUsed.push_back(1);
178 // For each entry of UniqueOperandCommands, there is a set of instructions
179 // that uses it. If the next command of all instructions in the set are
180 // identical, fold it into the command.
181 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size();
182 CommandIdx != e; ++CommandIdx) {
184 const auto &Idxs = InstIdxs[CommandIdx];
186 for (unsigned Op = 1; ; ++Op) {
187 // Find the first instruction in the set.
188 const AsmWriterInst &FirstInst = Instructions[Idxs.front()];
189 // If this instruction has no more operands, we isn't anything to merge
190 // into this command.
191 if (FirstInst.Operands.size() == Op)
194 // Otherwise, scan to see if all of the other instructions in this command
195 // set share the operand.
196 if (std::any_of(Idxs.begin()+1, Idxs.end(),
198 const AsmWriterInst &OtherInst = Instructions[Idx];
199 return OtherInst.Operands.size() == Op ||
200 OtherInst.Operands[Op] != FirstInst.Operands[Op];
204 // Okay, everything in this command set has the same next operand. Add it
205 // to UniqueOperandCommands and remember that it was consumed.
206 std::string Command = " " +
207 FirstInst.Operands[Op].getCode(PassSubtarget) + "\n";
209 UniqueOperandCommands[CommandIdx] += Command;
210 InstOpsUsed[CommandIdx]++;
214 // Prepend some of the instructions each case is used for onto the case val.
215 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
216 std::string Instrs = InstrsForCase[i];
217 if (Instrs.size() > 70) {
218 Instrs.erase(Instrs.begin()+70, Instrs.end());
223 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
224 UniqueOperandCommands[i];
229 static void UnescapeString(std::string &Str) {
230 for (unsigned i = 0; i != Str.size(); ++i) {
231 if (Str[i] == '\\' && i != Str.size()-1) {
233 default: continue; // Don't execute the code after the switch.
234 case 'a': Str[i] = '\a'; break;
235 case 'b': Str[i] = '\b'; break;
236 case 'e': Str[i] = 27; break;
237 case 'f': Str[i] = '\f'; break;
238 case 'n': Str[i] = '\n'; break;
239 case 'r': Str[i] = '\r'; break;
240 case 't': Str[i] = '\t'; break;
241 case 'v': Str[i] = '\v'; break;
242 case '"': Str[i] = '\"'; break;
243 case '\'': Str[i] = '\''; break;
244 case '\\': Str[i] = '\\'; break;
246 // Nuke the second character.
247 Str.erase(Str.begin()+i+1);
252 /// EmitPrintInstruction - Generate the code for the "printInstruction" method
253 /// implementation. Destroys all instances of AsmWriterInst information, by
254 /// clearing the Instructions vector.
255 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
256 Record *AsmWriter = Target.getAsmWriter();
257 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
258 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
261 "/// printInstruction - This method is automatically generated by tablegen\n"
262 "/// from the instruction set description.\n"
263 "void " << Target.getName() << ClassName
264 << "::printInstruction(const MCInst *MI, "
265 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
266 << "raw_ostream &O) {\n";
268 // Build an aggregate string, and build a table of offsets into it.
269 SequenceToOffsetTable<std::string> StringTable;
271 /// OpcodeInfo - This encodes the index of the string to use for the first
272 /// chunk of the output as well as indices used for operand printing.
273 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size());
274 const unsigned OpcodeInfoBits = 64;
276 // Add all strings to the string table upfront so it can generate an optimized
278 for (AsmWriterInst &AWI : Instructions) {
279 if (AWI.Operands[0].OperandType ==
280 AsmWriterOperand::isLiteralTextOperand &&
281 !AWI.Operands[0].Str.empty()) {
282 std::string Str = AWI.Operands[0].Str;
284 StringTable.add(Str);
288 StringTable.layout();
290 unsigned MaxStringIdx = 0;
291 for (AsmWriterInst &AWI : Instructions) {
293 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand ||
294 AWI.Operands[0].Str.empty()) {
295 // Something handled by the asmwriter printer, but with no leading string.
296 Idx = StringTable.get("");
298 std::string Str = AWI.Operands[0].Str;
300 Idx = StringTable.get(Str);
301 MaxStringIdx = std::max(MaxStringIdx, Idx);
303 // Nuke the string from the operand list. It is now handled!
304 AWI.Operands.erase(AWI.Operands.begin());
307 // Bias offset by one since we want 0 as a sentinel.
308 OpcodeInfo[AWI.CGIIndex] = Idx+1;
311 // Figure out how many bits we used for the string index.
312 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
314 // To reduce code size, we compactify common instructions into a few bits
315 // in the opcode-indexed table.
316 unsigned BitsLeft = OpcodeInfoBits-AsmStrBits;
318 std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
321 std::vector<std::string> UniqueOperandCommands;
322 std::vector<std::vector<unsigned>> InstIdxs;
323 std::vector<unsigned> NumInstOpsHandled;
324 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
325 NumInstOpsHandled, PassSubtarget);
327 // If we ran out of operands to print, we're done.
328 if (UniqueOperandCommands.empty()) break;
330 // Compute the number of bits we need to represent these cases, this is
331 // ceil(log2(numentries)).
332 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
334 // If we don't have enough bits for this operand, don't include it.
335 if (NumBits > BitsLeft) {
336 DEBUG(errs() << "Not enough bits to densely encode " << NumBits
341 // Otherwise, we can include this in the initial lookup table. Add it in.
342 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) {
343 unsigned NumOps = NumInstOpsHandled[i];
344 for (unsigned Idx : InstIdxs[i]) {
345 OpcodeInfo[Instructions[Idx].CGIIndex] |=
346 (uint64_t)i << (OpcodeInfoBits-BitsLeft);
347 // Remove the info about this operand from the instruction.
348 AsmWriterInst &Inst = Instructions[Idx];
349 if (!Inst.Operands.empty()) {
350 assert(NumOps <= Inst.Operands.size() &&
351 "Can't remove this many ops!");
352 Inst.Operands.erase(Inst.Operands.begin(),
353 Inst.Operands.begin()+NumOps);
359 // Remember the handlers for this set of operands.
360 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
363 // Emit the string table itself.
364 O << " static const char AsmStrs[] = {\n";
365 StringTable.emit(O, printChar);
368 // Emit the lookup tables in pieces to minimize wasted bytes.
369 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8;
370 unsigned Table = 0, Shift = 0;
371 SmallString<128> BitsString;
372 raw_svector_ostream BitsOS(BitsString);
373 // If the total bits is more than 32-bits we need to use a 64-bit type.
374 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
376 while (BytesNeeded != 0) {
377 // Figure out how big this table section needs to be, but no bigger than 4.
378 unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4);
379 BytesNeeded -= TableSize;
380 TableSize *= 8; // Convert to bits;
381 uint64_t Mask = (1ULL << TableSize) - 1;
382 O << " static const uint" << TableSize << "_t OpInfo" << Table
384 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
385 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
386 << NumberedInstructions[i]->TheDef->getName() << "\n";
389 // Emit string to combine the individual table lookups.
390 BitsOS << " Bits |= ";
391 // If the total bits is more than 32-bits we need to use a 64-bit type.
392 if (BitsLeft < (OpcodeInfoBits - 32))
393 BitsOS << "(uint64_t)";
394 BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n";
395 // Prepare the shift for the next iteration and increment the table count.
400 // Emit the initial tab character.
401 O << " O << \"\\t\";\n\n";
403 O << " // Emit the opcode for the instruction.\n";
406 // Emit the starting string.
407 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
408 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
410 // Output the table driven operand information.
411 BitsLeft = OpcodeInfoBits-AsmStrBits;
412 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
413 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
415 // Compute the number of bits we need to represent these cases, this is
416 // ceil(log2(numentries)).
417 unsigned NumBits = Log2_32_Ceil(Commands.size());
418 assert(NumBits <= BitsLeft && "consistency error");
420 // Emit code to extract this field from Bits.
421 O << "\n // Fragment " << i << " encoded into " << NumBits
422 << " bits for " << Commands.size() << " unique commands.\n";
424 if (Commands.size() == 2) {
425 // Emit two possibilitys with if/else.
426 O << " if ((Bits >> "
427 << (OpcodeInfoBits-BitsLeft) << ") & "
428 << ((1 << NumBits)-1) << ") {\n"
433 } else if (Commands.size() == 1) {
434 // Emit a single possibility.
435 O << Commands[0] << "\n\n";
437 O << " switch ((Bits >> "
438 << (OpcodeInfoBits-BitsLeft) << ") & "
439 << ((1 << NumBits)-1) << ") {\n"
440 << " default: llvm_unreachable(\"Invalid command number.\");\n";
442 // Print out all the cases.
443 for (unsigned j = 0, e = Commands.size(); j != e; ++j) {
444 O << " case " << j << ":\n";
453 // Okay, delete instructions with no operand info left.
454 auto I = std::remove_if(Instructions.begin(), Instructions.end(),
455 [](AsmWriterInst &Inst) {
456 return Inst.Operands.empty();
458 Instructions.erase(I, Instructions.end());
461 // Because this is a vector, we want to emit from the end. Reverse all of the
462 // elements in the vector.
463 std::reverse(Instructions.begin(), Instructions.end());
466 // Now that we've emitted all of the operand info that fit into 64 bits, emit
467 // information for those instructions that are left. This is a less dense
468 // encoding, but we expect the main 64-bit table to handle the majority of
470 if (!Instructions.empty()) {
471 // Find the opcode # of inline asm.
472 O << " switch (MI->getOpcode()) {\n";
473 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
474 while (!Instructions.empty())
475 EmitInstructions(Instructions, O, PassSubtarget);
483 static const char *getMinimalTypeForRange(uint64_t Range) {
484 assert(Range < 0xFFFFFFFFULL && "Enum too large");
493 emitRegisterNameString(raw_ostream &O, StringRef AltName,
494 const std::deque<CodeGenRegister> &Registers) {
495 SequenceToOffsetTable<std::string> StringTable;
496 SmallVector<std::string, 4> AsmNames(Registers.size());
498 for (const auto &Reg : Registers) {
499 std::string &AsmName = AsmNames[i++];
501 // "NoRegAltName" is special. We don't need to do a lookup for that,
502 // as it's just a reference to the default register name.
503 if (AltName == "" || AltName == "NoRegAltName") {
504 AsmName = Reg.TheDef->getValueAsString("AsmName");
506 AsmName = Reg.getName();
508 // Make sure the register has an alternate name for this index.
509 std::vector<Record*> AltNameList =
510 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
512 for (e = AltNameList.size();
513 Idx < e && (AltNameList[Idx]->getName() != AltName);
516 // If the register has an alternate name for this index, use it.
517 // Otherwise, leave it empty as an error flag.
519 std::vector<std::string> AltNames =
520 Reg.TheDef->getValueAsListOfStrings("AltNames");
521 if (AltNames.size() <= Idx)
522 PrintFatalError(Reg.TheDef->getLoc(),
523 "Register definition missing alt name for '" +
525 AsmName = AltNames[Idx];
528 StringTable.add(AsmName);
531 StringTable.layout();
532 O << " static const char AsmStrs" << AltName << "[] = {\n";
533 StringTable.emit(O, printChar);
536 O << " static const " << getMinimalTypeForRange(StringTable.size()-1)
537 << " RegAsmOffset" << AltName << "[] = {";
538 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
541 O << StringTable.get(AsmNames[i]) << ", ";
547 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
548 Record *AsmWriter = Target.getAsmWriter();
549 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
550 const auto &Registers = Target.getRegBank().getRegisters();
551 const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices();
552 bool hasAltNames = AltNameIndices.size() > 1;
553 std::string Namespace =
554 Registers.front().TheDef->getValueAsString("Namespace");
557 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
558 "/// from the register set description. This returns the assembler name\n"
559 "/// for the specified register.\n"
560 "const char *" << Target.getName() << ClassName << "::";
562 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
564 O << "getRegisterName(unsigned RegNo) {\n";
565 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
566 << " && \"Invalid register number!\");\n"
570 for (const Record *R : AltNameIndices)
571 emitRegisterNameString(O, R->getName(), Registers);
573 emitRegisterNameString(O, "", Registers);
576 O << " switch(AltIdx) {\n"
577 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
578 for (const Record *R : AltNameIndices) {
579 const std::string &AltName = R->getName();
580 std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
581 O << " case " << Prefix << AltName << ":\n"
582 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset"
583 << AltName << "[RegNo-1]) &&\n"
584 << " \"Invalid alt name index for register!\");\n"
585 << " return AsmStrs" << AltName << "+RegAsmOffset"
586 << AltName << "[RegNo-1];\n";
590 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
591 << " \"Invalid alt name index for register!\");\n"
592 << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
598 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if
599 // they both have the same conditionals. In which case, we cannot print out the
600 // alias for that pattern.
602 std::vector<std::string> Conds;
603 std::map<StringRef, std::pair<int, int>> OpMap;
606 std::string AsmString;
608 IAPrinter(std::string R, std::string AS)
609 : Result(std::move(R)), AsmString(std::move(AS)) {}
611 void addCond(const std::string &C) { Conds.push_back(C); }
613 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
614 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
615 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
617 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
620 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
621 int getOpIndex(StringRef Op) { return OpMap[Op].first; }
622 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
624 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
625 StringRef::iterator End) {
626 StringRef::iterator I = Start;
627 StringRef::iterator Next;
631 while (I != End && *I != '}')
638 // $name, just eat the usual suspects.
640 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
641 (*I >= '0' && *I <= '9') || *I == '_'))
646 return std::make_pair(StringRef(Start, I - Start), Next);
649 void print(raw_ostream &O) {
651 O.indent(6) << "return true;\n";
657 for (std::vector<std::string>::iterator
658 I = Conds.begin(), E = Conds.end(); I != E; ++I) {
659 if (I != Conds.begin()) {
668 O.indent(6) << "// " << Result << "\n";
670 // Directly mangle mapped operands into the string. Each operand is
671 // identified by a '$' sign followed by a byte identifying the number of the
672 // operand. We add one to the index to avoid zero bytes.
673 StringRef ASM(AsmString);
674 SmallString<128> OutString;
675 raw_svector_ostream OS(OutString);
676 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
680 std::tie(Name, I) = parseName(++I, E);
681 assert(isOpMapped(Name) && "Unmapped operand!");
683 int OpIndex, PrintIndex;
684 std::tie(OpIndex, PrintIndex) = getOpData(Name);
685 if (PrintIndex == -1) {
686 // Can use the default printOperand route.
687 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
689 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
690 // number, and which of our pre-detected Methods to call.
691 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
698 O.indent(6) << "AsmString = \"" << OutString << "\";\n";
700 O.indent(6) << "break;\n";
704 bool operator==(const IAPrinter &RHS) const {
705 if (Conds.size() != RHS.Conds.size())
709 for (const auto &str : Conds)
710 if (str != RHS.Conds[Idx++])
717 } // end anonymous namespace
719 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
720 std::string FlatAsmString =
721 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
722 AsmString = FlatAsmString;
724 return AsmString.count(' ') + AsmString.count('\t');
728 struct AliasPriorityComparator {
729 typedef std::pair<CodeGenInstAlias, int> ValueType;
730 bool operator()(const ValueType &LHS, const ValueType &RHS) {
731 if (LHS.second == RHS.second) {
732 // We don't actually care about the order, but for consistency it
733 // shouldn't depend on pointer comparisons.
734 return LHS.first.TheDef->getName() < RHS.first.TheDef->getName();
737 // Aliases with larger priorities should be considered first.
738 return LHS.second > RHS.second;
744 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
745 Record *AsmWriter = Target.getAsmWriter();
747 O << "\n#ifdef PRINT_ALIAS_INSTR\n";
748 O << "#undef PRINT_ALIAS_INSTR\n\n";
750 //////////////////////////////
751 // Gather information about aliases we need to print
752 //////////////////////////////
754 // Emit the method that prints the alias instruction.
755 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
756 unsigned Variant = AsmWriter->getValueAsInt("Variant");
757 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
759 std::vector<Record*> AllInstAliases =
760 Records.getAllDerivedDefinitions("InstAlias");
762 // Create a map from the qualified name to a list of potential matches.
763 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
765 std::map<std::string, AliasWithPriority> AliasMap;
766 for (Record *R : AllInstAliases) {
767 int Priority = R->getValueAsInt("EmitPriority");
769 continue; // Aliases with priority 0 are never emitted.
771 const DagInit *DI = R->getValueAsDag("ResultInst");
772 const DefInit *Op = cast<DefInit>(DI->getOperator());
773 AliasMap[getQualifiedName(Op->getDef())].insert(
774 std::make_pair(CodeGenInstAlias(R, Variant, Target), Priority));
777 // A map of which conditions need to be met for each instruction operand
778 // before it can be matched to the mnemonic.
779 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
781 std::vector<std::string> PrintMethods;
783 // A list of MCOperandPredicates for all operands in use, and the reverse map
784 std::vector<const Record*> MCOpPredicates;
785 DenseMap<const Record*, unsigned> MCOpPredicateMap;
787 for (auto &Aliases : AliasMap) {
788 for (auto &Alias : Aliases.second) {
789 const CodeGenInstAlias &CGA = Alias.first;
790 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
791 unsigned NumResultOps =
792 CountNumOperands(CGA.ResultInst->AsmString, Variant);
794 // Don't emit the alias if it has more operands than what it's aliasing.
795 if (NumResultOps < CountNumOperands(CGA.AsmString, Variant))
798 IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
800 std::string Namespace = Target.getName();
801 std::vector<Record *> ReqFeatures;
803 // We only consider ReqFeatures predicates if PassSubtarget
804 std::vector<Record *> RF =
805 CGA.TheDef->getValueAsListOfDefs("Predicates");
806 std::copy_if(RF.begin(), RF.end(), std::back_inserter(ReqFeatures),
808 return R->getValueAsBit("AssemblerMatcherPredicate");
812 unsigned NumMIOps = 0;
813 for (auto &Operand : CGA.ResultOperands)
814 NumMIOps += Operand.getMINumOperands();
817 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
820 bool CantHandle = false;
822 unsigned MIOpNum = 0;
823 for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
824 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
826 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
829 case CodeGenInstAlias::ResultOperand::K_Record: {
830 const Record *Rec = RO.getRecord();
831 StringRef ROName = RO.getName();
832 int PrintMethodIdx = -1;
834 // These two may have a PrintMethod, which we want to record (if it's
835 // the first time we've seen it) and provide an index for the aliasing
837 if (Rec->isSubClassOf("RegisterOperand") ||
838 Rec->isSubClassOf("Operand")) {
839 std::string PrintMethod = Rec->getValueAsString("PrintMethod");
840 if (PrintMethod != "" && PrintMethod != "printOperand") {
841 PrintMethodIdx = std::find(PrintMethods.begin(),
842 PrintMethods.end(), PrintMethod) -
843 PrintMethods.begin();
844 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
845 PrintMethods.push_back(PrintMethod);
849 if (Rec->isSubClassOf("RegisterOperand"))
850 Rec = Rec->getValueAsDef("RegClass");
851 if (Rec->isSubClassOf("RegisterClass")) {
852 IAP.addCond(Op + ".isReg()");
854 if (!IAP.isOpMapped(ROName)) {
855 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
856 Record *R = CGA.ResultOperands[i].getRecord();
857 if (R->isSubClassOf("RegisterOperand"))
858 R = R->getValueAsDef("RegClass");
859 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
860 R->getName() + "RegClassID)"
861 ".contains(" + Op + ".getReg())";
863 Cond = Op + ".getReg() == MI->getOperand(" +
864 llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
867 // Assume all printable operands are desired for now. This can be
868 // overridden in the InstAlias instantiation if necessary.
869 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
871 // There might be an additional predicate on the MCOperand
872 unsigned Entry = MCOpPredicateMap[Rec];
874 if (!Rec->isValueUnset("MCOperandPredicate")) {
875 MCOpPredicates.push_back(Rec);
876 Entry = MCOpPredicates.size();
877 MCOpPredicateMap[Rec] = Entry;
879 break; // No conditions on this operand at all
881 Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
882 Op + ", STI, " + llvm::utostr(Entry) + ")";
884 // for all subcases of ResultOperand::K_Record:
888 case CodeGenInstAlias::ResultOperand::K_Imm: {
889 // Just because the alias has an immediate result, doesn't mean the
890 // MCInst will. An MCExpr could be present, for example.
891 IAP.addCond(Op + ".isImm()");
893 Cond = Op + ".getImm() == " +
894 llvm::utostr(CGA.ResultOperands[i].getImm());
898 case CodeGenInstAlias::ResultOperand::K_Reg:
899 // If this is zero_reg, something's playing tricks we're not
900 // equipped to handle.
901 if (!CGA.ResultOperands[i].getRegister()) {
906 Cond = Op + ".getReg() == " + Target.getName() + "::" +
907 CGA.ResultOperands[i].getRegister()->getName();
912 MIOpNum += RO.getMINumOperands();
915 if (CantHandle) continue;
917 for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) {
919 std::string AsmCondString = R->getValueAsString("AssemblerCondString");
921 // AsmCondString has syntax [!]F(,[!]F)*
922 SmallVector<StringRef, 4> Ops;
923 SplitString(AsmCondString, Ops, ",");
924 assert(!Ops.empty() && "AssemblerCondString cannot be empty");
926 for (auto &Op : Ops) {
927 assert(!Op.empty() && "Empty operator");
929 Cond = "!STI.getFeatureBits()[" + Namespace + "::" +
930 Op.substr(1).str() + "]";
932 Cond = "STI.getFeatureBits()[" + Namespace + "::" + Op.str() + "]";
937 IAPrinterMap[Aliases.first].push_back(std::move(IAP));
941 //////////////////////////////
942 // Write out the printAliasInstr function
943 //////////////////////////////
946 raw_string_ostream HeaderO(Header);
948 HeaderO << "bool " << Target.getName() << ClassName
949 << "::printAliasInstr(const MCInst"
950 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
951 << "raw_ostream &OS) {\n";
954 raw_string_ostream CasesO(Cases);
956 for (auto &Entry : IAPrinterMap) {
957 std::vector<IAPrinter> &IAPs = Entry.second;
958 std::vector<IAPrinter*> UniqueIAPs;
960 for (auto &LHS : IAPs) {
962 for (const auto &RHS : IAPs) {
963 if (&LHS != &RHS && LHS == RHS) {
970 UniqueIAPs.push_back(&LHS);
973 if (UniqueIAPs.empty()) continue;
975 CasesO.indent(2) << "case " << Entry.first << ":\n";
977 for (IAPrinter *IAP : UniqueIAPs) {
983 CasesO.indent(4) << "return false;\n";
986 if (CasesO.str().empty()) {
988 O << " return false;\n";
990 O << "#endif // PRINT_ALIAS_INSTR\n";
994 if (!MCOpPredicates.empty())
995 O << "static bool " << Target.getName() << ClassName
996 << "ValidateMCOperand(const MCOperand &MCOp,\n"
997 << " const MCSubtargetInfo &STI,\n"
998 << " unsigned PredicateIndex);\n";
1001 O.indent(2) << "const char *AsmString;\n";
1002 O.indent(2) << "switch (MI->getOpcode()) {\n";
1003 O.indent(2) << "default: return false;\n";
1005 O.indent(2) << "}\n\n";
1007 // Code that prints the alias, replacing the operands with the ones from the
1009 O << " unsigned I = 0;\n";
1010 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n";
1011 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n";
1013 O << " OS << '\\t' << StringRef(AsmString, I);\n";
1015 O << " if (AsmString[I] != '\\0') {\n";
1016 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t')";
1017 O << " OS << '\\t';\n";
1019 O << " if (AsmString[I] == '$') {\n";
1021 O << " if (AsmString[I] == (char)0xff) {\n";
1023 O << " int OpIdx = AsmString[I++] - 1;\n";
1024 O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
1025 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, ";
1026 O << (PassSubtarget ? "STI, " : "");
1029 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
1030 O << (PassSubtarget ? "STI, " : "");
1033 O << " OS << AsmString[I++];\n";
1035 O << " } while (AsmString[I] != '\\0');\n";
1038 O << " return true;\n";
1041 //////////////////////////////
1042 // Write out the printCustomAliasOperand function
1043 //////////////////////////////
1045 O << "void " << Target.getName() << ClassName << "::"
1046 << "printCustomAliasOperand(\n"
1047 << " const MCInst *MI, unsigned OpIdx,\n"
1048 << " unsigned PrintMethodIdx,\n"
1049 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
1050 << " raw_ostream &OS) {\n";
1051 if (PrintMethods.empty())
1052 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
1054 O << " switch (PrintMethodIdx) {\n"
1056 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
1059 for (unsigned i = 0; i < PrintMethods.size(); ++i) {
1060 O << " case " << i << ":\n"
1061 << " " << PrintMethods[i] << "(MI, OpIdx, "
1062 << (PassSubtarget ? "STI, " : "") << "OS);\n"
1069 if (!MCOpPredicates.empty()) {
1070 O << "static bool " << Target.getName() << ClassName
1071 << "ValidateMCOperand(const MCOperand &MCOp,\n"
1072 << " const MCSubtargetInfo &STI,\n"
1073 << " unsigned PredicateIndex) {\n"
1074 << " switch (PredicateIndex) {\n"
1076 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
1079 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
1080 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
1081 if (CodeInit *SI = dyn_cast<CodeInit>(MCOpPred)) {
1082 O << " case " << i + 1 << ": {\n"
1083 << SI->getValue() << "\n"
1086 llvm_unreachable("Unexpected MCOperandPredicate field!");
1092 O << "#endif // PRINT_ALIAS_INSTR\n";
1095 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
1096 Record *AsmWriter = Target.getAsmWriter();
1097 unsigned Variant = AsmWriter->getValueAsInt("Variant");
1099 // Get the instruction numbering.
1100 NumberedInstructions = Target.getInstructionsByEnumValue();
1102 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
1103 const CodeGenInstruction *I = NumberedInstructions[i];
1104 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
1105 Instructions.emplace_back(*I, i, Variant);
1109 void AsmWriterEmitter::run(raw_ostream &O) {
1110 EmitPrintInstruction(O);
1111 EmitGetRegisterName(O);
1112 EmitPrintAliasInstruction(O);
1118 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
1119 emitSourceFileHeader("Assembly Writer Source Fragment", OS);
1120 AsmWriterEmitter(RK).run(OS);
1123 } // End llvm namespace