1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/IntEqClasses.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/TableGen/Error.h"
27 #define DEBUG_TYPE "regalloc-emitter"
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
33 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
36 if (R->getValue("Namespace"))
37 Namespace = R->getValueAsString("Namespace");
38 Size = R->getValueAsInt("Size");
39 Offset = R->getValueAsInt("Offset");
42 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
48 std::string CodeGenSubRegIndex::getQualifiedName() const {
49 std::string N = getNamespace();
56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
62 if (Comps.size() != 2)
63 PrintFatalError(TheDef->getLoc(),
64 "ComposedOf must have exactly two entries");
65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
67 CodeGenSubRegIndex *X = A->addComposite(B, this);
69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
72 std::vector<Record*> Parts =
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
76 PrintFatalError(TheDef->getLoc(),
77 "CoveredBySubRegs must have two or more entries");
78 SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
79 for (unsigned i = 0, e = Parts.size(); i != e; ++i)
80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i]));
81 RegBank.addConcatSubRegIndex(IdxParts, this);
85 unsigned CodeGenSubRegIndex::computeLaneMask() const {
90 // Recursion guard, shouldn't be required.
93 // The lane mask is simply the union of all sub-indices.
95 for (const auto &C : Composed)
96 M |= C.second->computeLaneMask();
97 assert(M && "Missing lane mask, sub-register cycle?");
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
109 CostPerUse(R->getValueAsInt("CostPerUse")),
110 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
111 HasDisjunctSubRegs(false),
112 SubRegsComplete(false),
113 SuperRegsComplete(false),
117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
121 if (SRIs.size() != SRs.size())
122 PrintFatalError(TheDef->getLoc(),
123 "SubRegs and SubRegIndices must have the same size");
125 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
130 // Also compute leading super-registers. Each register has a list of
131 // covered-by-subregs super-registers where it appears as the first explicit
134 // This is used by computeSecondarySubRegs() to find candidates.
135 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
136 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
138 // Add ad hoc alias links. This is a symmetric relationship between two
139 // registers, so build a symmetric graph by adding links in both ends.
140 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
141 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
148 const std::string &CodeGenRegister::getName() const {
149 assert(TheDef && "no def");
150 return TheDef->getName();
154 // Iterate over all register units in a set of registers.
155 class RegUnitIterator {
156 CodeGenRegister::Vec::const_iterator RegI, RegE;
157 CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
160 RegUnitIterator(const CodeGenRegister::Vec &Regs):
161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
164 UnitI = (*RegI)->getRegUnits().begin();
165 UnitE = (*RegI)->getRegUnits().end();
170 bool isValid() const { return UnitI != UnitE; }
172 unsigned operator* () const { assert(isValid()); return *UnitI; }
174 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
176 /// Preincrement. Move to the next unit.
178 assert(isValid() && "Cannot advance beyond the last operand");
185 while (UnitI == UnitE) {
188 UnitI = (*RegI)->getRegUnits().begin();
189 UnitE = (*RegI)->getRegUnits().end();
195 // Return true of this unit appears in RegUnits.
196 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
197 return RegUnits.test(Unit);
200 // Inherit register units from subregisters.
201 // Return true if the RegUnits changed.
202 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
203 bool changed = false;
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
206 CodeGenRegister *SR = I->second;
207 // Merge the subregister's units into this register's RegUnits.
208 changed |= (RegUnits |= SR->RegUnits);
214 const CodeGenRegister::SubRegMap &
215 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
216 // Only compute this map once.
219 SubRegsComplete = true;
221 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
223 // First insert the explicit subregs and make sure they are fully indexed.
224 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
225 CodeGenRegister *SR = ExplicitSubRegs[i];
226 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
228 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
229 " appears twice in Register " + getName());
230 // Map explicit sub-registers first, so the names take precedence.
231 // The inherited sub-registers are mapped below.
232 SubReg2Idx.insert(std::make_pair(SR, Idx));
235 // Keep track of inherited subregs and how they can be reached.
236 SmallPtrSet<CodeGenRegister*, 8> Orphans;
238 // Clone inherited subregs and place duplicate entries in Orphans.
239 // Here the order is important - earlier subregs take precedence.
240 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
241 CodeGenRegister *SR = ExplicitSubRegs[i];
242 const SubRegMap &Map = SR->computeSubRegs(RegBank);
243 HasDisjunctSubRegs |= SR->HasDisjunctSubRegs;
245 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
247 if (!SubRegs.insert(*SI).second)
248 Orphans.insert(SI->second);
252 // Expand any composed subreg indices.
253 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
254 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
255 // expanded subreg indices recursively.
256 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
257 for (unsigned i = 0; i != Indices.size(); ++i) {
258 CodeGenSubRegIndex *Idx = Indices[i];
259 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
260 CodeGenRegister *SR = SubRegs[Idx];
261 const SubRegMap &Map = SR->computeSubRegs(RegBank);
263 // Look at the possible compositions of Idx.
264 // They may not all be supported by SR.
265 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
266 E = Comps.end(); I != E; ++I) {
267 SubRegMap::const_iterator SRI = Map.find(I->first);
268 if (SRI == Map.end())
269 continue; // Idx + I->first doesn't exist in SR.
270 // Add I->second as a name for the subreg SRI->second, assuming it is
271 // orphaned, and the name isn't already used for something else.
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
274 // We found a new name for the orphaned sub-register.
275 SubRegs.insert(std::make_pair(I->second, SRI->second));
276 Indices.push_back(I->second);
280 // Now Orphans contains the inherited subregisters without a direct index.
281 // Create inferred indexes for all missing entries.
282 // Work backwards in the Indices vector in order to compose subregs bottom-up.
283 // Consider this subreg sequence:
285 // qsub_1 -> dsub_0 -> ssub_0
287 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
288 // can be reached in two different ways:
293 // We pick the latter composition because another register may have [dsub_0,
294 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
295 // dsub_2 -> ssub_0 composition can be shared.
296 while (!Indices.empty() && !Orphans.empty()) {
297 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
298 CodeGenRegister *SR = SubRegs[Idx];
299 const SubRegMap &Map = SR->computeSubRegs(RegBank);
300 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
302 if (Orphans.erase(SI->second))
303 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
306 // Compute the inverse SubReg -> Idx map.
307 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
309 if (SI->second == this) {
312 Loc = TheDef->getLoc();
313 PrintFatalError(Loc, "Register " + getName() +
314 " has itself as a sub-register");
317 // Compute AllSuperRegsCovered.
318 if (!CoveredBySubRegs)
319 SI->first->AllSuperRegsCovered = false;
321 // Ensure that every sub-register has a unique name.
322 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
323 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first;
324 if (Ins->second == SI->first)
326 // Trouble: Two different names for SI->second.
329 Loc = TheDef->getLoc();
330 PrintFatalError(Loc, "Sub-register can't have two names: " +
331 SI->second->getName() + " available as " +
332 SI->first->getName() + " and " + Ins->second->getName());
335 // Derive possible names for sub-register concatenations from any explicit
336 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
337 // that getConcatSubRegIndex() won't invent any concatenated indices that the
338 // user already specified.
339 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
340 CodeGenRegister *SR = ExplicitSubRegs[i];
341 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1)
344 // SR is composed of multiple sub-regs. Find their names in this register.
345 SmallVector<CodeGenSubRegIndex*, 8> Parts;
346 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j)
347 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
349 // Offer this as an existing spelling for the concatenation of Parts.
350 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]);
353 // Initialize RegUnitList. Because getSubRegs is called recursively, this
354 // processes the register hierarchy in postorder.
356 // Inherit all sub-register units. It is good enough to look at the explicit
357 // sub-registers, the other registers won't contribute any more units.
358 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
359 CodeGenRegister *SR = ExplicitSubRegs[i];
360 RegUnits |= SR->RegUnits;
363 // Absent any ad hoc aliasing, we create one register unit per leaf register.
364 // These units correspond to the maximal cliques in the register overlap
365 // graph which is optimal.
367 // When there is ad hoc aliasing, we simply create one unit per edge in the
368 // undirected ad hoc aliasing graph. Technically, we could do better by
369 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
370 // are extremely rare anyway (I've never seen one), so we don't bother with
371 // the added complexity.
372 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
373 CodeGenRegister *AR = ExplicitAliases[i];
374 // Only visit each edge once.
375 if (AR->SubRegsComplete)
377 // Create a RegUnit representing this alias edge, and add it to both
379 unsigned Unit = RegBank.newRegUnit(this, AR);
381 AR->RegUnits.set(Unit);
384 // Finally, create units for leaf registers without ad hoc aliases. Note that
385 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
386 // necessary. This means the aliasing leaf registers can share a single unit.
387 if (RegUnits.empty())
388 RegUnits.set(RegBank.newRegUnit(this));
390 // We have now computed the native register units. More may be adopted later
391 // for balancing purposes.
392 NativeRegUnits = RegUnits;
397 // In a register that is covered by its sub-registers, try to find redundant
398 // sub-registers. For example:
404 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
405 // the register definition.
407 // The explicitly specified registers form a tree. This function discovers
408 // sub-register relationships that would force a DAG.
410 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
411 // Collect new sub-registers first, add them later.
412 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
414 // Look at the leading super-registers of each sub-register. Those are the
415 // candidates for new sub-registers, assuming they are fully contained in
417 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){
418 const CodeGenRegister *SubReg = I->second;
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
420 for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
421 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
422 // Already got this sub-register?
423 if (Cand == this || getSubRegIndex(Cand))
425 // Check if each component of Cand is already a sub-register.
426 // We know that the first component is I->second, and is present with the
428 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first);
429 assert(!Cand->ExplicitSubRegs.empty() &&
430 "Super-register has no sub-registers");
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
433 Parts.push_back(Idx);
435 // Sub-register doesn't exist.
440 // If some Cand sub-register is not part of this register, or if Cand only
441 // has one sub-register, there is nothing to do.
442 if (Parts.size() <= 1)
445 // Each part of Cand is a sub-register of this. Make the full Cand also
446 // a sub-register with a concatenated sub-register index.
447 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts);
448 NewSubRegs.push_back(std::make_pair(Concat, Cand));
452 // Now add all the new sub-registers.
453 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
454 // Don't add Cand if another sub-register is already using the index.
455 if (!SubRegs.insert(NewSubRegs[i]).second)
458 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
459 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
460 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx));
463 // Create sub-register index composition maps for the synthesized indices.
464 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
465 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
466 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
467 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
468 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
471 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
472 SI->second->getName() + " in " + getName());
473 NewIdx->addComposite(SI->first, SubIdx);
478 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
479 // Only visit each register once.
480 if (SuperRegsComplete)
482 SuperRegsComplete = true;
484 // Make sure all sub-registers have been visited first, so the super-reg
485 // lists will be topologically ordered.
486 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
488 I->second->computeSuperRegs(RegBank);
490 // Now add this as a super-register on all sub-registers.
491 // Also compute the TopoSigId in post-order.
493 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
495 // Topological signature computed from SubIdx, TopoId(SubReg).
496 // Loops and idempotent indices have TopoSig = ~0u.
497 Id.push_back(I->first->EnumValue);
498 Id.push_back(I->second->TopoSig);
500 // Don't add duplicate entries.
501 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
503 I->second->SuperRegs.push_back(this);
505 TopoSig = RegBank.getTopoSig(Id);
509 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
510 CodeGenRegBank &RegBank) const {
511 assert(SubRegsComplete && "Must precompute sub-registers");
512 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
513 CodeGenRegister *SR = ExplicitSubRegs[i];
515 SR->addSubRegsPreOrder(OSet, RegBank);
517 // Add any secondary sub-registers that weren't part of the explicit tree.
518 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
520 OSet.insert(I->second);
523 // Get the sum of this register's unit weights.
524 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
526 for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
528 Weight += RegBank.getRegUnit(*I).Weight;
533 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
537 // A RegisterTuples def is used to generate pseudo-registers from lists of
538 // sub-registers. We provide a SetTheory expander class that returns the new
541 struct TupleExpander : SetTheory::Expander {
542 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
543 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
544 unsigned Dim = Indices.size();
545 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
546 if (Dim != SubRegs->size())
547 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
549 PrintFatalError(Def->getLoc(),
550 "Tuples must have at least 2 sub-registers");
552 // Evaluate the sub-register lists to be zipped.
553 unsigned Length = ~0u;
554 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
555 for (unsigned i = 0; i != Dim; ++i) {
556 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
557 Length = std::min(Length, unsigned(Lists[i].size()));
563 // Precompute some types.
564 Record *RegisterCl = Def->getRecords().getClass("Register");
565 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
566 StringInit *BlankName = StringInit::get("");
569 for (unsigned n = 0; n != Length; ++n) {
571 Record *Proto = Lists[0][n];
572 std::vector<Init*> Tuple;
573 unsigned CostPerUse = 0;
574 for (unsigned i = 0; i != Dim; ++i) {
575 Record *Reg = Lists[i][n];
577 Name += Reg->getName();
578 Tuple.push_back(DefInit::get(Reg));
579 CostPerUse = std::max(CostPerUse,
580 unsigned(Reg->getValueAsInt("CostPerUse")));
583 // Create a new Record representing the synthesized register. This record
584 // is only for consumption by CodeGenRegister, it is not added to the
586 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
589 // Copy Proto super-classes.
590 ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses();
591 for (const auto &SuperPair : Supers)
592 NewReg->addSuperClass(SuperPair.first, SuperPair.second);
594 // Copy Proto fields.
595 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
596 RecordVal RV = Proto->getValues()[i];
598 // Skip existing fields, like NAME.
599 if (NewReg->getValue(RV.getNameInit()))
602 StringRef Field = RV.getName();
604 // Replace the sub-register list with Tuple.
605 if (Field == "SubRegs")
606 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
608 // Provide a blank AsmName. MC hacks are required anyway.
609 if (Field == "AsmName")
610 RV.setValue(BlankName);
612 // CostPerUse is aggregated from all Tuple members.
613 if (Field == "CostPerUse")
614 RV.setValue(IntInit::get(CostPerUse));
616 // Composite registers are always covered by sub-registers.
617 if (Field == "CoveredBySubRegs")
618 RV.setValue(BitInit::get(true));
620 // Copy fields from the RegisterTuples def.
621 if (Field == "SubRegIndices" ||
622 Field == "CompositeIndices") {
623 NewReg->addValue(*Def->getValue(Field));
627 // Some fields get their default uninitialized value.
628 if (Field == "DwarfNumbers" ||
629 Field == "DwarfAlias" ||
630 Field == "Aliases") {
631 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
632 NewReg->addValue(*DefRV);
636 // Everything else is copied from Proto.
637 NewReg->addValue(RV);
644 //===----------------------------------------------------------------------===//
645 // CodeGenRegisterClass
646 //===----------------------------------------------------------------------===//
648 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
649 std::sort(M.begin(), M.end(), deref<llvm::less>());
650 M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
653 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
656 TopoSigs(RegBank.getNumTopoSigs()),
659 // Rename anonymous register classes.
660 if (R->getName().size() > 9 && R->getName()[9] == '.') {
661 static unsigned AnonCounter = 0;
662 R->setName("AnonRegClass_" + utostr(AnonCounter++));
665 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
666 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
667 Record *Type = TypeList[i];
668 if (!Type->isSubClassOf("ValueType"))
669 PrintFatalError("RegTypes list member '" + Type->getName() +
670 "' does not derive from the ValueType class!");
671 VTs.push_back(getValueType(Type));
673 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
675 // Allocation order 0 is the full set. AltOrders provides others.
676 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
677 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
678 Orders.resize(1 + AltOrders->size());
680 // Default allocation order always contains all registers.
681 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
682 Orders[0].push_back((*Elements)[i]);
683 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
684 Members.push_back(Reg);
685 TopoSigs.set(Reg->getTopoSig());
687 sortAndUniqueRegisters(Members);
689 // Alternative allocation orders may be subsets.
690 SetTheory::RecSet Order;
691 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
692 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
693 Orders[1 + i].append(Order.begin(), Order.end());
694 // Verify that all altorder members are regclass members.
695 while (!Order.empty()) {
696 CodeGenRegister *Reg = RegBank.getReg(Order.back());
699 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
700 " is not a class member");
704 // Allow targets to override the size in bits of the RegisterClass.
705 unsigned Size = R->getValueAsInt("Size");
707 Namespace = R->getValueAsString("Namespace");
708 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
709 SpillAlignment = R->getValueAsInt("Alignment");
710 CopyCost = R->getValueAsInt("CopyCost");
711 Allocatable = R->getValueAsBit("isAllocatable");
712 AltOrderSelect = R->getValueAsString("AltOrderSelect");
713 int AllocationPriority = R->getValueAsInt("AllocationPriority");
714 if (AllocationPriority < 0 || AllocationPriority > 63)
715 PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
716 this->AllocationPriority = AllocationPriority;
719 // Create an inferred register class that was missing from the .td files.
720 // Most properties will be inherited from the closest super-class after the
721 // class structure has been computed.
722 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
723 StringRef Name, Key Props)
724 : Members(*Props.Members),
727 TopoSigs(RegBank.getNumTopoSigs()),
729 SpillSize(Props.SpillSize),
730 SpillAlignment(Props.SpillAlignment),
733 AllocationPriority(0) {
734 for (const auto R : Members)
735 TopoSigs.set(R->getTopoSig());
738 // Compute inherited propertied for a synthesized register class.
739 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
740 assert(!getDef() && "Only synthesized classes can inherit properties");
741 assert(!SuperClasses.empty() && "Synthesized class without super class");
743 // The last super-class is the smallest one.
744 CodeGenRegisterClass &Super = *SuperClasses.back();
746 // Most properties are copied directly.
747 // Exceptions are members, size, and alignment
748 Namespace = Super.Namespace;
750 CopyCost = Super.CopyCost;
751 Allocatable = Super.Allocatable;
752 AltOrderSelect = Super.AltOrderSelect;
753 AllocationPriority = Super.AllocationPriority;
755 // Copy all allocation orders, filter out foreign registers from the larger
757 Orders.resize(Super.Orders.size());
758 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
759 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
760 if (contains(RegBank.getReg(Super.Orders[i][j])))
761 Orders[i].push_back(Super.Orders[i][j]);
764 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
765 return std::binary_search(Members.begin(), Members.end(), Reg,
766 deref<llvm::less>());
770 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
771 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
772 for (const auto R : *K.Members)
773 OS << ", " << R->getName();
778 // This is a simple lexicographical order that can be used to search for sets.
779 // It is not the same as the topological order provided by TopoOrderRC.
780 bool CodeGenRegisterClass::Key::
781 operator<(const CodeGenRegisterClass::Key &B) const {
782 assert(Members && B.Members);
783 return std::tie(*Members, SpillSize, SpillAlignment) <
784 std::tie(*B.Members, B.SpillSize, B.SpillAlignment);
787 // Returns true if RC is a strict subclass.
788 // RC is a sub-class of this class if it is a valid replacement for any
789 // instruction operand where a register of this classis required. It must
790 // satisfy these conditions:
792 // 1. All RC registers are also in this.
793 // 2. The RC spill size must not be smaller than our spill size.
794 // 3. RC spill alignment must be compatible with ours.
796 static bool testSubClass(const CodeGenRegisterClass *A,
797 const CodeGenRegisterClass *B) {
798 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
799 A->SpillSize <= B->SpillSize &&
800 std::includes(A->getMembers().begin(), A->getMembers().end(),
801 B->getMembers().begin(), B->getMembers().end(),
802 deref<llvm::less>());
805 /// Sorting predicate for register classes. This provides a topological
806 /// ordering that arranges all register classes before their sub-classes.
808 /// Register classes with the same registers, spill size, and alignment form a
809 /// clique. They will be ordered alphabetically.
811 static bool TopoOrderRC(const CodeGenRegisterClass &PA,
812 const CodeGenRegisterClass &PB) {
818 // Order by ascending spill size.
819 if (A->SpillSize < B->SpillSize)
821 if (A->SpillSize > B->SpillSize)
824 // Order by ascending spill alignment.
825 if (A->SpillAlignment < B->SpillAlignment)
827 if (A->SpillAlignment > B->SpillAlignment)
830 // Order by descending set size. Note that the classes' allocation order may
831 // not have been computed yet. The Members set is always vaild.
832 if (A->getMembers().size() > B->getMembers().size())
834 if (A->getMembers().size() < B->getMembers().size())
837 // Finally order by name as a tie breaker.
838 return StringRef(A->getName()) < B->getName();
841 std::string CodeGenRegisterClass::getQualifiedName() const {
842 if (Namespace.empty())
845 return Namespace + "::" + getName();
848 // Compute sub-classes of all register classes.
849 // Assume the classes are ordered topologically.
850 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
851 auto &RegClasses = RegBank.getRegClasses();
853 // Visit backwards so sub-classes are seen first.
854 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
855 CodeGenRegisterClass &RC = *I;
856 RC.SubClasses.resize(RegClasses.size());
857 RC.SubClasses.set(RC.EnumValue);
859 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
860 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
861 CodeGenRegisterClass &SubRC = *I2;
862 if (RC.SubClasses.test(SubRC.EnumValue))
864 if (!testSubClass(&RC, &SubRC))
866 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
868 RC.SubClasses |= SubRC.SubClasses;
871 // Sweep up missed clique members. They will be immediately preceding RC.
872 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2)
873 RC.SubClasses.set(I2->EnumValue);
876 // Compute the SuperClasses lists from the SubClasses vectors.
877 for (auto &RC : RegClasses) {
878 const BitVector &SC = RC.getSubClasses();
879 auto I = RegClasses.begin();
880 for (int s = 0, next_s = SC.find_first(); next_s != -1;
881 next_s = SC.find_next(s)) {
882 std::advance(I, next_s - s);
886 I->SuperClasses.push_back(&RC);
890 // With the class hierarchy in place, let synthesized register classes inherit
891 // properties from their closest super-class. The iteration order here can
892 // propagate properties down multiple levels.
893 for (auto &RC : RegClasses)
895 RC.inheritProperties(RegBank);
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
899 BitVector &Out) const {
900 auto FindI = SuperRegClasses.find(SubIdx);
901 if (FindI == SuperRegClasses.end())
903 for (CodeGenRegisterClass *RC : FindI->second)
904 Out.set(RC->EnumValue);
907 // Populate a unique sorted list of units from a register set.
908 void CodeGenRegisterClass::buildRegUnitSet(
909 std::vector<unsigned> &RegUnits) const {
910 std::vector<unsigned> TmpUnits;
911 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
912 TmpUnits.push_back(*UnitI);
913 std::sort(TmpUnits.begin(), TmpUnits.end());
914 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
915 std::back_inserter(RegUnits));
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
922 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
923 // Configure register Sets to understand register classes and tuples.
924 Sets.addFieldExpander("RegisterClass", "MemberList");
925 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
926 Sets.addExpander("RegisterTuples", llvm::make_unique<TupleExpander>());
928 // Read in the user-defined (named) sub-register indices.
929 // More indices will be synthesized later.
930 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
931 std::sort(SRIs.begin(), SRIs.end(), LessRecord());
932 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
933 getSubRegIdx(SRIs[i]);
934 // Build composite maps from ComposedOf fields.
935 for (auto &Idx : SubRegIndices)
936 Idx.updateComponents(*this);
938 // Read in the register definitions.
939 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
940 std::sort(Regs.begin(), Regs.end(), LessRecordRegister());
941 // Assign the enumeration values.
942 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
945 // Expand tuples and number the new registers.
946 std::vector<Record*> Tups =
947 Records.getAllDerivedDefinitions("RegisterTuples");
949 for (Record *R : Tups) {
950 std::vector<Record *> TupRegs = *Sets.expand(R);
951 std::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister());
952 for (Record *RC : TupRegs)
956 // Now all the registers are known. Build the object graph of explicit
957 // register-register references.
958 for (auto &Reg : Registers)
959 Reg.buildObjectGraph(*this);
961 // Compute register name map.
962 for (auto &Reg : Registers)
963 // FIXME: This could just be RegistersByName[name] = register, except that
964 // causes some failures in MIPS - perhaps they have duplicate register name
965 // entries? (or maybe there's a reason for it - I don't know much about this
966 // code, just drive-by refactoring)
967 RegistersByName.insert(
968 std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
970 // Precompute all sub-register maps.
971 // This will create Composite entries for all inferred sub-register indices.
972 for (auto &Reg : Registers)
973 Reg.computeSubRegs(*this);
975 // Infer even more sub-registers by combining leading super-registers.
976 for (auto &Reg : Registers)
977 if (Reg.CoveredBySubRegs)
978 Reg.computeSecondarySubRegs(*this);
980 // After the sub-register graph is complete, compute the topologically
981 // ordered SuperRegs list.
982 for (auto &Reg : Registers)
983 Reg.computeSuperRegs(*this);
985 // Native register units are associated with a leaf register. They've all been
987 NumNativeRegUnits = RegUnits.size();
989 // Read in register class definitions.
990 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
992 PrintFatalError("No 'RegisterClass' subclasses defined!");
994 // Allocate user-defined register classes.
995 for (auto *RC : RCs) {
996 RegClasses.emplace_back(*this, RC);
997 addToMaps(&RegClasses.back());
1000 // Infer missing classes to create a full algebra.
1001 computeInferredRegisterClasses();
1003 // Order register classes topologically and assign enum values.
1004 RegClasses.sort(TopoOrderRC);
1006 for (auto &RC : RegClasses)
1008 CodeGenRegisterClass::computeSubClasses(*this);
1011 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1013 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1014 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
1015 return &SubRegIndices.back();
1018 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1019 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1022 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1);
1023 Idx = &SubRegIndices.back();
1027 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1028 CodeGenRegister *&Reg = Def2Reg[Def];
1031 Registers.emplace_back(Def, Registers.size() + 1);
1032 Reg = &Registers.back();
1036 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1037 if (Record *Def = RC->getDef())
1038 Def2RC.insert(std::make_pair(Def, RC));
1040 // Duplicate classes are rejected by insert().
1041 // That's OK, we only care about the properties handled by CGRC::Key.
1042 CodeGenRegisterClass::Key K(*RC);
1043 Key2RC.insert(std::make_pair(K, RC));
1046 // Create a synthetic sub-class if it is missing.
1047 CodeGenRegisterClass*
1048 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1049 const CodeGenRegister::Vec *Members,
1051 // Synthetic sub-class has the same size and alignment as RC.
1052 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
1053 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1054 if (FoundI != Key2RC.end())
1055 return FoundI->second;
1057 // Sub-class doesn't exist, create a new one.
1058 RegClasses.emplace_back(*this, Name, K);
1059 addToMaps(&RegClasses.back());
1060 return &RegClasses.back();
1063 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1064 if (CodeGenRegisterClass *RC = Def2RC[Def])
1067 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1071 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1072 CodeGenSubRegIndex *B) {
1073 // Look for an existing entry.
1074 CodeGenSubRegIndex *Comp = A->compose(B);
1078 // None exists, synthesize one.
1079 std::string Name = A->getName() + "_then_" + B->getName();
1080 Comp = createSubRegIndex(Name, A->getNamespace());
1081 A->addComposite(B, Comp);
1085 CodeGenSubRegIndex *CodeGenRegBank::
1086 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
1087 assert(Parts.size() > 1 && "Need two parts to concatenate");
1089 // Look for an existing entry.
1090 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1094 // None exists, synthesize one.
1095 std::string Name = Parts.front()->getName();
1096 // Determine whether all parts are contiguous.
1097 bool isContinuous = true;
1098 unsigned Size = Parts.front()->Size;
1099 unsigned LastOffset = Parts.front()->Offset;
1100 unsigned LastSize = Parts.front()->Size;
1101 for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1103 Name += Parts[i]->getName();
1104 Size += Parts[i]->Size;
1105 if (Parts[i]->Offset != (LastOffset + LastSize))
1106 isContinuous = false;
1107 LastOffset = Parts[i]->Offset;
1108 LastSize = Parts[i]->Size;
1110 Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1112 Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
1116 void CodeGenRegBank::computeComposites() {
1117 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1118 // and many registers will share TopoSigs on regular architectures.
1119 BitVector TopoSigs(getNumTopoSigs());
1121 for (const auto &Reg1 : Registers) {
1122 // Skip identical subreg structures already processed.
1123 if (TopoSigs.test(Reg1.getTopoSig()))
1125 TopoSigs.set(Reg1.getTopoSig());
1127 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1128 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1129 e1 = SRM1.end(); i1 != e1; ++i1) {
1130 CodeGenSubRegIndex *Idx1 = i1->first;
1131 CodeGenRegister *Reg2 = i1->second;
1132 // Ignore identity compositions.
1135 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1136 // Try composing Idx1 with another SubRegIndex.
1137 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1138 e2 = SRM2.end(); i2 != e2; ++i2) {
1139 CodeGenSubRegIndex *Idx2 = i2->first;
1140 CodeGenRegister *Reg3 = i2->second;
1141 // Ignore identity compositions.
1144 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1145 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
1146 assert(Idx3 && "Sub-register doesn't have an index");
1148 // Conflicting composition? Emit a warning but allow it.
1149 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1150 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1151 " and " + Idx2->getQualifiedName() +
1152 " compose ambiguously as " + Prev->getQualifiedName() +
1153 " or " + Idx3->getQualifiedName());
1159 // Compute lane masks. This is similar to register units, but at the
1160 // sub-register index level. Each bit in the lane mask is like a register unit
1161 // class, and two lane masks will have a bit in common if two sub-register
1162 // indices overlap in some register.
1164 // Conservatively share a lane mask bit if two sub-register indices overlap in
1165 // some registers, but not in others. That shouldn't happen a lot.
1166 void CodeGenRegBank::computeSubRegLaneMasks() {
1167 // First assign individual bits to all the leaf indices.
1169 // Determine mask of lanes that cover their registers.
1170 CoveringLanes = ~0u;
1171 for (auto &Idx : SubRegIndices) {
1172 if (Idx.getComposites().empty()) {
1175 Twine("Ran out of lanemask bits to represent subregister ")
1178 Idx.LaneMask = 1u << Bit;
1185 // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1186 // here is that for each possible target subregister we look at the leafs
1187 // in the subregister graph that compose for this target and create
1188 // transformation sequences for the lanemasks. Each step in the sequence
1189 // consists of a bitmask and a bitrotate operation. As the rotation amounts
1190 // are usually the same for many subregisters we can easily combine the steps
1191 // by combining the masks.
1192 for (const auto &Idx : SubRegIndices) {
1193 const auto &Composites = Idx.getComposites();
1194 auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1196 if (Composites.empty()) {
1197 // Moving from a class with no subregisters we just had a single lane:
1198 // The subregister must be a leaf subregister and only occupies 1 bit.
1199 // Move the bit from the class without subregisters into that position.
1200 unsigned DstBit = Log2_32(Idx.LaneMask);
1201 assert(Idx.LaneMask == 1u << DstBit && "Must be a leaf subregister");
1202 MaskRolPair MaskRol = { 1, (uint8_t)DstBit };
1203 LaneTransforms.push_back(MaskRol);
1205 // Go through all leaf subregisters and find the ones that compose with
1206 // Idx. These make out all possible valid bits in the lane mask we want to
1207 // transform. Looking only at the leafs ensure that only a single bit in
1209 unsigned NextBit = 0;
1210 for (auto &Idx2 : SubRegIndices) {
1211 // Skip non-leaf subregisters.
1212 if (!Idx2.getComposites().empty())
1214 // Replicate the behaviour from the lane mask generation loop above.
1215 unsigned SrcBit = NextBit;
1216 unsigned SrcMask = 1u << SrcBit;
1219 assert(Idx2.LaneMask == SrcMask);
1221 // Get the composed subregister if there is any.
1222 auto C = Composites.find(&Idx2);
1223 if (C == Composites.end())
1225 const CodeGenSubRegIndex *Composite = C->second;
1226 // The Composed subreg should be a leaf subreg too
1227 assert(Composite->getComposites().empty());
1229 // Create Mask+Rotate operation and merge with existing ops if possible.
1230 unsigned DstBit = Log2_32(Composite->LaneMask);
1231 int Shift = DstBit - SrcBit;
1232 uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift : 32+Shift;
1233 for (auto &I : LaneTransforms) {
1234 if (I.RotateLeft == RotateLeft) {
1240 MaskRolPair MaskRol = { SrcMask, RotateLeft };
1241 LaneTransforms.push_back(MaskRol);
1246 // Optimize if the transformation consists of one step only: Set mask to
1247 // 0xffffffff (including some irrelevant invalid bits) so that it should
1248 // merge with more entries later while compressing the table.
1249 if (LaneTransforms.size() == 1)
1250 LaneTransforms[0].Mask = ~0u;
1252 // Further compression optimization: For invalid compositions resulting
1253 // in a sequence with 0 entries we can just pick any other. Choose
1254 // Mask 0xffffffff with Rotation 0.
1255 if (LaneTransforms.size() == 0) {
1256 MaskRolPair P = { ~0u, 0 };
1257 LaneTransforms.push_back(P);
1261 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1262 // by the sub-register graph? This doesn't occur in any known targets.
1264 // Inherit lanes from composites.
1265 for (const auto &Idx : SubRegIndices) {
1266 unsigned Mask = Idx.computeLaneMask();
1267 // If some super-registers without CoveredBySubRegs use this index, we can
1268 // no longer assume that the lanes are covering their registers.
1269 if (!Idx.AllSuperRegsCovered)
1270 CoveringLanes &= ~Mask;
1273 // Compute lane mask combinations for register classes.
1274 for (auto &RegClass : RegClasses) {
1275 unsigned LaneMask = 0;
1276 for (const auto &SubRegIndex : SubRegIndices) {
1277 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1279 LaneMask |= SubRegIndex.LaneMask;
1282 // For classes without any subregisters set LaneMask to 1 instead of 0.
1283 // This makes it easier for client code to handle classes uniformly.
1287 RegClass.LaneMask = LaneMask;
1292 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1293 // the transitive closure of the union of overlapping register
1294 // classes. Together, the UberRegSets form a partition of the registers. If we
1295 // consider overlapping register classes to be connected, then each UberRegSet
1296 // is a set of connected components.
1298 // An UberRegSet will likely be a horizontal slice of register names of
1299 // the same width. Nontrivial subregisters should then be in a separate
1300 // UberRegSet. But this property isn't required for valid computation of
1301 // register unit weights.
1303 // A Weight field caches the max per-register unit weight in each UberRegSet.
1305 // A set of SingularDeterminants flags single units of some register in this set
1306 // for which the unit weight equals the set weight. These units should not have
1307 // their weight increased.
1309 CodeGenRegister::Vec Regs;
1311 CodeGenRegister::RegUnitList SingularDeterminants;
1313 UberRegSet(): Weight(0) {}
1317 // Partition registers into UberRegSets, where each set is the transitive
1318 // closure of the union of overlapping register classes.
1320 // UberRegSets[0] is a special non-allocatable set.
1321 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1322 std::vector<UberRegSet*> &RegSets,
1323 CodeGenRegBank &RegBank) {
1325 const auto &Registers = RegBank.getRegisters();
1327 // The Register EnumValue is one greater than its index into Registers.
1328 assert(Registers.size() == Registers.back().EnumValue &&
1329 "register enum value mismatch");
1331 // For simplicitly make the SetID the same as EnumValue.
1332 IntEqClasses UberSetIDs(Registers.size()+1);
1333 std::set<unsigned> AllocatableRegs;
1334 for (auto &RegClass : RegBank.getRegClasses()) {
1335 if (!RegClass.Allocatable)
1338 const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1342 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1343 assert(USetID && "register number 0 is invalid");
1345 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1346 for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1347 AllocatableRegs.insert((*I)->EnumValue);
1348 UberSetIDs.join(USetID, (*I)->EnumValue);
1351 // Combine non-allocatable regs.
1352 for (const auto &Reg : Registers) {
1353 unsigned RegNum = Reg.EnumValue;
1354 if (AllocatableRegs.count(RegNum))
1357 UberSetIDs.join(0, RegNum);
1359 UberSetIDs.compress();
1361 // Make the first UberSet a special unallocatable set.
1362 unsigned ZeroID = UberSetIDs[0];
1364 // Insert Registers into the UberSets formed by union-find.
1365 // Do not resize after this.
1366 UberSets.resize(UberSetIDs.getNumClasses());
1368 for (const CodeGenRegister &Reg : Registers) {
1369 unsigned USetID = UberSetIDs[Reg.EnumValue];
1372 else if (USetID == ZeroID)
1375 UberRegSet *USet = &UberSets[USetID];
1376 USet->Regs.push_back(&Reg);
1377 sortAndUniqueRegisters(USet->Regs);
1378 RegSets[i++] = USet;
1382 // Recompute each UberSet weight after changing unit weights.
1383 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1384 CodeGenRegBank &RegBank) {
1385 // Skip the first unallocatable set.
1386 for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
1387 E = UberSets.end(); I != E; ++I) {
1389 // Initialize all unit weights in this set, and remember the max units/reg.
1390 const CodeGenRegister *Reg = nullptr;
1391 unsigned MaxWeight = 0, Weight = 0;
1392 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1393 if (Reg != UnitI.getReg()) {
1394 if (Weight > MaxWeight)
1396 Reg = UnitI.getReg();
1399 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1402 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1406 if (Weight > MaxWeight)
1408 if (I->Weight != MaxWeight) {
1410 dbgs() << "UberSet " << I - UberSets.begin() << " Weight " << MaxWeight;
1411 for (auto &Unit : I->Regs)
1412 dbgs() << " " << Unit->getName();
1414 // Update the set weight.
1415 I->Weight = MaxWeight;
1418 // Find singular determinants.
1419 for (const auto R : I->Regs) {
1420 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) {
1421 I->SingularDeterminants |= R->getRegUnits();
1427 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1428 // a register and its subregisters so that they have the same weight as their
1429 // UberSet. Self-recursion processes the subregister tree in postorder so
1430 // subregisters are normalized first.
1433 // - creates new adopted register units
1434 // - causes superregisters to inherit adopted units
1435 // - increases the weight of "singular" units
1436 // - induces recomputation of UberWeights.
1437 static bool normalizeWeight(CodeGenRegister *Reg,
1438 std::vector<UberRegSet> &UberSets,
1439 std::vector<UberRegSet*> &RegSets,
1440 SparseBitVector<> &NormalRegs,
1441 CodeGenRegister::RegUnitList &NormalUnits,
1442 CodeGenRegBank &RegBank) {
1443 if (NormalRegs.test(Reg->EnumValue))
1445 NormalRegs.set(Reg->EnumValue);
1447 bool Changed = false;
1448 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1449 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1450 SRE = SRM.end(); SRI != SRE; ++SRI) {
1451 if (SRI->second == Reg)
1452 continue; // self-cycles happen
1454 Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1455 NormalRegs, NormalUnits, RegBank);
1457 // Postorder register normalization.
1459 // Inherit register units newly adopted by subregisters.
1460 if (Reg->inheritRegUnits(RegBank))
1461 computeUberWeights(UberSets, RegBank);
1463 // Check if this register is too skinny for its UberRegSet.
1464 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1466 unsigned RegWeight = Reg->getWeight(RegBank);
1467 if (UberSet->Weight > RegWeight) {
1468 // A register unit's weight can be adjusted only if it is the singular unit
1469 // for this register, has not been used to normalize a subregister's set,
1470 // and has not already been used to singularly determine this UberRegSet.
1471 unsigned AdjustUnit = *Reg->getRegUnits().begin();
1472 if (Reg->getRegUnits().count() != 1
1473 || hasRegUnit(NormalUnits, AdjustUnit)
1474 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1475 // We don't have an adjustable unit, so adopt a new one.
1476 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1477 Reg->adoptRegUnit(AdjustUnit);
1478 // Adopting a unit does not immediately require recomputing set weights.
1481 // Adjust the existing single unit.
1482 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1483 // The unit may be shared among sets and registers within this set.
1484 computeUberWeights(UberSets, RegBank);
1489 // Mark these units normalized so superregisters can't change their weights.
1490 NormalUnits |= Reg->getRegUnits();
1495 // Compute a weight for each register unit created during getSubRegs.
1497 // The goal is that two registers in the same class will have the same weight,
1498 // where each register's weight is defined as sum of its units' weights.
1499 void CodeGenRegBank::computeRegUnitWeights() {
1500 std::vector<UberRegSet> UberSets;
1501 std::vector<UberRegSet*> RegSets(Registers.size());
1502 computeUberSets(UberSets, RegSets, *this);
1503 // UberSets and RegSets are now immutable.
1505 computeUberWeights(UberSets, *this);
1507 // Iterate over each Register, normalizing the unit weights until reaching
1509 unsigned NumIters = 0;
1510 for (bool Changed = true; Changed; ++NumIters) {
1511 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1513 for (auto &Reg : Registers) {
1514 CodeGenRegister::RegUnitList NormalUnits;
1515 SparseBitVector<> NormalRegs;
1516 Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
1517 NormalUnits, *this);
1522 // Find a set in UniqueSets with the same elements as Set.
1523 // Return an iterator into UniqueSets.
1524 static std::vector<RegUnitSet>::const_iterator
1525 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1526 const RegUnitSet &Set) {
1527 std::vector<RegUnitSet>::const_iterator
1528 I = UniqueSets.begin(), E = UniqueSets.end();
1530 if (I->Units == Set.Units)
1536 // Return true if the RUSubSet is a subset of RUSuperSet.
1537 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1538 const std::vector<unsigned> &RUSuperSet) {
1539 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1540 RUSubSet.begin(), RUSubSet.end());
1543 /// Iteratively prune unit sets. Prune subsets that are close to the superset,
1544 /// but with one or two registers removed. We occasionally have registers like
1545 /// APSR and PC thrown in with the general registers. We also see many
1546 /// special-purpose register subsets, such as tail-call and Thumb
1547 /// encodings. Generating all possible overlapping sets is combinatorial and
1548 /// overkill for modeling pressure. Ideally we could fix this statically in
1549 /// tablegen by (1) having the target define register classes that only include
1550 /// the allocatable registers and marking other classes as non-allocatable and
1551 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1552 /// the purpose of pressure. However, we make an attempt to handle targets that
1553 /// are not nicely defined by merging nearly identical register unit sets
1554 /// statically. This generates smaller tables. Then, dynamically, we adjust the
1555 /// set limit by filtering the reserved registers.
1557 /// Merge sets only if the units have the same weight. For example, on ARM,
1558 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1559 /// should not expand the S set to include D regs.
1560 void CodeGenRegBank::pruneUnitSets() {
1561 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1563 // Form an equivalence class of UnitSets with no significant difference.
1564 std::vector<unsigned> SuperSetIDs;
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1566 SubIdx != EndIdx; ++SubIdx) {
1567 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1568 unsigned SuperIdx = 0;
1569 for (; SuperIdx != EndIdx; ++SuperIdx) {
1570 if (SuperIdx == SubIdx)
1573 unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
1574 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1575 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1576 && (SubSet.Units.size() + 3 > SuperSet.Units.size())
1577 && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
1578 && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
1579 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
1581 // We can pick any of the set names for the merged set. Go for the
1582 // shortest one to avoid picking the name of one of the classes that are
1583 // artificially created by tablegen. So "FPR128_lo" instead of
1584 // "QQQQ_with_qsub3_in_FPR128_lo".
1585 if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
1586 RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
1590 if (SuperIdx == EndIdx)
1591 SuperSetIDs.push_back(SubIdx);
1593 // Populate PrunedUnitSets with each equivalence class's superset.
1594 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1595 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1596 unsigned SuperIdx = SuperSetIDs[i];
1597 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1598 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1600 RegUnitSets.swap(PrunedUnitSets);
1603 // Create a RegUnitSet for each RegClass that contains all units in the class
1604 // including adopted units that are necessary to model register pressure. Then
1605 // iteratively compute RegUnitSets such that the union of any two overlapping
1606 // RegUnitSets is repreresented.
1608 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1609 // RegUnitSet that is a superset of that RegUnitClass.
1610 void CodeGenRegBank::computeRegUnitSets() {
1611 assert(RegUnitSets.empty() && "dirty RegUnitSets");
1613 // Compute a unique RegUnitSet for each RegClass.
1614 auto &RegClasses = getRegClasses();
1615 for (auto &RC : RegClasses) {
1616 if (!RC.Allocatable)
1619 // Speculatively grow the RegUnitSets to hold the new set.
1620 RegUnitSets.resize(RegUnitSets.size() + 1);
1621 RegUnitSets.back().Name = RC.getName();
1623 // Compute a sorted list of units in this class.
1624 RC.buildRegUnitSet(RegUnitSets.back().Units);
1626 // Find an existing RegUnitSet.
1627 std::vector<RegUnitSet>::const_iterator SetI =
1628 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1629 if (SetI != std::prev(RegUnitSets.end()))
1630 RegUnitSets.pop_back();
1633 DEBUG(dbgs() << "\nBefore pruning:\n";
1634 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1635 USIdx < USEnd; ++USIdx) {
1636 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1638 for (auto &U : RegUnitSets[USIdx].Units)
1639 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1643 // Iteratively prune unit sets.
1646 DEBUG(dbgs() << "\nBefore union:\n";
1647 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1648 USIdx < USEnd; ++USIdx) {
1649 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1651 for (auto &U : RegUnitSets[USIdx].Units)
1652 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1655 dbgs() << "\nUnion sets:\n");
1657 // Iterate over all unit sets, including new ones added by this loop.
1658 unsigned NumRegUnitSubSets = RegUnitSets.size();
1659 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1660 // In theory, this is combinatorial. In practice, it needs to be bounded
1661 // by a small number of sets for regpressure to be efficient.
1662 // If the assert is hit, we need to implement pruning.
1663 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1665 // Compare new sets with all original classes.
1666 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1667 SearchIdx != EndIdx; ++SearchIdx) {
1668 std::set<unsigned> Intersection;
1669 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1670 RegUnitSets[Idx].Units.end(),
1671 RegUnitSets[SearchIdx].Units.begin(),
1672 RegUnitSets[SearchIdx].Units.end(),
1673 std::inserter(Intersection, Intersection.begin()));
1674 if (Intersection.empty())
1677 // Speculatively grow the RegUnitSets to hold the new set.
1678 RegUnitSets.resize(RegUnitSets.size() + 1);
1679 RegUnitSets.back().Name =
1680 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1682 std::set_union(RegUnitSets[Idx].Units.begin(),
1683 RegUnitSets[Idx].Units.end(),
1684 RegUnitSets[SearchIdx].Units.begin(),
1685 RegUnitSets[SearchIdx].Units.end(),
1686 std::inserter(RegUnitSets.back().Units,
1687 RegUnitSets.back().Units.begin()));
1689 // Find an existing RegUnitSet, or add the union to the unique sets.
1690 std::vector<RegUnitSet>::const_iterator SetI =
1691 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1692 if (SetI != std::prev(RegUnitSets.end()))
1693 RegUnitSets.pop_back();
1695 DEBUG(dbgs() << "UnitSet " << RegUnitSets.size()-1
1696 << " " << RegUnitSets.back().Name << ":";
1697 for (auto &U : RegUnitSets.back().Units)
1698 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1704 // Iteratively prune unit sets after inferring supersets.
1707 DEBUG(dbgs() << "\n";
1708 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1709 USIdx < USEnd; ++USIdx) {
1710 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name
1712 for (auto &U : RegUnitSets[USIdx].Units)
1713 dbgs() << " " << RegUnits[U].Roots[0]->getName();
1717 // For each register class, list the UnitSets that are supersets.
1718 RegClassUnitSets.resize(RegClasses.size());
1720 for (auto &RC : RegClasses) {
1722 if (!RC.Allocatable)
1725 // Recompute the sorted list of units in this class.
1726 std::vector<unsigned> RCRegUnits;
1727 RC.buildRegUnitSet(RCRegUnits);
1729 // Don't increase pressure for unallocatable regclasses.
1730 if (RCRegUnits.empty())
1733 DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n";
1734 for (auto &U : RCRegUnits)
1735 dbgs() << RegUnits[U].getRoots()[0]->getName() << " ";
1736 dbgs() << "\n UnitSetIDs:");
1738 // Find all supersets.
1739 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1740 USIdx != USEnd; ++USIdx) {
1741 if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
1742 DEBUG(dbgs() << " " << USIdx);
1743 RegClassUnitSets[RCIdx].push_back(USIdx);
1746 DEBUG(dbgs() << "\n");
1747 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1750 // For each register unit, ensure that we have the list of UnitSets that
1751 // contain the unit. Normally, this matches an existing list of UnitSets for a
1752 // register class. If not, we create a new entry in RegClassUnitSets as a
1753 // "fake" register class.
1754 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
1755 UnitIdx < UnitEnd; ++UnitIdx) {
1756 std::vector<unsigned> RUSets;
1757 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
1758 RegUnitSet &RUSet = RegUnitSets[i];
1759 if (std::find(RUSet.Units.begin(), RUSet.Units.end(), UnitIdx)
1760 == RUSet.Units.end())
1762 RUSets.push_back(i);
1764 unsigned RCUnitSetsIdx = 0;
1765 for (unsigned e = RegClassUnitSets.size();
1766 RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
1767 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
1771 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
1772 if (RCUnitSetsIdx == RegClassUnitSets.size()) {
1773 // Create a new list of UnitSets as a "fake" register class.
1774 RegClassUnitSets.resize(RCUnitSetsIdx + 1);
1775 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
1780 void CodeGenRegBank::computeRegUnitLaneMasks() {
1781 for (auto &Register : Registers) {
1782 // Create an initial lane mask for all register units.
1783 const auto &RegUnits = Register.getRegUnits();
1784 CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(RegUnits.count(), 0);
1785 // Iterate through SubRegisters.
1786 typedef CodeGenRegister::SubRegMap SubRegMap;
1787 const SubRegMap &SubRegs = Register.getSubRegs();
1788 for (SubRegMap::const_iterator S = SubRegs.begin(),
1789 SE = SubRegs.end(); S != SE; ++S) {
1790 CodeGenRegister *SubReg = S->second;
1791 // Ignore non-leaf subregisters, their lane masks are fully covered by
1792 // the leaf subregisters anyway.
1793 if (SubReg->getSubRegs().size() != 0)
1795 CodeGenSubRegIndex *SubRegIndex = S->first;
1796 const CodeGenRegister *SubRegister = S->second;
1797 unsigned LaneMask = SubRegIndex->LaneMask;
1798 // Distribute LaneMask to Register Units touched.
1799 for (unsigned SUI : SubRegister->getRegUnits()) {
1802 for (unsigned RU : RegUnits) {
1804 RegUnitLaneMasks[u] |= LaneMask;
1814 Register.setRegUnitLaneMasks(RegUnitLaneMasks);
1818 void CodeGenRegBank::computeDerivedInfo() {
1819 computeComposites();
1820 computeSubRegLaneMasks();
1822 // Compute a weight for each register unit created during getSubRegs.
1823 // This may create adopted register units (with unit # >= NumNativeRegUnits).
1824 computeRegUnitWeights();
1826 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
1827 // supersets for the union of overlapping sets.
1828 computeRegUnitSets();
1830 computeRegUnitLaneMasks();
1832 // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
1833 for (CodeGenRegisterClass &RC : RegClasses) {
1834 RC.HasDisjunctSubRegs = false;
1835 RC.CoveredBySubRegs = true;
1836 for (const CodeGenRegister *Reg : RC.getMembers()) {
1837 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
1838 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
1842 // Get the weight of each set.
1843 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
1844 RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units);
1846 // Find the order of each set.
1847 RegUnitSetOrder.reserve(RegUnitSets.size());
1848 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
1849 RegUnitSetOrder.push_back(Idx);
1851 std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(),
1852 [this](unsigned ID1, unsigned ID2) {
1853 return getRegPressureSet(ID1).Units.size() <
1854 getRegPressureSet(ID2).Units.size();
1856 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1857 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
1862 // Synthesize missing register class intersections.
1864 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
1865 // returns a maximal register class for all X.
1867 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
1868 assert(!RegClasses.empty());
1869 // Stash the iterator to the last element so that this loop doesn't visit
1870 // elements added by the getOrCreateSubClass call within it.
1871 for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end());
1872 I != std::next(E); ++I) {
1873 CodeGenRegisterClass *RC1 = RC;
1874 CodeGenRegisterClass *RC2 = &*I;
1878 // Compute the set intersection of RC1 and RC2.
1879 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
1880 const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
1881 CodeGenRegister::Vec Intersection;
1882 std::set_intersection(
1883 Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
1884 std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
1886 // Skip disjoint class pairs.
1887 if (Intersection.empty())
1890 // If RC1 and RC2 have different spill sizes or alignments, use the
1891 // larger size for sub-classing. If they are equal, prefer RC1.
1892 if (RC2->SpillSize > RC1->SpillSize ||
1893 (RC2->SpillSize == RC1->SpillSize &&
1894 RC2->SpillAlignment > RC1->SpillAlignment))
1895 std::swap(RC1, RC2);
1897 getOrCreateSubClass(RC1, &Intersection,
1898 RC1->getName() + "_and_" + RC2->getName());
1903 // Synthesize missing sub-classes for getSubClassWithSubReg().
1905 // Make sure that the set of registers in RC with a given SubIdx sub-register
1906 // form a register class. Update RC->SubClassWithSubReg.
1908 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
1909 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
1910 typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
1911 deref<llvm::less>> SubReg2SetMap;
1913 // Compute the set of registers supporting each SubRegIndex.
1914 SubReg2SetMap SRSets;
1915 for (const auto R : RC->getMembers()) {
1916 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
1917 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
1918 E = SRM.end(); I != E; ++I)
1919 SRSets[I->first].push_back(R);
1922 for (auto I : SRSets)
1923 sortAndUniqueRegisters(I.second);
1925 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
1926 // numerical order to visit synthetic indices last.
1927 for (const auto &SubIdx : SubRegIndices) {
1928 SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
1929 // Unsupported SubRegIndex. Skip it.
1930 if (I == SRSets.end())
1932 // In most cases, all RC registers support the SubRegIndex.
1933 if (I->second.size() == RC->getMembers().size()) {
1934 RC->setSubClassWithSubReg(&SubIdx, RC);
1937 // This is a real subset. See if we have a matching class.
1938 CodeGenRegisterClass *SubRC =
1939 getOrCreateSubClass(RC, &I->second,
1940 RC->getName() + "_with_" + I->first->getName());
1941 RC->setSubClassWithSubReg(&SubIdx, SubRC);
1946 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
1948 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
1949 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
1952 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
1953 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
1954 SmallVector<std::pair<const CodeGenRegister*,
1955 const CodeGenRegister*>, 16> SSPairs;
1956 BitVector TopoSigs(getNumTopoSigs());
1958 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
1959 for (auto &SubIdx : SubRegIndices) {
1960 // Skip indexes that aren't fully supported by RC's registers. This was
1961 // computed by inferSubClassWithSubReg() above which should have been
1963 if (RC->getSubClassWithSubReg(&SubIdx) != RC)
1966 // Build list of (Super, Sub) pairs for this SubIdx.
1969 for (const auto Super : RC->getMembers()) {
1970 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second;
1971 assert(Sub && "Missing sub-register");
1972 SSPairs.push_back(std::make_pair(Super, Sub));
1973 TopoSigs.set(Sub->getTopoSig());
1976 // Iterate over sub-register class candidates. Ignore classes created by
1977 // this loop. They will never be useful.
1978 // Store an iterator to the last element (not end) so that this loop doesn't
1979 // visit newly inserted elements.
1980 assert(!RegClasses.empty());
1981 for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end());
1982 I != std::next(E); ++I) {
1983 CodeGenRegisterClass &SubRC = *I;
1984 // Topological shortcut: SubRC members have the wrong shape.
1985 if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
1987 // Compute the subset of RC that maps into SubRC.
1988 CodeGenRegister::Vec SubSetVec;
1989 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
1990 if (SubRC.contains(SSPairs[i].second))
1991 SubSetVec.push_back(SSPairs[i].first);
1993 if (SubSetVec.empty())
1996 // RC injects completely into SubRC.
1997 sortAndUniqueRegisters(SubSetVec);
1998 if (SubSetVec.size() == SSPairs.size()) {
1999 SubRC.addSuperRegClass(&SubIdx, RC);
2003 // Only a subset of RC maps into SubRC. Make sure it is represented by a
2005 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
2006 SubIdx.getName() + "_in_" +
2014 // Infer missing register classes.
2016 void CodeGenRegBank::computeInferredRegisterClasses() {
2017 assert(!RegClasses.empty());
2018 // When this function is called, the register classes have not been sorted
2019 // and assigned EnumValues yet. That means getSubClasses(),
2020 // getSuperClasses(), and hasSubClass() functions are defunct.
2022 // Use one-before-the-end so it doesn't move forward when new elements are
2024 auto FirstNewRC = std::prev(RegClasses.end());
2026 // Visit all register classes, including the ones being added by the loop.
2027 // Watch out for iterator invalidation here.
2028 for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2029 CodeGenRegisterClass *RC = &*I;
2031 // Synthesize answers for getSubClassWithSubReg().
2032 inferSubClassWithSubReg(RC);
2034 // Synthesize answers for getCommonSubClass().
2035 inferCommonSubClass(RC);
2037 // Synthesize answers for getMatchingSuperRegClass().
2038 inferMatchingSuperRegClass(RC);
2040 // New register classes are created while this loop is running, and we need
2041 // to visit all of them. I particular, inferMatchingSuperRegClass needs
2042 // to match old super-register classes with sub-register classes created
2043 // after inferMatchingSuperRegClass was called. At this point,
2044 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2045 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
2046 if (I == FirstNewRC) {
2047 auto NextNewRC = std::prev(RegClasses.end());
2048 for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2;
2050 inferMatchingSuperRegClass(&*I2, E2);
2051 FirstNewRC = NextNewRC;
2056 /// getRegisterClassForRegister - Find the register class that contains the
2057 /// specified physical register. If the register is not in a register class,
2058 /// return null. If the register is in multiple classes, and the classes have a
2059 /// superset-subset relationship and the same set of types, return the
2060 /// superclass. Otherwise return null.
2061 const CodeGenRegisterClass*
2062 CodeGenRegBank::getRegClassForRegister(Record *R) {
2063 const CodeGenRegister *Reg = getReg(R);
2064 const CodeGenRegisterClass *FoundRC = nullptr;
2065 for (const auto &RC : getRegClasses()) {
2066 if (!RC.contains(Reg))
2069 // If this is the first class that contains the register,
2070 // make a note of it and go on to the next class.
2076 // If a register's classes have different types, return null.
2077 if (RC.getValueTypes() != FoundRC->getValueTypes())
2080 // Check to see if the previously found class that contains
2081 // the register is a subclass of the current class. If so,
2082 // prefer the superclass.
2083 if (RC.hasSubClass(FoundRC)) {
2088 // Check to see if the previously found class that contains
2089 // the register is a superclass of the current class. If so,
2090 // prefer the superclass.
2091 if (FoundRC->hasSubClass(&RC))
2094 // Multiple classes, and neither is a superclass of the other.
2101 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2102 SetVector<const CodeGenRegister*> Set;
2104 // First add Regs with all sub-registers.
2105 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2106 CodeGenRegister *Reg = getReg(Regs[i]);
2107 if (Set.insert(Reg))
2108 // Reg is new, add all sub-registers.
2109 // The pre-ordering is not important here.
2110 Reg->addSubRegsPreOrder(Set, *this);
2113 // Second, find all super-registers that are completely covered by the set.
2114 for (unsigned i = 0; i != Set.size(); ++i) {
2115 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
2116 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
2117 const CodeGenRegister *Super = SR[j];
2118 if (!Super->CoveredBySubRegs || Set.count(Super))
2120 // This new super-register is covered by its sub-registers.
2121 bool AllSubsInSet = true;
2122 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2123 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2124 E = SRM.end(); I != E; ++I)
2125 if (!Set.count(I->second)) {
2126 AllSubsInSet = false;
2129 // All sub-registers in Set, add Super as well.
2130 // We will visit Super later to recheck its super-registers.
2136 // Convert to BitVector.
2137 BitVector BV(Registers.size() + 1);
2138 for (unsigned i = 0, e = Set.size(); i != e; ++i)
2139 BV.set(Set[i]->EnumValue);