1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/SparseBitVector.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringMap.h"
27 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/MachineValueType.h"
29 #include "llvm/MC/LaneBitmask.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/TableGen/Record.h"
32 #include "llvm/TableGen/SetTheory.h"
45 template <typename T, typename Vector, typename Set> class SetVector;
47 /// Used to encode a step in a register lane mask transformation.
48 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
49 /// assuming a wraparound at 32bits.
54 bool operator==(const MaskRolPair Other) const {
55 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
57 bool operator!=(const MaskRolPair Other) const {
58 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
62 /// CodeGenSubRegIndex - Represents a sub-register index.
63 class CodeGenSubRegIndex {
66 std::string Namespace;
71 const unsigned EnumValue;
72 mutable LaneBitmask LaneMask;
73 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
75 // Are all super-registers containing this SubRegIndex covered by their
77 bool AllSuperRegsCovered;
79 CodeGenSubRegIndex(Record *R, unsigned Enum);
80 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
82 const std::string &getName() const { return Name; }
83 const std::string &getNamespace() const { return Namespace; }
84 std::string getQualifiedName() const;
86 // Map of composite subreg indices.
87 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
88 deref<llvm::less>> CompMap;
90 // Returns the subreg index that results from composing this with Idx.
91 // Returns NULL if this and Idx don't compose.
92 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
93 CompMap::const_iterator I = Composed.find(Idx);
94 return I == Composed.end() ? nullptr : I->second;
97 // Add a composite subreg index: this+A = B.
98 // Return a conflicting composite, or NULL
99 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
100 CodeGenSubRegIndex *B) {
102 std::pair<CompMap::iterator, bool> Ins =
103 Composed.insert(std::make_pair(A, B));
104 // Synthetic subreg indices that aren't contiguous (for instance ARM
105 // register tuples) don't have a bit range, so it's OK to let
106 // B->Offset == -1. For the other cases, accumulate the offset and set
107 // the size here. Only do so if there is no offset yet though.
108 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
109 (B->Offset == (uint16_t)-1)) {
110 B->Offset = Offset + A->Offset;
113 return (Ins.second || Ins.first->second == B) ? nullptr
117 // Update the composite maps of components specified in 'ComposedOf'.
118 void updateComponents(CodeGenRegBank&);
120 // Return the map of composites.
121 const CompMap &getComposites() const { return Composed; }
123 // Compute LaneMask from Composed. Return LaneMask.
124 LaneBitmask computeLaneMask() const;
130 inline bool operator<(const CodeGenSubRegIndex &A,
131 const CodeGenSubRegIndex &B) {
132 return A.EnumValue < B.EnumValue;
135 /// CodeGenRegister - Represents a register definition.
136 struct CodeGenRegister {
140 bool CoveredBySubRegs;
141 bool HasDisjunctSubRegs;
143 // Map SubRegIndex -> Register.
144 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
147 CodeGenRegister(Record *R, unsigned Enum);
149 const StringRef getName() const;
151 // Extract more information from TheDef. This is used to build an object
152 // graph after all CodeGenRegister objects have been created.
153 void buildObjectGraph(CodeGenRegBank&);
155 // Lazily compute a map of all sub-registers.
156 // This includes unique entries for all sub-sub-registers.
157 const SubRegMap &computeSubRegs(CodeGenRegBank&);
159 // Compute extra sub-registers by combining the existing sub-registers.
160 void computeSecondarySubRegs(CodeGenRegBank&);
162 // Add this as a super-register to all sub-registers after the sub-register
163 // graph has been built.
164 void computeSuperRegs(CodeGenRegBank&);
166 const SubRegMap &getSubRegs() const {
167 assert(SubRegsComplete && "Must precompute sub-registers");
171 // Add sub-registers to OSet following a pre-order defined by the .td file.
172 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
173 CodeGenRegBank&) const;
175 // Return the sub-register index naming Reg as a sub-register of this
176 // register. Returns NULL if Reg is not a sub-register.
177 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
178 return SubReg2Idx.lookup(Reg);
181 typedef std::vector<const CodeGenRegister*> SuperRegList;
183 // Get the list of super-registers in topological order, small to large.
184 // This is valid after computeSubRegs visits all registers during RegBank
186 const SuperRegList &getSuperRegs() const {
187 assert(SubRegsComplete && "Must precompute sub-registers");
191 // Get the list of ad hoc aliases. The graph is symmetric, so the list
192 // contains all registers in 'Aliases', and all registers that mention this
193 // register in 'Aliases'.
194 ArrayRef<CodeGenRegister*> getExplicitAliases() const {
195 return ExplicitAliases;
198 // Get the topological signature of this register. This is a small integer
199 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
200 // identical sub-register structure. That is, they support the same set of
201 // sub-register indices mapping to the same kind of sub-registers
203 unsigned getTopoSig() const {
204 assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
208 // List of register units in ascending order.
209 typedef SparseBitVector<> RegUnitList;
210 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
212 // How many entries in RegUnitList are native?
213 RegUnitList NativeRegUnits;
215 // Get the list of register units.
216 // This is only valid after computeSubRegs() completes.
217 const RegUnitList &getRegUnits() const { return RegUnits; }
219 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const {
220 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
223 // Get the native register units. This is a prefix of getRegUnits().
224 RegUnitList getNativeRegUnits() const {
225 return NativeRegUnits;
228 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
229 RegUnitLaneMasks = LaneMasks;
232 // Inherit register units from subregisters.
233 // Return true if the RegUnits changed.
234 bool inheritRegUnits(CodeGenRegBank &RegBank);
236 // Adopt a register unit for pressure tracking.
237 // A unit is adopted iff its unit number is >= NativeRegUnits.count().
238 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
240 // Get the sum of this register's register unit weights.
241 unsigned getWeight(const CodeGenRegBank &RegBank) const;
243 // Canonically ordered set.
244 typedef std::vector<const CodeGenRegister*> Vec;
247 bool SubRegsComplete;
248 bool SuperRegsComplete;
251 // The sub-registers explicit in the .td file form a tree.
252 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
253 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
255 // Explicit ad hoc aliases, symmetrized to form an undirected graph.
256 SmallVector<CodeGenRegister*, 8> ExplicitAliases;
258 // Super-registers where this is the first explicit sub-register.
259 SuperRegList LeadingSuperRegs;
262 SuperRegList SuperRegs;
263 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
264 RegUnitList RegUnits;
265 RegUnitLaneMaskList RegUnitLaneMasks;
268 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
269 return A.EnumValue < B.EnumValue;
272 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
273 return A.EnumValue == B.EnumValue;
276 class CodeGenRegisterClass {
277 CodeGenRegister::Vec Members;
278 // Allocation orders. Order[0] always contains all registers in Members.
279 std::vector<SmallVector<Record*, 16>> Orders;
280 // Bit mask of sub-classes including this, indexed by their EnumValue.
281 BitVector SubClasses;
282 // List of super-classes, topologocally ordered to have the larger classes
283 // first. This is the same as sorting by EnumValue.
284 SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
288 // For a synthesized class, inherit missing properties from the nearest
290 void inheritProperties(CodeGenRegBank&);
292 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
293 // registers have a SubRegIndex sub-register.
294 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
297 // Map SubRegIndex -> set of super-reg classes. This is all register
298 // classes SuperRC such that:
300 // R:SubRegIndex in this RC for all R in SuperRC.
302 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
305 // Bit vector of TopoSigs for the registers in this class. This will be
306 // very sparse on regular architectures.
312 SmallVector<MVT::SimpleValueType, 4> VTs;
314 unsigned SpillAlignment;
317 StringRef AltOrderSelect;
318 uint8_t AllocationPriority;
319 /// Contains the combination of the lane masks of all subregisters.
320 LaneBitmask LaneMask;
321 /// True if there are at least 2 subregisters which do not interfere.
322 bool HasDisjunctSubRegs;
323 bool CoveredBySubRegs;
325 // Return the Record that defined this class, or NULL if the class was
326 // created by TableGen.
327 Record *getDef() const { return TheDef; }
329 const std::string &getName() const { return Name; }
330 std::string getQualifiedName() const;
331 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
332 bool hasValueType(MVT::SimpleValueType VT) const {
333 return std::find(VTs.begin(), VTs.end(), VT) != VTs.end();
335 unsigned getNumValueTypes() const { return VTs.size(); }
337 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
338 if (VTNum < VTs.size())
340 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
343 // Return true if this this class contains the register.
344 bool contains(const CodeGenRegister*) const;
346 // Returns true if RC is a subclass.
347 // RC is a sub-class of this class if it is a valid replacement for any
348 // instruction operand where a register of this classis required. It must
349 // satisfy these conditions:
351 // 1. All RC registers are also in this.
352 // 2. The RC spill size must not be smaller than our spill size.
353 // 3. RC spill alignment must be compatible with ours.
355 bool hasSubClass(const CodeGenRegisterClass *RC) const {
356 return SubClasses.test(RC->EnumValue);
359 // getSubClassWithSubReg - Returns the largest sub-class where all
360 // registers have a SubIdx sub-register.
361 CodeGenRegisterClass *
362 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
363 return SubClassWithSubReg.lookup(SubIdx);
366 /// Find largest subclass where all registers have SubIdx subregisters in
367 /// SubRegClass and the largest subregister class that contains those
368 /// subregisters without (as far as possible) also containing additional registers.
370 /// This can be used to find a suitable pair of classes for subregister copies.
371 /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is
372 /// a class where every register has SubIdx and SubRegClass is a class where
373 /// every register is covered by the SubIdx subregister of SubClass.
374 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
375 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
376 const CodeGenSubRegIndex *SubIdx) const;
378 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
379 CodeGenRegisterClass *SubRC) {
380 SubClassWithSubReg[SubIdx] = SubRC;
383 // getSuperRegClasses - Returns a bit vector of all register classes
384 // containing only SubIdx super-registers of this class.
385 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
386 BitVector &Out) const;
388 // addSuperRegClass - Add a class containing only SubIdx super-registers.
389 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
390 CodeGenRegisterClass *SuperRC) {
391 SuperRegClasses[SubIdx].insert(SuperRC);
394 // getSubClasses - Returns a constant BitVector of subclasses indexed by
396 // The SubClasses vector includes an entry for this class.
397 const BitVector &getSubClasses() const { return SubClasses; }
399 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
400 // The array does not include an entry for this class.
401 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
405 // Returns an ordered list of class members.
406 // The order of registers is the same as in the .td file.
407 // No = 0 is the default allocation order, No = 1 is the first alternative.
408 ArrayRef<Record*> getOrder(unsigned No = 0) const {
412 // Return the total number of allocation orders available.
413 unsigned getNumOrders() const { return Orders.size(); }
415 // Get the set of registers. This set contains the same registers as
417 const CodeGenRegister::Vec &getMembers() const { return Members; }
419 // Get a bit vector of TopoSigs present in this register class.
420 const BitVector &getTopoSigs() const { return TopoSigs; }
422 // Populate a unique sorted list of units from a register set.
423 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
425 CodeGenRegisterClass(CodeGenRegBank&, Record *R);
427 // A key representing the parts of a register class used for forming
428 // sub-classes. Note the ordering provided by this key is not the same as
429 // the topological order used for the EnumValues.
431 const CodeGenRegister::Vec *Members;
433 unsigned SpillAlignment;
435 Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
436 : Members(M), SpillSize(S), SpillAlignment(A) {}
438 Key(const CodeGenRegisterClass &RC)
439 : Members(&RC.getMembers()),
440 SpillSize(RC.SpillSize),
441 SpillAlignment(RC.SpillAlignment) {}
443 // Lexicographical order of (Members, SpillSize, SpillAlignment).
444 bool operator<(const Key&) const;
447 // Create a non-user defined register class.
448 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
450 // Called by CodeGenRegBank::CodeGenRegBank().
451 static void computeSubClasses(CodeGenRegBank&);
454 // Register units are used to model interference and register pressure.
455 // Every register is assigned one or more register units such that two
456 // registers overlap if and only if they have a register unit in common.
458 // Normally, one register unit is created per leaf register. Non-leaf
459 // registers inherit the units of their sub-registers.
461 // Weight assigned to this RegUnit for estimating register pressure.
462 // This is useful when equalizing weights in register classes with mixed
463 // register topologies.
466 // Each native RegUnit corresponds to one or two root registers. The full
467 // set of registers containing this unit can be computed as the union of
468 // these two registers and their super-registers.
469 const CodeGenRegister *Roots[2];
471 // Index into RegClassUnitSets where we can find the list of UnitSets that
472 // contain this unit.
473 unsigned RegClassUnitSetsIdx;
475 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
476 Roots[0] = Roots[1] = nullptr;
479 ArrayRef<const CodeGenRegister*> getRoots() const {
480 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
481 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
485 // Each RegUnitSet is a sorted vector with a name.
487 typedef std::vector<unsigned>::const_iterator iterator;
490 std::vector<unsigned> Units;
491 unsigned Weight = 0; // Cache the sum of all unit weights.
492 unsigned Order = 0; // Cache the sort key.
494 RegUnitSet() = default;
497 // Base vector for identifying TopoSigs. The contents uniquely identify a
498 // TopoSig, only computeSuperRegs needs to know how.
499 typedef SmallVector<unsigned, 16> TopoSigId;
501 // CodeGenRegBank - Represent a target's registers and the relations between
503 class CodeGenRegBank {
506 std::deque<CodeGenSubRegIndex> SubRegIndices;
507 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
509 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
511 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
512 CodeGenSubRegIndex*> ConcatIdxMap;
513 ConcatIdxMap ConcatIdx;
516 std::deque<CodeGenRegister> Registers;
517 StringMap<CodeGenRegister*> RegistersByName;
518 DenseMap<Record*, CodeGenRegister*> Def2Reg;
519 unsigned NumNativeRegUnits;
521 std::map<TopoSigId, unsigned> TopoSigs;
523 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
524 SmallVector<RegUnit, 8> RegUnits;
527 std::list<CodeGenRegisterClass> RegClasses;
528 DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
529 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
532 // Remember each unique set of register units. Initially, this contains a
533 // unique set for each register class. Simliar sets are coalesced with
534 // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
535 std::vector<RegUnitSet> RegUnitSets;
537 // Map RegisterClass index to the index of the RegUnitSet that contains the
538 // class's units and any inferred RegUnit supersets.
540 // NOTE: This could grow beyond the number of register classes when we map
541 // register units to lists of unit sets. If the list of unit sets does not
542 // already exist for a register class, we create a new entry in this vector.
543 std::vector<std::vector<unsigned>> RegClassUnitSets;
545 // Give each register unit set an order based on sorting criteria.
546 std::vector<unsigned> RegUnitSetOrder;
548 // Add RC to *2RC maps.
549 void addToMaps(CodeGenRegisterClass*);
551 // Create a synthetic sub-class if it is missing.
552 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
553 const CodeGenRegister::Vec *Membs,
556 // Infer missing register classes.
557 void computeInferredRegisterClasses();
558 void inferCommonSubClass(CodeGenRegisterClass *RC);
559 void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
561 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
562 inferMatchingSuperRegClass(RC, RegClasses.begin());
565 void inferMatchingSuperRegClass(
566 CodeGenRegisterClass *RC,
567 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
569 // Iteratively prune unit sets.
570 void pruneUnitSets();
572 // Compute a weight for each register unit created during getSubRegs.
573 void computeRegUnitWeights();
575 // Create a RegUnitSet for each RegClass and infer superclasses.
576 void computeRegUnitSets();
578 // Populate the Composite map from sub-register relationships.
579 void computeComposites();
581 // Compute a lane mask for each sub-register index.
582 void computeSubRegLaneMasks();
584 /// Computes a lane mask for each register unit enumerated by a physical
586 void computeRegUnitLaneMasks();
589 CodeGenRegBank(RecordKeeper&);
591 SetTheory &getSets() { return Sets; }
593 // Sub-register indices. The first NumNamedIndices are defined by the user
594 // in the .td files. The rest are synthesized such that all sub-registers
595 // have a unique name.
596 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
597 return SubRegIndices;
600 // Find a SubRegIndex form its Record def.
601 CodeGenSubRegIndex *getSubRegIdx(Record*);
603 // Find or create a sub-register index representing the A+B composition.
604 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
605 CodeGenSubRegIndex *B);
607 // Find or create a sub-register index representing the concatenation of
608 // non-overlapping sibling indices.
610 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
613 addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
614 CodeGenSubRegIndex *Idx) {
615 ConcatIdx.insert(std::make_pair(Parts, Idx));
618 const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
620 const StringMap<CodeGenRegister*> &getRegistersByName() {
621 return RegistersByName;
624 // Find a register from its Record def.
625 CodeGenRegister *getReg(Record*);
627 // Get a Register's index into the Registers array.
628 unsigned getRegIndex(const CodeGenRegister *Reg) const {
629 return Reg->EnumValue - 1;
632 // Return the number of allocated TopoSigs. The first TopoSig representing
633 // leaf registers is allocated number 0.
634 unsigned getNumTopoSigs() const {
635 return TopoSigs.size();
638 // Find or create a TopoSig for the given TopoSigId.
639 // This function is only for use by CodeGenRegister::computeSuperRegs().
640 // Others should simply use Reg->getTopoSig().
641 unsigned getTopoSig(const TopoSigId &Id) {
642 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
645 // Create a native register unit that is associated with one or two root
647 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
648 RegUnits.resize(RegUnits.size() + 1);
649 RegUnits.back().Roots[0] = R0;
650 RegUnits.back().Roots[1] = R1;
651 return RegUnits.size() - 1;
654 // Create a new non-native register unit that can be adopted by a register
655 // to increase its pressure. Note that NumNativeRegUnits is not increased.
656 unsigned newRegUnit(unsigned Weight) {
657 RegUnits.resize(RegUnits.size() + 1);
658 RegUnits.back().Weight = Weight;
659 return RegUnits.size() - 1;
662 // Native units are the singular unit of a leaf register. Register aliasing
663 // is completely characterized by native units. Adopted units exist to give
664 // register additional weight but don't affect aliasing.
665 bool isNativeUnit(unsigned RUID) {
666 return RUID < NumNativeRegUnits;
669 unsigned getNumNativeRegUnits() const {
670 return NumNativeRegUnits;
673 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
674 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
676 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
678 const std::list<CodeGenRegisterClass> &getRegClasses() const {
682 // Find a register class from its def.
683 CodeGenRegisterClass *getRegClass(Record*);
685 /// getRegisterClassForRegister - Find the register class that contains the
686 /// specified physical register. If the register is not in a register
687 /// class, return null. If the register is in multiple classes, and the
688 /// classes have a superset-subset relationship and the same set of types,
689 /// return the superclass. Otherwise return null.
690 const CodeGenRegisterClass* getRegClassForRegister(Record *R);
692 // Get the sum of unit weights.
693 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
695 for (std::vector<unsigned>::const_iterator
696 I = Units.begin(), E = Units.end(); I != E; ++I)
697 Weight += getRegUnit(*I).Weight;
701 unsigned getRegSetIDAt(unsigned Order) const {
702 return RegUnitSetOrder[Order];
705 const RegUnitSet &getRegSetAt(unsigned Order) const {
706 return RegUnitSets[RegUnitSetOrder[Order]];
709 // Increase a RegUnitWeight.
710 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
711 getRegUnit(RUID).Weight += Inc;
714 // Get the number of register pressure dimensions.
715 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
717 // Get a set of register unit IDs for a given dimension of pressure.
718 const RegUnitSet &getRegPressureSet(unsigned Idx) const {
719 return RegUnitSets[Idx];
722 // The number of pressure set lists may be larget than the number of
723 // register classes if some register units appeared in a list of sets that
724 // did not correspond to an existing register class.
725 unsigned getNumRegClassPressureSetLists() const {
726 return RegClassUnitSets.size();
729 // Get a list of pressure set IDs for a register class. Liveness of a
730 // register in this class impacts each pressure set in this list by the
731 // weight of the register. An exact solution requires all registers in a
732 // class to have the same class, but it is not strictly guaranteed.
733 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
734 return RegClassUnitSets[RCIdx];
737 // Computed derived records such as missing sub-register indices.
738 void computeDerivedInfo();
740 // Compute the set of registers completely covered by the registers in Regs.
741 // The returned BitVector will have a bit set for each register in Regs,
742 // all sub-registers, and all super-registers that are covered by the
743 // registers in Regs.
745 // This is used to compute the mask of call-preserved registers from a list
747 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
749 // Bit mask of lanes that cover their registers. A sub-register index whose
750 // LaneMask is contained in CoveringLanes will be completely covered by
751 // another sub-register with the same or larger lane mask.
752 LaneBitmask CoveringLanes;
754 // Helper function for printing debug information. Handles artificial
755 // (non-native) reg units.
756 void printRegUnitName(unsigned Unit) const;
759 } // end namespace llvm
761 #endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H