1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines structures to encapsulate the machine model as described in
11 // the target description.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
16 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/StringMap.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/TableGen/Record.h"
23 #include "llvm/TableGen/SetTheory.h"
28 class CodeGenSchedModels;
29 class CodeGenInstruction;
30 class CodeGenRegisterClass;
32 using RecVec = std::vector<Record*>;
33 using RecIter = std::vector<Record*>::const_iterator;
35 using IdxVec = std::vector<unsigned>;
36 using IdxIter = std::vector<unsigned>::const_iterator;
38 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
39 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
40 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
43 /// IsVariadic controls whether the variants are expanded into multiple operands
44 /// or a sequence of writes on one operand.
45 struct CodeGenSchedRW {
58 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
59 HasVariants(false), IsVariadic(false), IsSequence(false) {}
60 CodeGenSchedRW(unsigned Idx, Record *Def)
61 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
62 Name = Def->getName();
63 IsRead = Def->isSubClassOf("SchedRead");
64 HasVariants = Def->isSubClassOf("SchedVariant");
66 IsVariadic = Def->getValueAsBit("Variadic");
68 // Read records don't currently have sequences, but it can be easily
69 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
71 IsSequence = Def->isSubClassOf("WriteSequence");
74 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
75 const std::string &Name)
76 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
77 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
78 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
81 bool isValid() const {
82 assert((!HasVariants || TheDef) && "Variant write needs record def");
83 assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
84 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
85 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
86 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
87 return TheDef || !Sequence.empty();
95 /// Represent a transition between SchedClasses induced by SchedVariant.
96 struct CodeGenSchedTransition {
102 /// Scheduling class.
104 /// Each instruction description will be mapped to a scheduling class. There are
105 /// four types of classes:
107 /// 1) An explicitly defined itinerary class with ItinClassDef set.
108 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
110 /// 2) An implied class with a list of SchedWrites and SchedReads that are
111 /// defined in an instruction definition and which are common across all
112 /// subtargets. ProcIndices contains 0 for any processor.
114 /// 3) An implied class with a list of InstRW records that map instructions to
115 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
116 /// instructions to this class. ProcIndices contains all the processors that
117 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
118 /// still be defined for processors with no InstRW entry.
120 /// 4) An inferred class represents a variant of another class that may be
121 /// resolved at runtime. ProcIndices contains the set of processors that may
122 /// require the class. ProcIndices are propagated through SchedClasses as
123 /// variants are expanded. Multiple SchedClasses may be inferred from an
124 /// itinerary class. Each inherits the processor index from the ItinRW record
125 /// that mapped the itinerary class to the variant Writes or Reads.
126 struct CodeGenSchedClass {
129 Record *ItinClassDef;
133 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
136 std::vector<CodeGenSchedTransition> Transitions;
138 // InstRW records associated with this class. These records may refer to an
139 // Instruction no longer mapped to this class by InstrClassMap. These
140 // Instructions should be ignored by this class because they have been split
141 // off to join another inferred class.
144 CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
145 : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
147 bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
148 ArrayRef<unsigned> R) const {
149 return ItinClassDef == IC && makeArrayRef(Writes) == W &&
150 makeArrayRef(Reads) == R;
153 // Is this class generated from a variants if existing classes? Instructions
154 // are never mapped directly to inferred scheduling classes.
155 bool isInferred() const { return !ItinClassDef; }
158 void dump(const CodeGenSchedModels *SchedModels) const;
162 /// Represent the cost of allocating a register of register class RCDef.
164 /// The cost of allocating a register is equivalent to the number of physical
165 /// registers used by the register renamer. Register costs are defined at
166 /// register class granularity.
167 struct CodeGenRegisterCost {
170 bool AllowMoveElimination;
171 CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
172 : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
173 CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
174 CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
177 /// A processor register file.
179 /// This class describes a processor register file. Register file information is
180 /// currently consumed by external tools like llvm-mca to predict dispatch
181 /// stalls due to register pressure.
182 struct CodeGenRegisterFile {
184 Record *RegisterFileDef;
185 unsigned MaxMovesEliminatedPerCycle;
186 bool AllowZeroMoveEliminationOnly;
188 unsigned NumPhysRegs;
189 std::vector<CodeGenRegisterCost> Costs;
191 CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
192 bool AllowZeroMoveElimOnly = false)
193 : Name(name), RegisterFileDef(def),
194 MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
195 AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
198 bool hasDefaultCosts() const { return Costs.empty(); }
203 // ModelName is a unique name used to name an instantiation of MCSchedModel.
205 // ModelDef is NULL for inferred Models. This happens when a processor defines
206 // an itinerary but no machine model. If the processor defines neither a machine
207 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
208 // the special "NoModel" field set to true.
210 // ItinsDef always points to a valid record definition, but may point to the
211 // default NoItineraries. NoItineraries has an empty list of InstrItinData
214 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
215 struct CodeGenProcModel {
217 std::string ModelName;
221 // Derived members...
223 // Array of InstrItinData records indexed by a CodeGenSchedClass index.
224 // This list is empty if the Processor has no value for Itineraries.
225 // Initialized by collectProcItins().
228 // Map itinerary classes to per-operand resources.
229 // This list is empty if no ItinRW refers to this Processor.
232 // List of unsupported feature.
233 // This list is empty if the Processor has no UnsupportedFeatures.
234 RecVec UnsupportedFeaturesDefs;
236 // All read/write resources associated with this processor.
238 RecVec ReadAdvanceDefs;
240 // Per-operand machine model resources associated with this processor.
241 RecVec ProcResourceDefs;
243 // List of Register Files.
244 std::vector<CodeGenRegisterFile> RegisterFiles;
246 // Optional Retire Control Unit definition.
247 Record *RetireControlUnit;
249 // Load/Store queue descriptors.
253 CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
255 Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
256 RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
258 bool hasItineraries() const {
259 return !ItinsDef->getValueAsListOfDefs("IID").empty();
262 bool hasInstrSchedModel() const {
263 return !WriteResDefs.empty() || !ItinRWDefs.empty();
266 bool hasExtraProcessorInfo() const {
267 return RetireControlUnit || LoadQueue || StoreQueue ||
268 !RegisterFiles.empty();
271 unsigned getProcResourceIdx(Record *PRDef) const;
273 bool isUnsupported(const CodeGenInstruction &Inst) const;
280 /// Used to correlate instructions to MCInstPredicates specified by
281 /// InstructionEquivalentClass tablegen definitions.
283 /// Example: a XOR of a register with self, is a known zero-idiom for most
286 /// Each processor can use a (potentially different) InstructionEquivalenceClass
287 /// definition to classify zero-idioms. That means, XORrr is likely to appear
288 /// in more than one equivalence class (where each class definition is
289 /// contributed by a different processor).
291 /// There is no guarantee that the same MCInstPredicate will be used to describe
292 /// equivalence classes that identify XORrr as a zero-idiom.
294 /// To be more specific, the requirements for being a zero-idiom XORrr may be
295 /// different for different processors.
297 /// Class PredicateInfo identifies a subset of processors that specify the same
298 /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction
301 /// Back to the example. Field `ProcModelMask` will have one bit set for every
302 /// processor model that sees XORrr as a zero-idiom, and that specifies the same
303 /// set of constraints.
305 /// By construction, there can be multiple instances of PredicateInfo associated
306 /// with a same instruction opcode. For example, different processors may define
307 /// different constraints on the same opcode.
309 /// Field OperandMask can be used as an extra constraint.
310 /// It may be used to describe conditions that appy only to a subset of the
311 /// operands of a machine instruction, and the operands subset may not be the
312 /// same for all processor models.
313 struct PredicateInfo {
314 llvm::APInt ProcModelMask; // A set of processor model indices.
315 llvm::APInt OperandMask; // An operand mask.
316 const Record *Predicate; // MCInstrPredicate definition.
317 PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred)
318 : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {}
320 bool operator==(const PredicateInfo &Other) const {
321 return ProcModelMask == Other.ProcModelMask &&
322 OperandMask == Other.OperandMask && Predicate == Other.Predicate;
326 /// A collection of PredicateInfo objects.
328 /// There is at least one OpcodeInfo object for every opcode specified by a
329 /// TIPredicate definition.
331 std::vector<PredicateInfo> Predicates;
333 OpcodeInfo(const OpcodeInfo &Other) = delete;
334 OpcodeInfo &operator=(const OpcodeInfo &Other) = delete;
337 OpcodeInfo() = default;
338 OpcodeInfo &operator=(OpcodeInfo &&Other) = default;
339 OpcodeInfo(OpcodeInfo &&Other) = default;
341 ArrayRef<PredicateInfo> getPredicates() const { return Predicates; }
343 void addPredicateForProcModel(const llvm::APInt &CpuMask,
344 const llvm::APInt &OperandMask,
345 const Record *Predicate);
348 /// Used to group together tablegen instruction definitions that are subject
349 /// to a same set of constraints (identified by an instance of OpcodeInfo).
352 std::vector<const Record *> Opcodes;
354 OpcodeGroup(const OpcodeGroup &Other) = delete;
355 OpcodeGroup &operator=(const OpcodeGroup &Other) = delete;
358 OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {}
359 OpcodeGroup(OpcodeGroup &&Other) = default;
361 void addOpcode(const Record *Opcode) {
362 assert(std::find(Opcodes.begin(), Opcodes.end(), Opcode) == Opcodes.end() &&
363 "Opcode already in set!");
364 Opcodes.push_back(Opcode);
367 ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
368 const OpcodeInfo &getOpcodeInfo() const { return Info; }
371 /// An STIPredicateFunction descriptor used by tablegen backends to
372 /// auto-generate the body of a predicate function as a member of tablegen'd
373 /// class XXXGenSubtargetInfo.
374 class STIPredicateFunction {
375 const Record *FunctionDeclaration;
377 std::vector<const Record *> Definitions;
378 std::vector<OpcodeGroup> Groups;
380 STIPredicateFunction(const STIPredicateFunction &Other) = delete;
381 STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete;
384 STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {}
385 STIPredicateFunction(STIPredicateFunction &&Other) = default;
387 bool isCompatibleWith(const STIPredicateFunction &Other) const {
388 return FunctionDeclaration == Other.FunctionDeclaration;
391 void addDefinition(const Record *Def) { Definitions.push_back(Def); }
392 void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) {
393 if (Groups.empty() ||
394 Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates())
395 Groups.emplace_back(std::move(Info));
396 Groups.back().addOpcode(OpcodeRec);
399 StringRef getName() const {
400 return FunctionDeclaration->getValueAsString("Name");
402 const Record *getDefaultReturnPredicate() const {
403 return FunctionDeclaration->getValueAsDef("DefaultReturnValue");
406 const Record *getDeclaration() const { return FunctionDeclaration; }
407 ArrayRef<const Record *> getDefinitions() const { return Definitions; }
408 ArrayRef<OpcodeGroup> getGroups() const { return Groups; }
411 /// Top level container for machine model data.
412 class CodeGenSchedModels {
413 RecordKeeper &Records;
414 const CodeGenTarget &Target;
416 // Map dag expressions to Instruction lists.
419 // List of unique processor models.
420 std::vector<CodeGenProcModel> ProcModels;
422 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
423 using ProcModelMapTy = DenseMap<Record*, unsigned>;
424 ProcModelMapTy ProcModelMap;
426 // Per-operand SchedReadWrite types.
427 std::vector<CodeGenSchedRW> SchedWrites;
428 std::vector<CodeGenSchedRW> SchedReads;
430 // List of unique SchedClasses.
431 std::vector<CodeGenSchedClass> SchedClasses;
433 // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
434 unsigned NumInstrSchedClasses;
436 RecVec ProcResourceDefs;
437 RecVec ProcResGroups;
439 // Map each instruction to its unique SchedClass index considering the
440 // combination of it's itinerary class, SchedRW list, and InstRW records.
441 using InstClassMapTy = DenseMap<Record*, unsigned>;
442 InstClassMapTy InstrClassMap;
444 std::vector<STIPredicateFunction> STIPredicates;
447 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
449 // iterator access to the scheduling classes.
450 using class_iterator = std::vector<CodeGenSchedClass>::iterator;
451 using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
452 class_iterator classes_begin() { return SchedClasses.begin(); }
453 const_class_iterator classes_begin() const { return SchedClasses.begin(); }
454 class_iterator classes_end() { return SchedClasses.end(); }
455 const_class_iterator classes_end() const { return SchedClasses.end(); }
456 iterator_range<class_iterator> classes() {
457 return make_range(classes_begin(), classes_end());
459 iterator_range<const_class_iterator> classes() const {
460 return make_range(classes_begin(), classes_end());
462 iterator_range<class_iterator> explicit_classes() {
463 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
465 iterator_range<const_class_iterator> explicit_classes() const {
466 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
469 Record *getModelOrItinDef(Record *ProcDef) const {
470 Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
471 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
472 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
473 assert(ModelDef->getValueAsBit("NoModel")
474 && "Itineraries must be defined within SchedMachineModel");
480 const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
481 Record *ModelDef = getModelOrItinDef(ProcDef);
482 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
483 assert(I != ProcModelMap.end() && "missing machine model");
484 return ProcModels[I->second];
487 CodeGenProcModel &getProcModel(Record *ModelDef) {
488 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
489 assert(I != ProcModelMap.end() && "missing machine model");
490 return ProcModels[I->second];
492 const CodeGenProcModel &getProcModel(Record *ModelDef) const {
493 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
496 // Iterate over the unique processor models.
497 using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
498 ProcIter procModelBegin() const { return ProcModels.begin(); }
499 ProcIter procModelEnd() const { return ProcModels.end(); }
500 ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
502 // Return true if any processors have itineraries.
503 bool hasItineraries() const;
505 // Get a SchedWrite from its index.
506 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
507 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
508 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
509 return SchedWrites[Idx];
511 // Get a SchedWrite from its index.
512 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
513 assert(Idx < SchedReads.size() && "bad SchedRead index");
514 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
515 return SchedReads[Idx];
518 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
519 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
521 CodeGenSchedRW &getSchedRW(Record *Def) {
522 bool IsRead = Def->isSubClassOf("SchedRead");
523 unsigned Idx = getSchedRWIdx(Def, IsRead);
524 return const_cast<CodeGenSchedRW&>(
525 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
527 const CodeGenSchedRW &getSchedRW(Record *Def) const {
528 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
531 unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
533 // Return true if the given write record is referenced by a ReadAdvance.
534 bool hasReadOfWrite(Record *WriteDef) const;
536 // Get a SchedClass from its index.
537 CodeGenSchedClass &getSchedClass(unsigned Idx) {
538 assert(Idx < SchedClasses.size() && "bad SchedClass index");
539 return SchedClasses[Idx];
541 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
542 assert(Idx < SchedClasses.size() && "bad SchedClass index");
543 return SchedClasses[Idx];
546 // Get the SchedClass index for an instruction. Instructions with no
547 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
549 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
551 using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
552 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
553 SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
554 ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
556 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
558 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
559 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
560 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
561 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
562 const CodeGenProcModel &ProcModel) const;
564 unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
565 ArrayRef<unsigned> OperReads,
566 ArrayRef<unsigned> ProcIndices);
568 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
570 Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM,
571 ArrayRef<SMLoc> Loc) const;
573 ArrayRef<STIPredicateFunction> getSTIPredicates() const {
574 return STIPredicates;
577 void collectProcModels();
579 // Initialize a new processor model if it is unique.
580 void addProcModel(Record *ProcDef);
582 void collectSchedRW();
584 std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
585 unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
587 void collectSchedClasses();
589 void collectRetireControlUnits();
591 void collectRegisterFiles();
593 void collectOptionalProcessorInfo();
595 std::string createSchedClassName(Record *ItinClassDef,
596 ArrayRef<unsigned> OperWrites,
597 ArrayRef<unsigned> OperReads);
598 std::string createSchedClassName(const RecVec &InstDefs);
599 void createInstRWClass(Record *InstRWDef);
601 void collectProcItins();
603 void collectProcItinRW();
605 void collectProcUnsupportedFeatures();
607 void inferSchedClasses();
609 void checkMCInstPredicates() const;
611 void checkSTIPredicates() const;
613 void collectSTIPredicates();
615 void collectLoadStoreQueueInfo();
617 void checkCompleteness();
619 void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
620 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
621 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
622 void inferFromInstRWs(unsigned SCIdx);
624 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
625 void verifyProcResourceGroups(CodeGenProcModel &PM);
627 void collectProcResources();
629 void collectItinProcResources(Record *ItinClassDef);
631 void collectRWResources(unsigned RWIdx, bool IsRead,
632 ArrayRef<unsigned> ProcIndices);
634 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
635 ArrayRef<unsigned> ProcIndices);
637 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM,
638 ArrayRef<SMLoc> Loc);
640 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
642 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);