1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class wraps target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes abort on error conditions.
15 //===----------------------------------------------------------------------===//
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/TableGen/Error.h"
24 #include "llvm/TableGen/Record.h"
28 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
29 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
31 static cl::opt<unsigned>
32 AsmParserNum("asmparsernum", cl::init(0),
33 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
34 cl::cat(AsmParserCat));
36 static cl::opt<unsigned>
37 AsmWriterNum("asmwriternum", cl::init(0),
38 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
39 cl::cat(AsmWriterCat));
41 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
42 /// record corresponds to.
43 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
44 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47 StringRef llvm::getName(MVT::SimpleValueType T) {
49 case MVT::Other: return "UNKNOWN";
50 case MVT::iPTR: return "TLI.getPointerTy()";
51 case MVT::iPTRAny: return "TLI.getPointerTy()";
52 default: return getEnumName(T);
56 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
58 case MVT::Other: return "MVT::Other";
59 case MVT::i1: return "MVT::i1";
60 case MVT::i8: return "MVT::i8";
61 case MVT::i16: return "MVT::i16";
62 case MVT::i32: return "MVT::i32";
63 case MVT::i64: return "MVT::i64";
64 case MVT::i128: return "MVT::i128";
65 case MVT::Any: return "MVT::Any";
66 case MVT::iAny: return "MVT::iAny";
67 case MVT::fAny: return "MVT::fAny";
68 case MVT::vAny: return "MVT::vAny";
69 case MVT::f16: return "MVT::f16";
70 case MVT::f32: return "MVT::f32";
71 case MVT::f64: return "MVT::f64";
72 case MVT::f80: return "MVT::f80";
73 case MVT::f128: return "MVT::f128";
74 case MVT::ppcf128: return "MVT::ppcf128";
75 case MVT::x86mmx: return "MVT::x86mmx";
76 case MVT::Glue: return "MVT::Glue";
77 case MVT::isVoid: return "MVT::isVoid";
78 case MVT::v1i1: return "MVT::v1i1";
79 case MVT::v2i1: return "MVT::v2i1";
80 case MVT::v4i1: return "MVT::v4i1";
81 case MVT::v8i1: return "MVT::v8i1";
82 case MVT::v16i1: return "MVT::v16i1";
83 case MVT::v32i1: return "MVT::v32i1";
84 case MVT::v64i1: return "MVT::v64i1";
85 case MVT::v512i1: return "MVT::v512i1";
86 case MVT::v1024i1: return "MVT::v1024i1";
87 case MVT::v1i8: return "MVT::v1i8";
88 case MVT::v2i8: return "MVT::v2i8";
89 case MVT::v4i8: return "MVT::v4i8";
90 case MVT::v8i8: return "MVT::v8i8";
91 case MVT::v16i8: return "MVT::v16i8";
92 case MVT::v32i8: return "MVT::v32i8";
93 case MVT::v64i8: return "MVT::v64i8";
94 case MVT::v128i8: return "MVT::v128i8";
95 case MVT::v256i8: return "MVT::v256i8";
96 case MVT::v1i16: return "MVT::v1i16";
97 case MVT::v2i16: return "MVT::v2i16";
98 case MVT::v4i16: return "MVT::v4i16";
99 case MVT::v8i16: return "MVT::v8i16";
100 case MVT::v16i16: return "MVT::v16i16";
101 case MVT::v32i16: return "MVT::v32i16";
102 case MVT::v64i16: return "MVT::v64i16";
103 case MVT::v128i16: return "MVT::v128i16";
104 case MVT::v1i32: return "MVT::v1i32";
105 case MVT::v2i32: return "MVT::v2i32";
106 case MVT::v4i32: return "MVT::v4i32";
107 case MVT::v8i32: return "MVT::v8i32";
108 case MVT::v16i32: return "MVT::v16i32";
109 case MVT::v32i32: return "MVT::v32i32";
110 case MVT::v64i32: return "MVT::v64i32";
111 case MVT::v1i64: return "MVT::v1i64";
112 case MVT::v2i64: return "MVT::v2i64";
113 case MVT::v4i64: return "MVT::v4i64";
114 case MVT::v8i64: return "MVT::v8i64";
115 case MVT::v16i64: return "MVT::v16i64";
116 case MVT::v32i64: return "MVT::v32i64";
117 case MVT::v1i128: return "MVT::v1i128";
118 case MVT::v2f16: return "MVT::v2f16";
119 case MVT::v4f16: return "MVT::v4f16";
120 case MVT::v8f16: return "MVT::v8f16";
121 case MVT::v1f32: return "MVT::v1f32";
122 case MVT::v2f32: return "MVT::v2f32";
123 case MVT::v4f32: return "MVT::v4f32";
124 case MVT::v8f32: return "MVT::v8f32";
125 case MVT::v16f32: return "MVT::v16f32";
126 case MVT::v1f64: return "MVT::v1f64";
127 case MVT::v2f64: return "MVT::v2f64";
128 case MVT::v4f64: return "MVT::v4f64";
129 case MVT::v8f64: return "MVT::v8f64";
130 case MVT::nxv1i1: return "MVT::nxv1i1";
131 case MVT::nxv2i1: return "MVT::nxv2i1";
132 case MVT::nxv4i1: return "MVT::nxv4i1";
133 case MVT::nxv8i1: return "MVT::nxv8i1";
134 case MVT::nxv16i1: return "MVT::nxv16i1";
135 case MVT::nxv32i1: return "MVT::nxv32i1";
136 case MVT::nxv1i8: return "MVT::nxv1i8";
137 case MVT::nxv2i8: return "MVT::nxv2i8";
138 case MVT::nxv4i8: return "MVT::nxv4i8";
139 case MVT::nxv8i8: return "MVT::nxv8i8";
140 case MVT::nxv16i8: return "MVT::nxv16i8";
141 case MVT::nxv32i8: return "MVT::nxv32i8";
142 case MVT::nxv1i16: return "MVT::nxv1i16";
143 case MVT::nxv2i16: return "MVT::nxv2i16";
144 case MVT::nxv4i16: return "MVT::nxv4i16";
145 case MVT::nxv8i16: return "MVT::nxv8i16";
146 case MVT::nxv16i16: return "MVT::nxv16i16";
147 case MVT::nxv32i16: return "MVT::nxv32i16";
148 case MVT::nxv1i32: return "MVT::nxv1i32";
149 case MVT::nxv2i32: return "MVT::nxv2i32";
150 case MVT::nxv4i32: return "MVT::nxv4i32";
151 case MVT::nxv8i32: return "MVT::nxv8i32";
152 case MVT::nxv16i32: return "MVT::nxv16i32";
153 case MVT::nxv1i64: return "MVT::nxv1i64";
154 case MVT::nxv2i64: return "MVT::nxv2i64";
155 case MVT::nxv4i64: return "MVT::nxv4i64";
156 case MVT::nxv8i64: return "MVT::nxv8i64";
157 case MVT::nxv16i64: return "MVT::nxv16i64";
158 case MVT::nxv2f16: return "MVT::nxv2f16";
159 case MVT::nxv4f16: return "MVT::nxv4f16";
160 case MVT::nxv8f16: return "MVT::nxv8f16";
161 case MVT::nxv1f32: return "MVT::nxv1f32";
162 case MVT::nxv2f32: return "MVT::nxv2f32";
163 case MVT::nxv4f32: return "MVT::nxv4f32";
164 case MVT::nxv8f32: return "MVT::nxv8f32";
165 case MVT::nxv16f32: return "MVT::nxv16f32";
166 case MVT::nxv1f64: return "MVT::nxv1f64";
167 case MVT::nxv2f64: return "MVT::nxv2f64";
168 case MVT::nxv4f64: return "MVT::nxv4f64";
169 case MVT::nxv8f64: return "MVT::nxv8f64";
170 case MVT::token: return "MVT::token";
171 case MVT::Metadata: return "MVT::Metadata";
172 case MVT::iPTR: return "MVT::iPTR";
173 case MVT::iPTRAny: return "MVT::iPTRAny";
174 case MVT::Untyped: return "MVT::Untyped";
175 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
179 /// getQualifiedName - Return the name of the specified record, with a
180 /// namespace qualifier if the record contains one.
182 std::string llvm::getQualifiedName(const Record *R) {
183 std::string Namespace;
184 if (R->getValue("Namespace"))
185 Namespace = R->getValueAsString("Namespace");
186 if (Namespace.empty()) return R->getName();
187 return Namespace + "::" + R->getName().str();
191 /// getTarget - Return the current instance of the Target class.
193 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
195 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
196 if (Targets.size() == 0)
197 PrintFatalError("ERROR: No 'Target' subclasses defined!");
198 if (Targets.size() != 1)
199 PrintFatalError("ERROR: Multiple subclasses of Target defined!");
200 TargetRec = Targets[0];
203 CodeGenTarget::~CodeGenTarget() {
206 const StringRef CodeGenTarget::getName() const {
207 return TargetRec->getName();
210 std::string CodeGenTarget::getInstNamespace() const {
211 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
212 // Make sure not to pick up "TargetOpcode" by accidentally getting
213 // the namespace off the PHI instruction or something.
214 if (Inst->Namespace != "TargetOpcode")
215 return Inst->Namespace;
221 Record *CodeGenTarget::getInstructionSet() const {
222 return TargetRec->getValueAsDef("InstructionSet");
226 /// getAsmParser - Return the AssemblyParser definition for this target.
228 Record *CodeGenTarget::getAsmParser() const {
229 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
230 if (AsmParserNum >= LI.size())
231 PrintFatalError("Target does not have an AsmParser #" +
232 Twine(AsmParserNum) + "!");
233 return LI[AsmParserNum];
236 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
239 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
240 std::vector<Record*> LI =
241 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
243 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
248 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
249 /// available for this target.
251 unsigned CodeGenTarget::getAsmParserVariantCount() const {
252 std::vector<Record*> LI =
253 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
257 /// getAsmWriter - Return the AssemblyWriter definition for this target.
259 Record *CodeGenTarget::getAsmWriter() const {
260 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
261 if (AsmWriterNum >= LI.size())
262 PrintFatalError("Target does not have an AsmWriter #" +
263 Twine(AsmWriterNum) + "!");
264 return LI[AsmWriterNum];
267 CodeGenRegBank &CodeGenTarget::getRegBank() const {
269 RegBank = llvm::make_unique<CodeGenRegBank>(Records);
273 void CodeGenTarget::ReadRegAltNameIndices() const {
274 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
275 std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
278 /// getRegisterByName - If there is a register with the specific AsmName,
280 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
281 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
282 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
288 std::vector<MVT::SimpleValueType> CodeGenTarget::
289 getRegisterVTs(Record *R) const {
290 const CodeGenRegister *Reg = getRegBank().getReg(R);
291 std::vector<MVT::SimpleValueType> Result;
292 for (const auto &RC : getRegBank().getRegClasses()) {
293 if (RC.contains(Reg)) {
294 ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes();
295 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
299 // Remove duplicates.
300 array_pod_sort(Result.begin(), Result.end());
301 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
306 void CodeGenTarget::ReadLegalValueTypes() const {
307 for (const auto &RC : getRegBank().getRegClasses())
308 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
310 // Remove duplicates.
311 array_pod_sort(LegalValueTypes.begin(), LegalValueTypes.end());
312 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
313 LegalValueTypes.end()),
314 LegalValueTypes.end());
317 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
319 SchedModels = llvm::make_unique<CodeGenSchedModels>(Records, *this);
323 void CodeGenTarget::ReadInstructions() const {
324 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
325 if (Insts.size() <= 2)
326 PrintFatalError("No 'Instruction' subclasses defined!");
328 // Parse the instructions defined in the .td file.
329 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
330 Instructions[Insts[i]] = llvm::make_unique<CodeGenInstruction>(Insts[i]);
333 static const CodeGenInstruction *
334 GetInstByName(const char *Name,
335 const DenseMap<const Record*,
336 std::unique_ptr<CodeGenInstruction>> &Insts,
337 RecordKeeper &Records) {
338 const Record *Rec = Records.getDef(Name);
340 const auto I = Insts.find(Rec);
341 if (!Rec || I == Insts.end())
342 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
343 return I->second.get();
346 /// \brief Return all of the instructions defined by the target, ordered by
347 /// their enum value.
348 void CodeGenTarget::ComputeInstrsByEnum() const {
349 static const char *const FixedInstrs[] = {
350 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
351 #include "llvm/Target/TargetOpcodes.def"
353 const auto &Insts = getInstructions();
354 for (const char *const *p = FixedInstrs; *p; ++p) {
355 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
356 assert(Instr && "Missing target independent instruction");
357 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
358 InstrsByEnum.push_back(Instr);
360 unsigned EndOfPredefines = InstrsByEnum.size();
362 for (const auto &I : Insts) {
363 const CodeGenInstruction *CGI = I.second.get();
364 if (CGI->Namespace != "TargetOpcode")
365 InstrsByEnum.push_back(CGI);
368 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
370 // All of the instructions are now in random order based on the map iteration.
371 // Sort them by name.
372 std::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
373 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
374 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
379 /// isLittleEndianEncoding - Return whether this target encodes its instruction
380 /// in little-endian format, i.e. bits laid out in the order [0..n]
382 bool CodeGenTarget::isLittleEndianEncoding() const {
383 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
386 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
387 /// encodings, reverse the bit order of all instructions.
388 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
389 if (!isLittleEndianEncoding())
392 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
393 for (Record *R : Insts) {
394 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
395 R->getValueAsBit("isPseudo"))
398 BitsInit *BI = R->getValueAsBitsInit("Inst");
400 unsigned numBits = BI->getNumBits();
402 SmallVector<Init *, 16> NewBits(numBits);
404 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
405 unsigned bitSwapIdx = numBits - bit - 1;
406 Init *OrigBit = BI->getBit(bit);
407 Init *BitSwap = BI->getBit(bitSwapIdx);
408 NewBits[bit] = BitSwap;
409 NewBits[bitSwapIdx] = OrigBit;
412 unsigned middle = (numBits + 1) / 2;
413 NewBits[middle] = BI->getBit(middle);
416 BitsInit *NewBI = BitsInit::get(NewBits);
418 // Update the bits in reversed order so that emitInstrOpBits will get the
419 // correct endianness.
420 R->getValue("Inst")->setValue(NewBI);
424 /// guessInstructionProperties - Return true if it's OK to guess instruction
425 /// properties instead of raising an error.
427 /// This is configurable as a temporary migration aid. It will eventually be
428 /// permanently false.
429 bool CodeGenTarget::guessInstructionProperties() const {
430 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
433 //===----------------------------------------------------------------------===//
434 // ComplexPattern implementation
436 ComplexPattern::ComplexPattern(Record *R) {
437 Ty = ::getValueType(R->getValueAsDef("Ty"));
438 NumOperands = R->getValueAsInt("NumOperands");
439 SelectFunc = R->getValueAsString("SelectFunc");
440 RootNodes = R->getValueAsListOfDefs("RootNodes");
442 // FIXME: This is a hack to statically increase the priority of patterns which
443 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
444 // possible pattern match we'll need to dynamically calculate the complexity
445 // of all patterns a dag can potentially map to.
446 int64_t RawComplexity = R->getValueAsInt("Complexity");
447 if (RawComplexity == -1)
448 Complexity = NumOperands * 3;
450 Complexity = RawComplexity;
452 // Parse the properties.
454 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
455 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
456 if (PropList[i]->getName() == "SDNPHasChain") {
457 Properties |= 1 << SDNPHasChain;
458 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
459 Properties |= 1 << SDNPOptInGlue;
460 } else if (PropList[i]->getName() == "SDNPMayStore") {
461 Properties |= 1 << SDNPMayStore;
462 } else if (PropList[i]->getName() == "SDNPMayLoad") {
463 Properties |= 1 << SDNPMayLoad;
464 } else if (PropList[i]->getName() == "SDNPSideEffect") {
465 Properties |= 1 << SDNPSideEffect;
466 } else if (PropList[i]->getName() == "SDNPMemOperand") {
467 Properties |= 1 << SDNPMemOperand;
468 } else if (PropList[i]->getName() == "SDNPVariadic") {
469 Properties |= 1 << SDNPVariadic;
470 } else if (PropList[i]->getName() == "SDNPWantRoot") {
471 Properties |= 1 << SDNPWantRoot;
472 } else if (PropList[i]->getName() == "SDNPWantParent") {
473 Properties |= 1 << SDNPWantParent;
475 PrintFatalError("Unsupported SD Node property '" +
476 PropList[i]->getName() + "' on ComplexPattern '" +
477 R->getName() + "'!");
481 //===----------------------------------------------------------------------===//
482 // CodeGenIntrinsic Implementation
483 //===----------------------------------------------------------------------===//
485 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
487 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
489 Intrinsics.reserve(Defs.size());
491 for (unsigned I = 0, e = Defs.size(); I != e; ++I) {
492 bool isTarget = Defs[I]->getValueAsBit("isTarget");
493 if (isTarget == TargetOnly)
494 Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
496 std::sort(Intrinsics.begin(), Intrinsics.end(),
497 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
498 return std::tie(LHS.TargetPrefix, LHS.Name) <
499 std::tie(RHS.TargetPrefix, RHS.Name);
501 Targets.push_back({"", 0, 0});
502 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
503 if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
504 Targets.back().Count = I - Targets.back().Offset;
505 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
507 Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
510 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
512 std::string DefName = R->getName();
513 ModRef = ReadWriteMem;
514 isOverloaded = false;
515 isCommutative = false;
518 isNoDuplicate = false;
519 isConvergent = false;
520 isSpeculatable = false;
521 hasSideEffects = false;
523 if (DefName.size() <= 4 ||
524 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
525 PrintFatalError("Intrinsic '" + DefName + "' does not start with 'int_'!");
527 EnumName = std::string(DefName.begin()+4, DefName.end());
529 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
530 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
531 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
532 MSBuiltinName = R->getValueAsString("MSBuiltinName");
534 TargetPrefix = R->getValueAsString("TargetPrefix");
535 Name = R->getValueAsString("LLVMName");
538 // If an explicit name isn't specified, derive one from the DefName.
541 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
542 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
544 // Verify it starts with "llvm.".
545 if (Name.size() <= 5 ||
546 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
547 PrintFatalError("Intrinsic '" + DefName + "'s name does not start with 'llvm.'!");
550 // If TargetPrefix is specified, make sure that Name starts with
551 // "llvm.<targetprefix>.".
552 if (!TargetPrefix.empty()) {
553 if (Name.size() < 6+TargetPrefix.size() ||
554 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
555 != (TargetPrefix + "."))
556 PrintFatalError("Intrinsic '" + DefName + "' does not start with 'llvm." +
557 TargetPrefix + ".'!");
560 // Parse the list of return types.
561 std::vector<MVT::SimpleValueType> OverloadedVTs;
562 ListInit *TypeList = R->getValueAsListInit("RetTypes");
563 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
564 Record *TyEl = TypeList->getElementAsRecord(i);
565 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
566 MVT::SimpleValueType VT;
567 if (TyEl->isSubClassOf("LLVMMatchType")) {
568 unsigned MatchTy = TyEl->getValueAsInt("Number");
569 assert(MatchTy < OverloadedVTs.size() &&
570 "Invalid matching number!");
571 VT = OverloadedVTs[MatchTy];
572 // It only makes sense to use the extended and truncated vector element
573 // variants with iAny types; otherwise, if the intrinsic is not
574 // overloaded, all the types can be specified directly.
575 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
576 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
577 VT == MVT::iAny || VT == MVT::vAny) &&
578 "Expected iAny or vAny type");
580 VT = getValueType(TyEl->getValueAsDef("VT"));
582 if (MVT(VT).isOverloaded()) {
583 OverloadedVTs.push_back(VT);
587 // Reject invalid types.
588 if (VT == MVT::isVoid)
589 PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
591 IS.RetVTs.push_back(VT);
592 IS.RetTypeDefs.push_back(TyEl);
595 // Parse the list of parameter types.
596 TypeList = R->getValueAsListInit("ParamTypes");
597 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
598 Record *TyEl = TypeList->getElementAsRecord(i);
599 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
600 MVT::SimpleValueType VT;
601 if (TyEl->isSubClassOf("LLVMMatchType")) {
602 unsigned MatchTy = TyEl->getValueAsInt("Number");
603 assert(MatchTy < OverloadedVTs.size() &&
604 "Invalid matching number!");
605 VT = OverloadedVTs[MatchTy];
606 // It only makes sense to use the extended and truncated vector element
607 // variants with iAny types; otherwise, if the intrinsic is not
608 // overloaded, all the types can be specified directly.
609 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
610 !TyEl->isSubClassOf("LLVMTruncatedType") &&
611 !TyEl->isSubClassOf("LLVMVectorSameWidth")) ||
612 VT == MVT::iAny || VT == MVT::vAny) &&
613 "Expected iAny or vAny type");
615 VT = getValueType(TyEl->getValueAsDef("VT"));
617 if (MVT(VT).isOverloaded()) {
618 OverloadedVTs.push_back(VT);
622 // Reject invalid types.
623 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
624 PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
626 IS.ParamVTs.push_back(VT);
627 IS.ParamTypeDefs.push_back(TyEl);
630 // Parse the intrinsic properties.
631 ListInit *PropList = R->getValueAsListInit("IntrProperties");
632 for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
633 Record *Property = PropList->getElementAsRecord(i);
634 assert(Property->isSubClassOf("IntrinsicProperty") &&
635 "Expected a property!");
637 if (Property->getName() == "IntrNoMem")
639 else if (Property->getName() == "IntrReadMem")
640 ModRef = ModRefBehavior(ModRef & ~MR_Mod);
641 else if (Property->getName() == "IntrWriteMem")
642 ModRef = ModRefBehavior(ModRef & ~MR_Ref);
643 else if (Property->getName() == "IntrArgMemOnly")
644 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
645 else if (Property->getName() == "IntrInaccessibleMemOnly")
646 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
647 else if (Property->getName() == "IntrInaccessibleMemOrArgMemOnly")
648 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
650 else if (Property->getName() == "Commutative")
651 isCommutative = true;
652 else if (Property->getName() == "Throws")
654 else if (Property->getName() == "IntrNoDuplicate")
655 isNoDuplicate = true;
656 else if (Property->getName() == "IntrConvergent")
658 else if (Property->getName() == "IntrNoReturn")
660 else if (Property->getName() == "IntrSpeculatable")
661 isSpeculatable = true;
662 else if (Property->getName() == "IntrHasSideEffects")
663 hasSideEffects = true;
664 else if (Property->isSubClassOf("NoCapture")) {
665 unsigned ArgNo = Property->getValueAsInt("ArgNo");
666 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
667 } else if (Property->isSubClassOf("Returned")) {
668 unsigned ArgNo = Property->getValueAsInt("ArgNo");
669 ArgumentAttributes.push_back(std::make_pair(ArgNo, Returned));
670 } else if (Property->isSubClassOf("ReadOnly")) {
671 unsigned ArgNo = Property->getValueAsInt("ArgNo");
672 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
673 } else if (Property->isSubClassOf("WriteOnly")) {
674 unsigned ArgNo = Property->getValueAsInt("ArgNo");
675 ArgumentAttributes.push_back(std::make_pair(ArgNo, WriteOnly));
676 } else if (Property->isSubClassOf("ReadNone")) {
677 unsigned ArgNo = Property->getValueAsInt("ArgNo");
678 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
680 llvm_unreachable("Unknown property!");
683 // Sort the argument attributes for later benefit.
684 std::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());