1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines wrappers for the Target class and related global
11 // functionality. This makes it easier to access the data and provides a single
12 // place that needs to check it for validity. All of these classes abort
13 // on error conditions.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
18 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
20 #include "CodeGenHwModes.h"
21 #include "CodeGenInstruction.h"
22 #include "CodeGenRegisters.h"
23 #include "InfoByHwMode.h"
24 #include "SDNodeProperties.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/TableGen/Record.h"
31 struct CodeGenRegister;
32 class CodeGenSchedModels;
35 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
36 /// record corresponds to.
37 MVT::SimpleValueType getValueType(Record *Rec);
39 StringRef getName(MVT::SimpleValueType T);
40 StringRef getEnumName(MVT::SimpleValueType T);
42 /// getQualifiedName - Return the name of the specified record, with a
43 /// namespace qualifier if the record contains one.
44 std::string getQualifiedName(const Record *R);
46 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
49 RecordKeeper &Records;
52 mutable DenseMap<const Record*,
53 std::unique_ptr<CodeGenInstruction>> Instructions;
54 mutable std::unique_ptr<CodeGenRegBank> RegBank;
55 mutable std::vector<Record*> RegAltNameIndices;
56 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
58 void ReadRegAltNameIndices() const;
59 void ReadInstructions() const;
60 void ReadLegalValueTypes() const;
62 mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
64 mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
66 CodeGenTarget(RecordKeeper &Records);
69 Record *getTargetRecord() const { return TargetRec; }
70 const StringRef getName() const;
72 /// getInstNamespace - Return the target-specific instruction namespace.
74 StringRef getInstNamespace() const;
76 /// getInstructionSet - Return the InstructionSet object.
78 Record *getInstructionSet() const;
80 /// getAsmParser - Return the AssemblyParser definition for this target.
82 Record *getAsmParser() const;
84 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
87 Record *getAsmParserVariant(unsigned i) const;
89 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
90 /// available for this target.
92 unsigned getAsmParserVariantCount() const;
94 /// getAsmWriter - Return the AssemblyWriter definition for this target.
96 Record *getAsmWriter() const;
98 /// getRegBank - Return the register bank description.
99 CodeGenRegBank &getRegBank() const;
101 /// getRegisterByName - If there is a register with the specific AsmName,
103 const CodeGenRegister *getRegisterByName(StringRef Name) const;
105 const std::vector<Record*> &getRegAltNameIndices() const {
106 if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
107 return RegAltNameIndices;
110 const CodeGenRegisterClass &getRegisterClass(Record *R) const {
111 return *getRegBank().getRegClass(R);
114 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
115 /// specified physical register.
116 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
118 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
119 if (LegalValueTypes.empty())
120 ReadLegalValueTypes();
121 return LegalValueTypes;
124 CodeGenSchedModels &getSchedModels() const;
126 const CodeGenHwModes &getHwModes() const { return CGH; }
129 DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
130 getInstructions() const {
131 if (Instructions.empty()) ReadInstructions();
136 CodeGenInstruction &getInstruction(const Record *InstRec) const {
137 if (Instructions.empty()) ReadInstructions();
138 auto I = Instructions.find(InstRec);
139 assert(I != Instructions.end() && "Not an instruction");
143 /// getInstructionsByEnumValue - Return all of the instructions defined by the
144 /// target, ordered by their enum value.
145 ArrayRef<const CodeGenInstruction *>
146 getInstructionsByEnumValue() const {
147 if (InstrsByEnum.empty()) ComputeInstrsByEnum();
151 typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
152 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
153 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
156 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
158 bool isLittleEndianEncoding() const;
160 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
161 /// encodings, reverse the bit order of all instructions.
162 void reverseBitsForLittleEndianEncoding();
164 /// guessInstructionProperties - should we just guess unset instruction
166 bool guessInstructionProperties() const;
169 void ComputeInstrsByEnum() const;
172 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
173 /// tablegen class in TargetSelectionDAG.td
174 class ComplexPattern {
175 MVT::SimpleValueType Ty;
176 unsigned NumOperands;
177 std::string SelectFunc;
178 std::vector<Record*> RootNodes;
179 unsigned Properties; // Node properties
182 ComplexPattern(Record *R);
184 MVT::SimpleValueType getValueType() const { return Ty; }
185 unsigned getNumOperands() const { return NumOperands; }
186 const std::string &getSelectFunc() const { return SelectFunc; }
187 const std::vector<Record*> &getRootNodes() const {
190 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
191 unsigned getComplexity() const { return Complexity; }
194 } // End llvm namespace