1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "dfa-emitter"
20 #include "CodeGenTarget.h"
21 #include "llvm/ADT/DenseSet.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/TableGen/TableGenBackend.h"
26 #include "llvm/Support/Debug.h"
33 // --------------------------------------------------------------------
34 // Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
36 // DFA_MAX_RESTERMS * DFA_MAX_RESOURCES must fit within sizeof DFAInput.
37 // This is verified in DFAPacketizer.cpp:DFAPacketizer::DFAPacketizer.
39 // e.g. terms x resource bit combinations that fit in uint32_t:
40 // 4 terms x 8 bits = 32 bits
41 // 3 terms x 10 bits = 30 bits
42 // 2 terms x 16 bits = 32 bits
44 // e.g. terms x resource bit combinations that fit in uint64_t:
45 // 8 terms x 8 bits = 64 bits
46 // 7 terms x 9 bits = 63 bits
47 // 6 terms x 10 bits = 60 bits
48 // 5 terms x 12 bits = 60 bits
49 // 4 terms x 16 bits = 64 bits <--- current
50 // 3 terms x 21 bits = 63 bits
51 // 2 terms x 32 bits = 64 bits
53 #define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
54 #define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
56 typedef uint64_t DFAInput;
57 typedef int64_t DFAStateInput;
58 #define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
61 DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
62 return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
65 /// Return the DFAInput for an instruction class input vector.
66 /// This function is used in both DFAPacketizer.cpp and in
67 /// DFAPacketizerEmitter.cpp.
68 DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
69 DFAInput InsnInput = 0;
70 assert ((InsnClass.size() <= DFA_MAX_RESTERMS) &&
71 "Exceeded maximum number of DFA terms");
72 for (auto U : InsnClass)
73 InsnInput = addDFAFuncUnits(InsnInput, U);
76 } // end anonymous namespace
78 // --------------------------------------------------------------------
81 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
83 // dbgsInsnClass - When debugging, print instruction class stages.
85 void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
87 // dbgsStateInfo - When debugging, print the set of state info.
89 void dbgsStateInfo(const std::set<unsigned> &stateInfo);
91 // dbgsIndent - When debugging, indent by the specified amount.
93 void dbgsIndent(unsigned indent);
97 // class DFAPacketizerEmitter: class that generates and prints out the DFA
98 // for resource tracking.
101 class DFAPacketizerEmitter {
103 std::string TargetName;
105 // allInsnClasses is the set of all possible resources consumed by an
108 std::vector<std::vector<unsigned>> allInsnClasses;
109 RecordKeeper &Records;
112 DFAPacketizerEmitter(RecordKeeper &R);
115 // collectAllFuncUnits - Construct a map of function unit names to bits.
117 int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
118 std::map<std::string, unsigned> &FUNameToBitsMap,
123 // collectAllComboFuncs - Construct a map from a combo function unit bit to
124 // the bits of all included functional units.
126 int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
127 std::map<std::string, unsigned> &FUNameToBitsMap,
128 std::map<unsigned, unsigned> &ComboBitToBitsMap,
132 // collectOneInsnClass - Populate allInsnClasses with one instruction class.
134 int collectOneInsnClass(const std::string &ProcName,
135 std::vector<Record*> &ProcItinList,
136 std::map<std::string, unsigned> &FUNameToBitsMap,
141 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
142 // used in each stage.
144 int collectAllInsnClasses(const std::string &ProcName,
145 std::vector<Record*> &ProcItinList,
146 std::map<std::string, unsigned> &FUNameToBitsMap,
147 std::vector<Record*> &ItinDataList,
151 void run(raw_ostream &OS);
153 } // end anonymous namespace
157 // State represents the usage of machine resources if the packet contains
158 // a set of instruction classes.
160 // Specifically, currentState is a set of bit-masks.
161 // The nth bit in a bit-mask indicates whether the nth resource is being used
162 // by this state. The set of bit-masks in a state represent the different
163 // possible outcomes of transitioning to this state.
164 // For example: consider a two resource architecture: resource L and resource M
165 // with three instruction classes: L, M, and L_or_M.
166 // From the initial state (currentState = 0x00), if we add instruction class
167 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
168 // represents the possible resource states that can result from adding a L_or_M
171 // Another way of thinking about this transition is we are mapping a NDFA with
172 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
174 // A State instance also contains a collection of transitions from that state:
175 // a map from inputs to new states.
180 static int currentStateNum;
181 // stateNum is the only member used for equality/ordering, all other members
182 // can be mutated even in const State objects.
184 mutable bool isInitial;
185 mutable std::set<unsigned> stateInfo;
186 typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
187 mutable TransitionMap Transitions;
191 bool operator<(const State &s) const {
192 return stateNum < s.stateNum;
196 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
197 // may be a valid transition from this state i.e., can an instruction of type
198 // InsnClass be added to the packet represented by this state.
200 // Note that for multiple stages, this quick check does not take into account
201 // any possible resource competition between the stages themselves. That is
202 // enforced in AddInsnClassStages which checks the cross product of all
203 // stages for resource availability (which is a more involved check).
205 bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
206 std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
208 // AddInsnClass - Return all combinations of resource reservation
209 // which are possible from this state (PossibleStates).
211 // PossibleStates is the set of valid resource states that ensue from valid
214 void AddInsnClass(std::vector<unsigned> &InsnClass,
215 std::map<unsigned, unsigned> &ComboBitToBitsMap,
216 std::set<unsigned> &PossibleStates) const;
218 // AddInsnClassStages - Return all combinations of resource reservation
219 // resulting from the cross product of all stages for this InsnClass
220 // which are possible from this state (PossibleStates).
222 void AddInsnClassStages(std::vector<unsigned> &InsnClass,
223 std::map<unsigned, unsigned> &ComboBitToBitsMap,
224 unsigned chkstage, unsigned numstages,
225 unsigned prevState, unsigned origState,
226 DenseSet<unsigned> &VisitedResourceStates,
227 std::set<unsigned> &PossibleStates) const;
229 // addTransition - Add a transition from this state given the input InsnClass
231 void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
233 // hasTransition - Returns true if there is a transition from this state
234 // given the input InsnClass
236 bool hasTransition(std::vector<unsigned> InsnClass) const;
238 } // end anonymous namespace
241 // class DFA: deterministic finite automaton for processor resource tracking.
248 // Set of states. Need to keep this sorted to emit the transition table.
249 typedef std::set<State> StateSet;
257 const State &newState();
260 // writeTable: Print out a table representing the DFA.
262 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
263 int numInsnClasses = 0,
264 int maxResources = 0, int numCombos = 0, int maxStages = 0);
266 } // end anonymous namespace
269 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
271 // dbgsInsnClass - When debugging, print instruction class stages.
273 void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
274 DEBUG(dbgs() << "InsnClass: ");
275 for (unsigned i = 0; i < InsnClass.size(); ++i) {
277 DEBUG(dbgs() << ", ");
279 DEBUG(dbgs() << "0x" << utohexstr(InsnClass[i]));
281 DFAInput InsnInput = getDFAInsnInput(InsnClass);
282 DEBUG(dbgs() << " (input: 0x" << utohexstr(InsnInput) << ")");
286 // dbgsStateInfo - When debugging, print the set of state info.
288 void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
289 DEBUG(dbgs() << "StateInfo: ");
291 for (std::set<unsigned>::iterator SI = stateInfo.begin();
292 SI != stateInfo.end(); ++SI, ++i) {
293 unsigned thisState = *SI;
295 DEBUG(dbgs() << ", ");
297 DEBUG(dbgs() << "0x" << utohexstr(thisState));
302 // dbgsIndent - When debugging, indent by the specified amount.
304 void dbgsIndent(unsigned indent) {
305 for (unsigned i = 0; i < indent; ++i) {
306 DEBUG(dbgs() << " ");
312 // Constructors and destructors for State and DFA
315 stateNum(currentStateNum++), isInitial(false) {}
317 DFA::DFA(): currentState(nullptr) {}
320 // addTransition - Add a transition from this state given the input InsnClass
322 void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
324 assert(!Transitions.count(InsnClass) &&
325 "Cannot have multiple transitions for the same input");
326 Transitions[InsnClass] = To;
330 // hasTransition - Returns true if there is a transition from this state
331 // given the input InsnClass
333 bool State::hasTransition(std::vector<unsigned> InsnClass) const {
334 return Transitions.count(InsnClass) > 0;
338 // AddInsnClass - Return all combinations of resource reservation
339 // which are possible from this state (PossibleStates).
341 // PossibleStates is the set of valid resource states that ensue from valid
344 void State::AddInsnClass(std::vector<unsigned> &InsnClass,
345 std::map<unsigned, unsigned> &ComboBitToBitsMap,
346 std::set<unsigned> &PossibleStates) const {
348 // Iterate over all resource states in currentState.
350 unsigned numstages = InsnClass.size();
351 assert((numstages > 0) && "InsnClass has no stages");
353 for (std::set<unsigned>::iterator SI = stateInfo.begin();
354 SI != stateInfo.end(); ++SI) {
355 unsigned thisState = *SI;
357 DenseSet<unsigned> VisitedResourceStates;
359 DEBUG(dbgs() << " thisState: 0x" << utohexstr(thisState) << "\n");
360 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
361 numstages - 1, numstages,
362 thisState, thisState,
363 VisitedResourceStates, PossibleStates);
367 void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
368 std::map<unsigned, unsigned> &ComboBitToBitsMap,
369 unsigned chkstage, unsigned numstages,
370 unsigned prevState, unsigned origState,
371 DenseSet<unsigned> &VisitedResourceStates,
372 std::set<unsigned> &PossibleStates) const {
374 assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
375 unsigned thisStage = InsnClass[chkstage];
378 dbgsIndent((1 + numstages - chkstage) << 1);
379 dbgs() << "AddInsnClassStages " << chkstage << " (0x"
380 << utohexstr(thisStage) << ") from ";
381 dbgsInsnClass(InsnClass);
386 // Iterate over all possible resources used in thisStage.
387 // For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
389 for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
390 unsigned resourceMask = (0x1 << j);
391 if (resourceMask & thisStage) {
392 unsigned combo = ComboBitToBitsMap[resourceMask];
393 if (combo && ((~prevState & combo) != combo)) {
394 DEBUG(dbgs() << "\tSkipped Add 0x" << utohexstr(prevState)
395 << " - combo op 0x" << utohexstr(resourceMask)
396 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
400 // For each possible resource used in thisStage, generate the
401 // resource state if that resource was used.
403 unsigned ResultingResourceState = prevState | resourceMask | combo;
405 dbgsIndent((2 + numstages - chkstage) << 1);
406 dbgs() << "0x" << utohexstr(prevState)
407 << " | 0x" << utohexstr(resourceMask);
409 dbgs() << " | 0x" << utohexstr(combo);
410 dbgs() << " = 0x" << utohexstr(ResultingResourceState) << " ";
414 // If this is the final stage for this class
418 // Check if the resulting resource state can be accommodated in this
420 // We compute resource OR prevState (originally started as origState).
421 // If the result of the OR is different than origState, it implies
422 // that there is at least one resource that can be used to schedule
423 // thisStage in the current packet.
424 // Insert ResultingResourceState into PossibleStates only if we haven't
425 // processed ResultingResourceState before.
427 if (ResultingResourceState != prevState) {
428 if (VisitedResourceStates.count(ResultingResourceState) == 0) {
429 VisitedResourceStates.insert(ResultingResourceState);
430 PossibleStates.insert(ResultingResourceState);
431 DEBUG(dbgs() << "\tResultingResourceState: 0x"
432 << utohexstr(ResultingResourceState) << "\n");
434 DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
437 DEBUG(dbgs() << "\tSkipped Add - no final resources available\n");
441 // If the current resource can be accommodated, check the next
442 // stage in InsnClass for available resources.
444 if (ResultingResourceState != prevState) {
445 DEBUG(dbgs() << "\n");
446 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
447 chkstage - 1, numstages,
448 ResultingResourceState, origState,
449 VisitedResourceStates, PossibleStates);
451 DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
459 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
460 // may be a valid transition from this state i.e., can an instruction of type
461 // InsnClass be added to the packet represented by this state.
463 // Note that this routine is performing conservative checks that can be
464 // quickly executed acting as a filter before calling AddInsnClassStages.
465 // Any cases allowed through here will be caught later in AddInsnClassStages
466 // which performs the more expensive exact check.
468 bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
469 std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
470 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
471 SI != stateInfo.end(); ++SI) {
473 // Check to see if all required resources are available.
474 bool available = true;
476 // Inspect each stage independently.
477 // note: This is a conservative check as we aren't checking for
478 // possible resource competition between the stages themselves
479 // The full cross product is examined later in AddInsnClass.
480 for (unsigned i = 0; i < InsnClass.size(); ++i) {
481 unsigned resources = *SI;
482 if ((~resources & InsnClass[i]) == 0) {
486 // Make sure _all_ resources for a combo function are available.
487 // note: This is a quick conservative check as it won't catch an
488 // unscheduleable combo if this stage is an OR expression
489 // containing a combo.
490 // These cases are caught later in AddInsnClass.
491 unsigned combo = ComboBitToBitsMap[InsnClass[i]];
492 if (combo && ((~resources & combo) != combo)) {
493 DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x" << utohexstr(resources)
494 << " - combo op 0x" << utohexstr(InsnClass[i])
495 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
508 const State &DFA::newState() {
509 auto IterPair = states.insert(State());
510 assert(IterPair.second && "State already exists");
511 return *IterPair.first;
514 int State::currentStateNum = 0;
516 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
517 TargetName(CodeGenTarget(R).getName()),
518 allInsnClasses(), Records(R) {}
521 // writeTableAndAPI - Print out a table representing the DFA and the
522 // associated API to create a DFA packetizer.
525 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
527 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
531 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
533 int maxResources, int numCombos, int maxStages) {
535 unsigned numStates = states.size();
537 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
538 DEBUG(dbgs() << "writeTableAndAPI\n");
539 DEBUG(dbgs() << "Total states: " << numStates << "\n");
541 OS << "namespace llvm {\n";
543 OS << "\n// Input format:\n";
544 OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
545 << "\t// maximum AND'ed resource terms\n";
546 OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
547 << "\t// maximum resource bits in one term\n";
549 OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
550 << "pairs of <Input, NextState> for all valid\n";
551 OS << "// transitions.\n";
552 OS << "// " << numStates << "\tstates\n";
553 OS << "// " << numInsnClasses << "\tinstruction classes\n";
554 OS << "// " << maxResources << "\tresources max\n";
555 OS << "// " << numCombos << "\tcombo resources\n";
556 OS << "// " << maxStages << "\tstages max\n";
557 OS << "const " << DFA_TBLTYPE << " "
558 << TargetName << "DFAStateInputTable[][2] = {\n";
560 // This table provides a map to the beginning of the transitions for State s
561 // in DFAStateInputTable.
562 std::vector<int> StateEntry(numStates+1);
563 static const std::string SentinelEntry = "{-1, -1}";
565 // Tracks the total valid transitions encountered so far. It is used
566 // to construct the StateEntry table.
567 int ValidTransitions = 0;
568 DFA::StateSet::iterator SI = states.begin();
569 for (unsigned i = 0; i < numStates; ++i, ++SI) {
570 assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
571 StateEntry[i] = ValidTransitions;
572 for (State::TransitionMap::iterator
573 II = SI->Transitions.begin(), IE = SI->Transitions.end();
575 OS << "{0x" << utohexstr(getDFAInsnInput(II->first)) << ", "
576 << II->second->stateNum
579 ValidTransitions += SI->Transitions.size();
581 // If there are no valid transitions from this stage, we need a sentinel
583 if (ValidTransitions == StateEntry[i]) {
584 OS << SentinelEntry << ",\t";
588 OS << " // state " << i << ": " << StateEntry[i];
589 if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
590 OS << "-" << (ValidTransitions-1);
595 // Print out a sentinel entry at the end of the StateInputTable. This is
596 // needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
597 OS << SentinelEntry << "\t";
598 OS << " // state " << numStates << ": " << ValidTransitions;
602 OS << "// " << TargetName << "DFAStateEntryTable[i] = "
603 << "Index of the first entry in DFAStateInputTable for\n";
605 << "the ith state.\n";
606 OS << "// " << numStates << " states\n";
607 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
609 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
611 unsigned lastState = 0;
612 for (unsigned i = 0; i < numStates; ++i) {
613 if (i && ((i % 10) == 0)) {
615 OS << " // states " << (i-10) << ":" << lastState << "\n";
617 OS << StateEntry[i] << ", ";
620 // Print out the index to the sentinel entry in StateInputTable
621 OS << ValidTransitions << ", ";
622 OS << " // states " << (lastState+1) << ":" << numStates << "\n";
625 OS << "} // namespace\n";
628 // Emit DFA Packetizer tables if the target is a VLIW machine.
630 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
631 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
632 OS << "namespace llvm {\n";
633 OS << "DFAPacketizer *" << SubTargetClassName << "::"
634 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
635 << " return new DFAPacketizer(IID, " << TargetName
636 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
637 OS << "} // End llvm namespace \n";
641 // collectAllFuncUnits - Construct a map of function unit names to bits.
643 int DFAPacketizerEmitter::collectAllFuncUnits(
644 std::vector<Record*> &ProcItinList,
645 std::map<std::string, unsigned> &FUNameToBitsMap,
648 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
649 DEBUG(dbgs() << "collectAllFuncUnits");
650 DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
653 // Parse functional units for all the itineraries.
654 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
655 Record *Proc = ProcItinList[i];
656 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
658 DEBUG(dbgs() << " FU:" << i
659 << " (" << FUs.size() << " FUs) "
663 // Convert macros to bits for each stage.
664 unsigned numFUs = FUs.size();
665 for (unsigned j = 0; j < numFUs; ++j) {
666 assert ((j < DFA_MAX_RESOURCES) &&
667 "Exceeded maximum number of representable resources");
668 unsigned FuncResources = (unsigned) (1U << j);
669 FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
670 DEBUG(dbgs() << " " << FUs[j]->getName()
671 << ":0x" << utohexstr(FuncResources));
673 if (((int) numFUs) > maxFUs) {
677 DEBUG(dbgs() << "\n");
683 // collectAllComboFuncs - Construct a map from a combo function unit bit to
684 // the bits of all included functional units.
686 int DFAPacketizerEmitter::collectAllComboFuncs(
687 std::vector<Record*> &ComboFuncList,
688 std::map<std::string, unsigned> &FUNameToBitsMap,
689 std::map<unsigned, unsigned> &ComboBitToBitsMap,
691 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
692 DEBUG(dbgs() << "collectAllComboFuncs");
693 DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
696 for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
697 Record *Func = ComboFuncList[i];
698 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
700 DEBUG(dbgs() << " CFD:" << i
701 << " (" << FUs.size() << " combo FUs) "
702 << Func->getName() << "\n");
704 // Convert macros to bits for each stage.
705 for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
706 assert ((j < DFA_MAX_RESOURCES) &&
707 "Exceeded maximum number of DFA resources");
708 Record *FuncData = FUs[j];
709 Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
710 const std::vector<Record*> &FuncList =
711 FuncData->getValueAsListOfDefs("FuncList");
712 const std::string &ComboFuncName = ComboFunc->getName();
713 unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
714 unsigned ComboResources = ComboBit;
715 DEBUG(dbgs() << " combo: " << ComboFuncName
716 << ":0x" << utohexstr(ComboResources) << "\n");
717 for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
718 std::string FuncName = FuncList[k]->getName();
719 unsigned FuncResources = FUNameToBitsMap[FuncName];
720 DEBUG(dbgs() << " " << FuncName
721 << ":0x" << utohexstr(FuncResources) << "\n");
722 ComboResources |= FuncResources;
724 ComboBitToBitsMap[ComboBit] = ComboResources;
726 DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
727 << utohexstr(ComboBit) << " = 0x"
728 << utohexstr(ComboResources) << "\n");
735 // collectOneInsnClass - Populate allInsnClasses with one instruction class
737 int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
738 std::vector<Record*> &ProcItinList,
739 std::map<std::string, unsigned> &FUNameToBitsMap,
742 const std::vector<Record*> &StageList =
743 ItinData->getValueAsListOfDefs("Stages");
745 // The number of stages.
746 unsigned NStages = StageList.size();
748 DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName()
751 std::vector<unsigned> UnitBits;
753 // Compute the bitwise or of each unit used in this stage.
754 for (unsigned i = 0; i < NStages; ++i) {
755 const Record *Stage = StageList[i];
758 const std::vector<Record*> &UnitList =
759 Stage->getValueAsListOfDefs("Units");
761 DEBUG(dbgs() << " stage:" << i
762 << " [" << UnitList.size() << " units]:");
763 unsigned dbglen = 26; // cursor after stage dbgs
765 // Compute the bitwise or of each unit used in this stage.
766 unsigned UnitBitValue = 0;
767 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
768 // Conduct bitwise or.
769 std::string UnitName = UnitList[j]->getName();
770 DEBUG(dbgs() << " " << j << ":" << UnitName);
771 dbglen += 3 + UnitName.length();
772 assert(FUNameToBitsMap.count(UnitName));
773 UnitBitValue |= FUNameToBitsMap[UnitName];
776 if (UnitBitValue != 0)
777 UnitBits.push_back(UnitBitValue);
779 while (dbglen <= 64) { // line up bits dbgs
781 DEBUG(dbgs() << "\t");
783 DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
786 if (UnitBits.size() > 0)
787 allInsnClasses.push_back(UnitBits);
791 dbgsInsnClass(UnitBits);
799 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
800 // used in each stage.
802 int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
803 std::vector<Record*> &ProcItinList,
804 std::map<std::string, unsigned> &FUNameToBitsMap,
805 std::vector<Record*> &ItinDataList,
808 // Collect all instruction classes.
809 unsigned M = ItinDataList.size();
811 int numInsnClasses = 0;
812 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"
813 << "collectAllInsnClasses "
815 << " (" << M << " classes)\n");
817 // Collect stages for each instruction class for all itinerary data
818 for (unsigned j = 0; j < M; j++) {
819 Record *ItinData = ItinDataList[j];
820 int NStages = collectOneInsnClass(ProcName, ProcItinList,
821 FUNameToBitsMap, ItinData, OS);
822 if (NStages > maxStages) {
827 return numInsnClasses;
831 // Run the worklist algorithm to generate the DFA.
833 void DFAPacketizerEmitter::run(raw_ostream &OS) {
835 // Collect processor iteraries.
836 std::vector<Record*> ProcItinList =
837 Records.getAllDerivedDefinitions("ProcessorItineraries");
840 // Collect the Functional units.
842 std::map<std::string, unsigned> FUNameToBitsMap;
843 int maxResources = 0;
844 collectAllFuncUnits(ProcItinList,
845 FUNameToBitsMap, maxResources, OS);
848 // Collect the Combo Functional units.
850 std::map<unsigned, unsigned> ComboBitToBitsMap;
851 std::vector<Record*> ComboFuncList =
852 Records.getAllDerivedDefinitions("ComboFuncUnits");
853 int numCombos = collectAllComboFuncs(ComboFuncList,
854 FUNameToBitsMap, ComboBitToBitsMap, OS);
857 // Collect the itineraries.
860 int numInsnClasses = 0;
861 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
862 Record *Proc = ProcItinList[i];
864 // Get processor itinerary name.
865 const std::string &ProcName = Proc->getName();
868 if (ProcName == "NoItineraries")
871 // Sanity check for at least one instruction itinerary class.
872 unsigned NItinClasses =
873 Records.getAllDerivedDefinitions("InstrItinClass").size();
874 if (NItinClasses == 0)
877 // Get itinerary data list.
878 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
880 // Collect all instruction classes
881 numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
882 FUNameToBitsMap, ItinDataList, maxStages, OS);
886 // Run a worklist algorithm to generate the DFA.
889 const State *Initial = &D.newState();
890 Initial->isInitial = true;
891 Initial->stateInfo.insert(0x0);
892 SmallVector<const State*, 32> WorkList;
893 // std::queue<State*> WorkList;
894 std::map<std::set<unsigned>, const State*> Visited;
896 WorkList.push_back(Initial);
899 // Worklist algorithm to create a DFA for processor resource tracking.
900 // C = {set of InsnClasses}
901 // Begin with initial node in worklist. Initial node does not have
902 // any consumed resources,
903 // ResourceState = 0x0
905 // While worklist != empty
906 // S = first element of worklist
907 // For every instruction class C
908 // if we can accommodate C in S:
909 // S' = state with resource states = {S Union C}
910 // Add a new transition: S x C -> S'
911 // If S' is not in Visited:
912 // Add S' to worklist
915 while (!WorkList.empty()) {
916 const State *current = WorkList.pop_back_val();
918 dbgs() << "---------------------\n";
919 dbgs() << "Processing state: " << current->stateNum << " - ";
920 dbgsStateInfo(current->stateInfo);
923 for (unsigned i = 0; i < allInsnClasses.size(); i++) {
924 std::vector<unsigned> InsnClass = allInsnClasses[i];
927 dbgsInsnClass(InsnClass);
931 std::set<unsigned> NewStateResources;
933 // If we haven't already created a transition for this input
934 // and the state can accommodate this InsnClass, create a transition.
936 if (!current->hasTransition(InsnClass) &&
937 current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
938 const State *NewState = nullptr;
939 current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
940 if (NewStateResources.size() == 0) {
941 DEBUG(dbgs() << " Skipped - no new states generated\n");
947 dbgsStateInfo(NewStateResources);
952 // If we have seen this state before, then do not create a new state.
954 auto VI = Visited.find(NewStateResources);
955 if (VI != Visited.end()) {
956 NewState = VI->second;
958 dbgs() << "\tFound existing state: " << NewState->stateNum
960 dbgsStateInfo(NewState->stateInfo);
964 NewState = &D.newState();
965 NewState->stateInfo = NewStateResources;
966 Visited[NewStateResources] = NewState;
967 WorkList.push_back(NewState);
969 dbgs() << "\tAccepted new state: " << NewState->stateNum << " - ";
970 dbgsStateInfo(NewState->stateInfo);
975 current->addTransition(InsnClass, NewState);
980 // Print out the table.
981 D.writeTableAndAPI(OS, TargetName,
982 numInsnClasses, maxResources, numCombos, maxStages);
987 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
988 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
989 DFAPacketizerEmitter(RK).run(OS);
992 } // end namespaec llvm