1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "CodeGenDAGPatterns.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
31 /// InstructionMemo - This class holds additional information about an
32 /// instruction needed to emit code for it.
35 struct InstructionMemo {
37 const CodeGenRegisterClass *RC;
39 std::vector<std::string>* PhysRegs;
40 std::string PredicateCheck;
42 } // End anonymous namespace
44 /// ImmPredicateSet - This uniques predicates (represented as a string) and
45 /// gives them unique (small) integer ID's that start at 0.
47 class ImmPredicateSet {
48 DenseMap<TreePattern *, unsigned> ImmIDs;
49 std::vector<TreePredicateFn> PredsByName;
52 unsigned getIDFor(TreePredicateFn Pred) {
53 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
55 PredsByName.push_back(Pred);
56 Entry = PredsByName.size();
61 const TreePredicateFn &getPredicate(unsigned i) {
62 assert(i < PredsByName.size());
63 return PredsByName[i];
66 typedef std::vector<TreePredicateFn>::const_iterator iterator;
67 iterator begin() const { return PredsByName.begin(); }
68 iterator end() const { return PredsByName.end(); }
71 } // End anonymous namespace
73 /// OperandsSignature - This class holds a description of a list of operand
74 /// types. It has utility methods for emitting text based on the operands.
77 struct OperandsSignature {
79 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
83 OpKind() : Repr(OK_Invalid) {}
85 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
86 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
88 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
89 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
90 static OpKind getImm(unsigned V) {
91 assert((unsigned)OK_Imm+V < 128 &&
92 "Too many integer predicates for the 'Repr' char");
93 OpKind K; K.Repr = OK_Imm+V; return K;
96 bool isReg() const { return Repr == OK_Reg; }
97 bool isFP() const { return Repr == OK_FP; }
98 bool isImm() const { return Repr >= OK_Imm; }
100 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
102 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
103 bool StripImmCodes) const {
111 if (unsigned Code = getImmCode())
112 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
118 SmallVector<OpKind, 3> Operands;
120 bool operator<(const OperandsSignature &O) const {
121 return Operands < O.Operands;
123 bool operator==(const OperandsSignature &O) const {
124 return Operands == O.Operands;
127 bool empty() const { return Operands.empty(); }
129 bool hasAnyImmediateCodes() const {
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
136 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
138 OperandsSignature getWithoutImmCodes() const {
139 OperandsSignature Result;
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
141 if (!Operands[i].isImm())
142 Result.Operands.push_back(Operands[i]);
144 Result.Operands.push_back(OpKind::getImm(0));
148 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
149 bool EmittedAnything = false;
150 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
151 if (!Operands[i].isImm()) continue;
153 unsigned Code = Operands[i].getImmCode();
154 if (Code == 0) continue;
159 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
161 // Emit the type check.
163 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
167 OS << PredFn.getFnName() << "(imm" << i <<')';
168 EmittedAnything = true;
172 /// initialize - Examine the given pattern and initialize the contents
173 /// of the Operands array accordingly. Return true if all the operands
174 /// are supported, false otherwise.
176 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
177 MVT::SimpleValueType VT,
178 ImmPredicateSet &ImmediatePredicates,
179 const CodeGenRegisterClass *OrigDstRC) {
180 if (InstPatNode->isLeaf())
183 if (InstPatNode->getOperator()->getName() == "imm") {
184 Operands.push_back(OpKind::getImm(0));
188 if (InstPatNode->getOperator()->getName() == "fpimm") {
189 Operands.push_back(OpKind::getFP());
193 const CodeGenRegisterClass *DstRC = nullptr;
195 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
196 TreePatternNode *Op = InstPatNode->getChild(i);
198 // Handle imm operands specially.
199 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
201 if (!Op->getPredicateFns().empty()) {
202 TreePredicateFn PredFn = Op->getPredicateFns()[0];
203 // If there is more than one predicate weighing in on this operand
204 // then we don't handle it. This doesn't typically happen for
205 // immediates anyway.
206 if (Op->getPredicateFns().size() > 1 ||
207 !PredFn.isImmediatePattern())
209 // Ignore any instruction with 'FastIselShouldIgnore', these are
210 // not needed and just bloat the fast instruction selector. For
211 // example, X86 doesn't need to generate code to match ADD16ri8 since
212 // ADD16ri will do just fine.
213 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
214 if (Rec->getValueAsBit("FastIselShouldIgnore"))
217 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
220 // Handle unmatched immediate sizes here.
221 //if (Op->getType(0) != VT)
224 Operands.push_back(OpKind::getImm(PredNo));
229 // For now, filter out any operand with a predicate.
230 // For now, filter out any operand with multiple values.
231 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
235 if (Op->getOperator()->getName() == "fpimm") {
236 Operands.push_back(OpKind::getFP());
239 // For now, ignore other non-leaf nodes.
243 assert(Op->hasTypeSet(0) && "Type infererence not done?");
245 // For now, all the operands must have the same type (if they aren't
246 // immediates). Note that this causes us to reject variable sized shifts
248 if (Op->getType(0) != VT)
251 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
254 Record *OpLeafRec = OpDI->getDef();
256 // For now, the only other thing we accept is register operands.
257 const CodeGenRegisterClass *RC = nullptr;
258 if (OpLeafRec->isSubClassOf("RegisterOperand"))
259 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
260 if (OpLeafRec->isSubClassOf("RegisterClass"))
261 RC = &Target.getRegisterClass(OpLeafRec);
262 else if (OpLeafRec->isSubClassOf("Register"))
263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
264 else if (OpLeafRec->isSubClassOf("ValueType")) {
269 // For now, this needs to be a register class of some sort.
273 // For now, all the operands must have the same register class or be
274 // a strict subclass of the destination.
276 if (DstRC != RC && !DstRC->hasSubClass(RC))
280 Operands.push_back(OpKind::getReg());
285 void PrintParameters(raw_ostream &OS) const {
286 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
287 if (Operands[i].isReg()) {
288 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
289 } else if (Operands[i].isImm()) {
290 OS << "uint64_t imm" << i;
291 } else if (Operands[i].isFP()) {
292 OS << "const ConstantFP *f" << i;
294 llvm_unreachable("Unknown operand kind!");
301 void PrintArguments(raw_ostream &OS,
302 const std::vector<std::string> &PR) const {
303 assert(PR.size() == Operands.size());
304 bool PrintedArg = false;
305 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
307 // Implicit physical register operand.
312 if (Operands[i].isReg()) {
313 OS << "Op" << i << ", Op" << i << "IsKill";
315 } else if (Operands[i].isImm()) {
318 } else if (Operands[i].isFP()) {
322 llvm_unreachable("Unknown operand kind!");
327 void PrintArguments(raw_ostream &OS) const {
328 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
329 if (Operands[i].isReg()) {
330 OS << "Op" << i << ", Op" << i << "IsKill";
331 } else if (Operands[i].isImm()) {
333 } else if (Operands[i].isFP()) {
336 llvm_unreachable("Unknown operand kind!");
344 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
345 ImmPredicateSet &ImmPredicates,
346 bool StripImmCodes = false) const {
347 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
349 // Implicit physical register operand. e.g. Instruction::Mul expect to
350 // select to a binary op. On x86, mul may take a single operand with
351 // the other operand being implicit. We must emit something that looks
352 // like a binary instruction except for the very inner fastEmitInst_*
355 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
359 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
360 bool StripImmCodes = false) const {
361 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
362 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
365 } // End anonymous namespace
369 // A multimap is needed instead of a "plain" map because the key is
370 // the instruction's complexity (an int) and they are not unique.
371 typedef std::multimap<int, InstructionMemo> PredMap;
372 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
373 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
374 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
375 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
376 OperandsOpcodeTypeRetPredMap;
378 OperandsOpcodeTypeRetPredMap SimplePatterns;
380 // This is used to check that there are no duplicate predicates
381 typedef std::multimap<std::string, bool> PredCheckMap;
382 typedef std::map<MVT::SimpleValueType, PredCheckMap> RetPredCheckMap;
383 typedef std::map<MVT::SimpleValueType, RetPredCheckMap> TypeRetPredCheckMap;
384 typedef std::map<std::string, TypeRetPredCheckMap> OpcodeTypeRetPredCheckMap;
385 typedef std::map<OperandsSignature, OpcodeTypeRetPredCheckMap>
386 OperandsOpcodeTypeRetPredCheckMap;
388 OperandsOpcodeTypeRetPredCheckMap SimplePatternsCheck;
390 std::map<OperandsSignature, std::vector<OperandsSignature> >
391 SignaturesWithConstantForms;
394 ImmPredicateSet ImmediatePredicates;
396 explicit FastISelMap(std::string InstNS);
398 void collectPatterns(CodeGenDAGPatterns &CGP);
399 void printImmediatePredicates(raw_ostream &OS);
400 void printFunctionDefinitions(raw_ostream &OS);
402 void emitInstructionCode(raw_ostream &OS,
403 const OperandsSignature &Operands,
405 const std::string &RetVTName);
407 } // End anonymous namespace
409 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
410 return CGP.getSDNodeInfo(Op).getEnumName();
413 static std::string getLegalCName(std::string OpName) {
414 std::string::size_type pos = OpName.find("::");
415 if (pos != std::string::npos)
416 OpName.replace(pos, 2, "_");
420 FastISelMap::FastISelMap(std::string instns) : InstNS(std::move(instns)) {}
422 static std::string PhyRegForNode(TreePatternNode *Op,
423 const CodeGenTarget &Target) {
429 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
430 if (!OpLeafRec->isSubClassOf("Register"))
433 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
436 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
440 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
441 const CodeGenTarget &Target = CGP.getTargetInfo();
443 // Determine the target's namespace name.
444 InstNS = Target.getInstNamespace() + "::";
445 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
447 // Scan through all the patterns and record the simple ones.
448 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
449 E = CGP.ptm_end(); I != E; ++I) {
450 const PatternToMatch &Pattern = *I;
452 // For now, just look at Instructions, so that we don't have to worry
453 // about emitting multiple instructions for a pattern.
454 TreePatternNode *Dst = Pattern.getDstPattern();
455 if (Dst->isLeaf()) continue;
456 Record *Op = Dst->getOperator();
457 if (!Op->isSubClassOf("Instruction"))
459 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
460 if (II.Operands.empty())
463 // For now, ignore multi-instruction patterns.
464 bool MultiInsts = false;
465 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
466 TreePatternNode *ChildOp = Dst->getChild(i);
467 if (ChildOp->isLeaf())
469 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
477 // For now, ignore instructions where the first operand is not an
479 const CodeGenRegisterClass *DstRC = nullptr;
480 std::string SubRegNo;
481 if (Op->getName() != "EXTRACT_SUBREG") {
482 Record *Op0Rec = II.Operands[0].Rec;
483 if (Op0Rec->isSubClassOf("RegisterOperand"))
484 Op0Rec = Op0Rec->getValueAsDef("RegClass");
485 if (!Op0Rec->isSubClassOf("RegisterClass"))
487 DstRC = &Target.getRegisterClass(Op0Rec);
491 // If this isn't a leaf, then continue since the register classes are
492 // a bit too complicated for now.
493 if (!Dst->getChild(1)->isLeaf()) continue;
495 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
497 SubRegNo = getQualifiedName(SR->getDef());
499 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
502 // Inspect the pattern.
503 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
504 if (!InstPatNode) continue;
505 if (InstPatNode->isLeaf()) continue;
507 // Ignore multiple result nodes for now.
508 if (InstPatNode->getNumTypes() > 1) continue;
510 Record *InstPatOp = InstPatNode->getOperator();
511 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
512 MVT::SimpleValueType RetVT = MVT::isVoid;
513 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
514 MVT::SimpleValueType VT = RetVT;
515 if (InstPatNode->getNumChildren()) {
516 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
517 VT = InstPatNode->getChild(0)->getType(0);
520 // For now, filter out any instructions with predicates.
521 if (!InstPatNode->getPredicateFns().empty())
524 // Check all the operands.
525 OperandsSignature Operands;
526 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
530 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
531 if (InstPatNode->getOperator()->getName() == "imm" ||
532 InstPatNode->getOperator()->getName() == "fpimm")
533 PhysRegInputs->push_back("");
535 // Compute the PhysRegs used by the given pattern, and check that
536 // the mapping from the src to dst patterns is simple.
537 bool FoundNonSimplePattern = false;
538 unsigned DstIndex = 0;
539 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
540 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
541 if (PhysReg.empty()) {
542 if (DstIndex >= Dst->getNumChildren() ||
543 Dst->getChild(DstIndex)->getName() !=
544 InstPatNode->getChild(i)->getName()) {
545 FoundNonSimplePattern = true;
551 PhysRegInputs->push_back(PhysReg);
554 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
555 FoundNonSimplePattern = true;
557 if (FoundNonSimplePattern)
561 // Check if the operands match one of the patterns handled by FastISel.
562 std::string ManglingSuffix;
563 raw_string_ostream SuffixOS(ManglingSuffix);
564 Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
566 if (!StringSwitch<bool>(ManglingSuffix)
567 .Cases("", "r", "rr", "ri", "i", "f", true)
571 // Get the predicate that guards this pattern.
572 std::string PredicateCheck = Pattern.getPredicateCheck();
574 // Ok, we found a pattern that we can handle. Remember it.
575 InstructionMemo Memo = {
576 Pattern.getDstPattern()->getOperator()->getName(),
583 int complexity = Pattern.getPatternComplexity(CGP);
585 if (SimplePatternsCheck[Operands][OpcodeName][VT]
586 [RetVT].count(PredicateCheck)) {
587 PrintFatalError(Pattern.getSrcRecord()->getLoc(),
588 "Duplicate predicate in FastISel table!");
590 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
591 std::make_pair(PredicateCheck, true));
593 // Note: Instructions with the same complexity will appear in the order
594 // that they are encountered.
595 SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
596 std::make_pair(complexity, Memo));
598 // If any of the operands were immediates with predicates on them, strip
599 // them down to a signature that doesn't have predicates so that we can
600 // associate them with the stripped predicate version.
601 if (Operands.hasAnyImmediateCodes()) {
602 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
603 .push_back(Operands);
608 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
609 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
612 OS << "\n// FastEmit Immediate Predicate functions.\n";
613 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
614 E = ImmediatePredicates.end(); I != E; ++I) {
615 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
616 OS << I->getImmediatePredicateCode() << "\n}\n";
622 void FastISelMap::emitInstructionCode(raw_ostream &OS,
623 const OperandsSignature &Operands,
625 const std::string &RetVTName) {
626 // Emit code for each possible instruction. There may be
627 // multiple if there are subtarget concerns. A reverse iterator
628 // is used to produce the ones with highest complexity first.
630 bool OneHadNoPredicate = false;
631 for (PredMap::const_reverse_iterator PI = PM.rbegin(), PE = PM.rend();
633 const InstructionMemo &Memo = PI->second;
634 std::string PredicateCheck = Memo.PredicateCheck;
636 if (PredicateCheck.empty()) {
637 assert(!OneHadNoPredicate &&
638 "Multiple instructions match and more than one had "
640 OneHadNoPredicate = true;
642 if (OneHadNoPredicate) {
643 // FIXME: This should be a PrintError once the x86 target
645 PrintWarning("Multiple instructions match and one with no "
646 "predicate came before one with a predicate! "
647 "name:" + Memo.Name + " predicate: " +
650 OS << " if (" + PredicateCheck + ") {\n";
654 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
655 if ((*Memo.PhysRegs)[i] != "")
656 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
657 << "TII.get(TargetOpcode::COPY), "
658 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
661 OS << " return fastEmitInst_";
662 if (Memo.SubRegNo.empty()) {
663 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
664 ImmediatePredicates, true);
665 OS << "(" << InstNS << Memo.Name << ", ";
666 OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
667 if (!Operands.empty())
669 Operands.PrintArguments(OS, *Memo.PhysRegs);
672 OS << "extractsubreg(" << RetVTName
673 << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
676 if (!PredicateCheck.empty()) {
680 // Return 0 if all of the possibilities had predicates but none
682 if (!OneHadNoPredicate)
683 OS << " return 0;\n";
689 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
690 // Now emit code for all the patterns that we collected.
691 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
692 OE = SimplePatterns.end(); OI != OE; ++OI) {
693 const OperandsSignature &Operands = OI->first;
694 const OpcodeTypeRetPredMap &OTM = OI->second;
696 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
698 const std::string &Opcode = I->first;
699 const TypeRetPredMap &TM = I->second;
701 OS << "// FastEmit functions for " << Opcode << ".\n";
704 // Emit one function for each opcode,type pair.
705 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
707 MVT::SimpleValueType VT = TI->first;
708 const RetPredMap &RM = TI->second;
709 if (RM.size() != 1) {
710 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
712 MVT::SimpleValueType RetVT = RI->first;
713 const PredMap &PM = RI->second;
715 OS << "unsigned fastEmit_"
716 << getLegalCName(Opcode)
717 << "_" << getLegalCName(getName(VT))
718 << "_" << getLegalCName(getName(RetVT)) << "_";
719 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
721 Operands.PrintParameters(OS);
724 emitInstructionCode(OS, Operands, PM, getName(RetVT));
727 // Emit one function for the type that demultiplexes on return type.
728 OS << "unsigned fastEmit_"
729 << getLegalCName(Opcode) << "_"
730 << getLegalCName(getName(VT)) << "_";
731 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
733 if (!Operands.empty())
735 Operands.PrintParameters(OS);
736 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
737 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
739 MVT::SimpleValueType RetVT = RI->first;
740 OS << " case " << getName(RetVT) << ": return fastEmit_"
741 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
742 << "_" << getLegalCName(getName(RetVT)) << "_";
743 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
745 Operands.PrintArguments(OS);
748 OS << " default: return 0;\n}\n}\n\n";
751 // Non-variadic return type.
752 OS << "unsigned fastEmit_"
753 << getLegalCName(Opcode) << "_"
754 << getLegalCName(getName(VT)) << "_";
755 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
757 if (!Operands.empty())
759 Operands.PrintParameters(OS);
762 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
763 << ")\n return 0;\n";
765 const PredMap &PM = RM.begin()->second;
767 emitInstructionCode(OS, Operands, PM, "RetVT");
771 // Emit one function for the opcode that demultiplexes based on the type.
772 OS << "unsigned fastEmit_"
773 << getLegalCName(Opcode) << "_";
774 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
775 OS << "(MVT VT, MVT RetVT";
776 if (!Operands.empty())
778 Operands.PrintParameters(OS);
780 OS << " switch (VT.SimpleTy) {\n";
781 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
783 MVT::SimpleValueType VT = TI->first;
784 std::string TypeName = getName(VT);
785 OS << " case " << TypeName << ": return fastEmit_"
786 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
787 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
789 if (!Operands.empty())
791 Operands.PrintArguments(OS);
794 OS << " default: return 0;\n";
800 OS << "// Top-level FastEmit function.\n";
803 // Emit one function for the operand signature that demultiplexes based
804 // on opcode and type.
805 OS << "unsigned fastEmit_";
806 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
807 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
808 if (!Operands.empty())
810 Operands.PrintParameters(OS);
812 if (!Operands.hasAnyImmediateCodes())
816 // If there are any forms of this signature available that operate on
817 // constrained forms of the immediate (e.g., 32-bit sext immediate in a
818 // 64-bit operand), check them first.
820 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
821 = SignaturesWithConstantForms.find(Operands);
822 if (MI != SignaturesWithConstantForms.end()) {
823 // Unique any duplicates out of the list.
824 std::sort(MI->second.begin(), MI->second.end());
825 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
828 // Check each in order it was seen. It would be nice to have a good
829 // relative ordering between them, but we're not going for optimality
831 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
833 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
834 OS << ")\n if (unsigned Reg = fastEmit_";
835 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
836 OS << "(VT, RetVT, Opcode";
837 if (!MI->second[i].empty())
839 MI->second[i].PrintArguments(OS);
840 OS << "))\n return Reg;\n\n";
843 // Done with this, remove it.
844 SignaturesWithConstantForms.erase(MI);
847 OS << " switch (Opcode) {\n";
848 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
850 const std::string &Opcode = I->first;
852 OS << " case " << Opcode << ": return fastEmit_"
853 << getLegalCName(Opcode) << "_";
854 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
856 if (!Operands.empty())
858 Operands.PrintArguments(OS);
861 OS << " default: return 0;\n";
867 // TODO: SignaturesWithConstantForms should be empty here.
872 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
873 CodeGenDAGPatterns CGP(RK);
874 const CodeGenTarget &Target = CGP.getTargetInfo();
875 emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
876 Target.getName().str() + " target", OS);
878 // Determine the target's namespace name.
879 std::string InstNS = Target.getInstNamespace() + "::";
880 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
882 FastISelMap F(InstNS);
883 F.collectPatterns(CGP);
884 F.printImmediatePredicates(OS);
885 F.printFunctionDefinitions(OS);
888 } // End llvm namespace