1 ///===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits code for use by the "fast" instruction
11 // selection algorithm. See the comments at the top of
12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background.
14 // This file scans through the target's tablegen instruction-info files
15 // and extracts instructions with obvious-looking patterns, and it emits
16 // code to look up these instructions by type and operator.
18 //===----------------------------------------------------------------------===//
20 #include "CodeGenDAGPatterns.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
31 /// InstructionMemo - This class holds additional information about an
32 /// instruction needed to emit code for it.
35 struct InstructionMemo {
37 const CodeGenRegisterClass *RC;
39 std::vector<std::string>* PhysRegs;
40 std::string PredicateCheck;
42 } // End anonymous namespace
44 /// ImmPredicateSet - This uniques predicates (represented as a string) and
45 /// gives them unique (small) integer ID's that start at 0.
47 class ImmPredicateSet {
48 DenseMap<TreePattern *, unsigned> ImmIDs;
49 std::vector<TreePredicateFn> PredsByName;
52 unsigned getIDFor(TreePredicateFn Pred) {
53 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
55 PredsByName.push_back(Pred);
56 Entry = PredsByName.size();
61 const TreePredicateFn &getPredicate(unsigned i) {
62 assert(i < PredsByName.size());
63 return PredsByName[i];
66 typedef std::vector<TreePredicateFn>::const_iterator iterator;
67 iterator begin() const { return PredsByName.begin(); }
68 iterator end() const { return PredsByName.end(); }
71 } // End anonymous namespace
73 /// OperandsSignature - This class holds a description of a list of operand
74 /// types. It has utility methods for emitting text based on the operands.
77 struct OperandsSignature {
79 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
83 OpKind() : Repr(OK_Invalid) {}
85 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
86 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
88 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
89 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
90 static OpKind getImm(unsigned V) {
91 assert((unsigned)OK_Imm+V < 128 &&
92 "Too many integer predicates for the 'Repr' char");
93 OpKind K; K.Repr = OK_Imm+V; return K;
96 bool isReg() const { return Repr == OK_Reg; }
97 bool isFP() const { return Repr == OK_FP; }
98 bool isImm() const { return Repr >= OK_Imm; }
100 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
102 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
103 bool StripImmCodes) const {
111 if (unsigned Code = getImmCode())
112 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
118 SmallVector<OpKind, 3> Operands;
120 bool operator<(const OperandsSignature &O) const {
121 return Operands < O.Operands;
123 bool operator==(const OperandsSignature &O) const {
124 return Operands == O.Operands;
127 bool empty() const { return Operands.empty(); }
129 bool hasAnyImmediateCodes() const {
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
136 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
138 OperandsSignature getWithoutImmCodes() const {
139 OperandsSignature Result;
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
141 if (!Operands[i].isImm())
142 Result.Operands.push_back(Operands[i]);
144 Result.Operands.push_back(OpKind::getImm(0));
148 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
149 bool EmittedAnything = false;
150 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
151 if (!Operands[i].isImm()) continue;
153 unsigned Code = Operands[i].getImmCode();
154 if (Code == 0) continue;
159 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
161 // Emit the type check.
162 TreePattern *TP = PredFn.getOrigPatFragRecord();
163 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0);
164 assert(VVT.isSimple() &&
165 "Cannot use variable value types with fast isel");
166 OS << "VT == " << getEnumName(VVT.getSimple().SimpleTy) << " && ";
168 OS << PredFn.getFnName() << "(imm" << i <<')';
169 EmittedAnything = true;
173 /// initialize - Examine the given pattern and initialize the contents
174 /// of the Operands array accordingly. Return true if all the operands
175 /// are supported, false otherwise.
177 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
178 MVT::SimpleValueType VT,
179 ImmPredicateSet &ImmediatePredicates,
180 const CodeGenRegisterClass *OrigDstRC) {
181 if (InstPatNode->isLeaf())
184 if (InstPatNode->getOperator()->getName() == "imm") {
185 Operands.push_back(OpKind::getImm(0));
189 if (InstPatNode->getOperator()->getName() == "fpimm") {
190 Operands.push_back(OpKind::getFP());
194 const CodeGenRegisterClass *DstRC = nullptr;
196 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
197 TreePatternNode *Op = InstPatNode->getChild(i);
199 // Handle imm operands specially.
200 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
202 if (!Op->getPredicateFns().empty()) {
203 TreePredicateFn PredFn = Op->getPredicateFns()[0];
204 // If there is more than one predicate weighing in on this operand
205 // then we don't handle it. This doesn't typically happen for
206 // immediates anyway.
207 if (Op->getPredicateFns().size() > 1 ||
208 !PredFn.isImmediatePattern())
210 // Ignore any instruction with 'FastIselShouldIgnore', these are
211 // not needed and just bloat the fast instruction selector. For
212 // example, X86 doesn't need to generate code to match ADD16ri8 since
213 // ADD16ri will do just fine.
214 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
215 if (Rec->getValueAsBit("FastIselShouldIgnore"))
218 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
221 Operands.push_back(OpKind::getImm(PredNo));
226 // For now, filter out any operand with a predicate.
227 // For now, filter out any operand with multiple values.
228 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
232 if (Op->getOperator()->getName() == "fpimm") {
233 Operands.push_back(OpKind::getFP());
236 // For now, ignore other non-leaf nodes.
240 assert(Op->hasConcreteType(0) && "Type infererence not done?");
242 // For now, all the operands must have the same type (if they aren't
243 // immediates). Note that this causes us to reject variable sized shifts
245 if (Op->getSimpleType(0) != VT)
248 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
251 Record *OpLeafRec = OpDI->getDef();
253 // For now, the only other thing we accept is register operands.
254 const CodeGenRegisterClass *RC = nullptr;
255 if (OpLeafRec->isSubClassOf("RegisterOperand"))
256 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
257 if (OpLeafRec->isSubClassOf("RegisterClass"))
258 RC = &Target.getRegisterClass(OpLeafRec);
259 else if (OpLeafRec->isSubClassOf("Register"))
260 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261 else if (OpLeafRec->isSubClassOf("ValueType")) {
266 // For now, this needs to be a register class of some sort.
270 // For now, all the operands must have the same register class or be
271 // a strict subclass of the destination.
273 if (DstRC != RC && !DstRC->hasSubClass(RC))
277 Operands.push_back(OpKind::getReg());
282 void PrintParameters(raw_ostream &OS) const {
283 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
284 if (Operands[i].isReg()) {
285 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
286 } else if (Operands[i].isImm()) {
287 OS << "uint64_t imm" << i;
288 } else if (Operands[i].isFP()) {
289 OS << "const ConstantFP *f" << i;
291 llvm_unreachable("Unknown operand kind!");
298 void PrintArguments(raw_ostream &OS,
299 const std::vector<std::string> &PR) const {
300 assert(PR.size() == Operands.size());
301 bool PrintedArg = false;
302 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
304 // Implicit physical register operand.
309 if (Operands[i].isReg()) {
310 OS << "Op" << i << ", Op" << i << "IsKill";
312 } else if (Operands[i].isImm()) {
315 } else if (Operands[i].isFP()) {
319 llvm_unreachable("Unknown operand kind!");
324 void PrintArguments(raw_ostream &OS) const {
325 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
326 if (Operands[i].isReg()) {
327 OS << "Op" << i << ", Op" << i << "IsKill";
328 } else if (Operands[i].isImm()) {
330 } else if (Operands[i].isFP()) {
333 llvm_unreachable("Unknown operand kind!");
341 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
342 ImmPredicateSet &ImmPredicates,
343 bool StripImmCodes = false) const {
344 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
346 // Implicit physical register operand. e.g. Instruction::Mul expect to
347 // select to a binary op. On x86, mul may take a single operand with
348 // the other operand being implicit. We must emit something that looks
349 // like a binary instruction except for the very inner fastEmitInst_*
352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
356 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
357 bool StripImmCodes = false) const {
358 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
359 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
362 } // End anonymous namespace
366 // A multimap is needed instead of a "plain" map because the key is
367 // the instruction's complexity (an int) and they are not unique.
368 typedef std::multimap<int, InstructionMemo> PredMap;
369 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
370 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
371 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
372 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
373 OperandsOpcodeTypeRetPredMap;
375 OperandsOpcodeTypeRetPredMap SimplePatterns;
377 // This is used to check that there are no duplicate predicates
378 typedef std::multimap<std::string, bool> PredCheckMap;
379 typedef std::map<MVT::SimpleValueType, PredCheckMap> RetPredCheckMap;
380 typedef std::map<MVT::SimpleValueType, RetPredCheckMap> TypeRetPredCheckMap;
381 typedef std::map<std::string, TypeRetPredCheckMap> OpcodeTypeRetPredCheckMap;
382 typedef std::map<OperandsSignature, OpcodeTypeRetPredCheckMap>
383 OperandsOpcodeTypeRetPredCheckMap;
385 OperandsOpcodeTypeRetPredCheckMap SimplePatternsCheck;
387 std::map<OperandsSignature, std::vector<OperandsSignature> >
388 SignaturesWithConstantForms;
391 ImmPredicateSet ImmediatePredicates;
393 explicit FastISelMap(StringRef InstNS);
395 void collectPatterns(CodeGenDAGPatterns &CGP);
396 void printImmediatePredicates(raw_ostream &OS);
397 void printFunctionDefinitions(raw_ostream &OS);
399 void emitInstructionCode(raw_ostream &OS,
400 const OperandsSignature &Operands,
402 const std::string &RetVTName);
404 } // End anonymous namespace
406 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
407 return CGP.getSDNodeInfo(Op).getEnumName();
410 static std::string getLegalCName(std::string OpName) {
411 std::string::size_type pos = OpName.find("::");
412 if (pos != std::string::npos)
413 OpName.replace(pos, 2, "_");
417 FastISelMap::FastISelMap(StringRef instns) : InstNS(instns) {}
419 static std::string PhyRegForNode(TreePatternNode *Op,
420 const CodeGenTarget &Target) {
426 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
427 if (!OpLeafRec->isSubClassOf("Register"))
430 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
433 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
437 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
438 const CodeGenTarget &Target = CGP.getTargetInfo();
440 // Scan through all the patterns and record the simple ones.
441 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
442 E = CGP.ptm_end(); I != E; ++I) {
443 const PatternToMatch &Pattern = *I;
445 // For now, just look at Instructions, so that we don't have to worry
446 // about emitting multiple instructions for a pattern.
447 TreePatternNode *Dst = Pattern.getDstPattern();
448 if (Dst->isLeaf()) continue;
449 Record *Op = Dst->getOperator();
450 if (!Op->isSubClassOf("Instruction"))
452 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
453 if (II.Operands.empty())
456 // For now, ignore multi-instruction patterns.
457 bool MultiInsts = false;
458 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
459 TreePatternNode *ChildOp = Dst->getChild(i);
460 if (ChildOp->isLeaf())
462 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
470 // For now, ignore instructions where the first operand is not an
472 const CodeGenRegisterClass *DstRC = nullptr;
473 std::string SubRegNo;
474 if (Op->getName() != "EXTRACT_SUBREG") {
475 Record *Op0Rec = II.Operands[0].Rec;
476 if (Op0Rec->isSubClassOf("RegisterOperand"))
477 Op0Rec = Op0Rec->getValueAsDef("RegClass");
478 if (!Op0Rec->isSubClassOf("RegisterClass"))
480 DstRC = &Target.getRegisterClass(Op0Rec);
484 // If this isn't a leaf, then continue since the register classes are
485 // a bit too complicated for now.
486 if (!Dst->getChild(1)->isLeaf()) continue;
488 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
490 SubRegNo = getQualifiedName(SR->getDef());
492 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
495 // Inspect the pattern.
496 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
497 if (!InstPatNode) continue;
498 if (InstPatNode->isLeaf()) continue;
500 // Ignore multiple result nodes for now.
501 if (InstPatNode->getNumTypes() > 1) continue;
503 Record *InstPatOp = InstPatNode->getOperator();
504 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
505 MVT::SimpleValueType RetVT = MVT::isVoid;
506 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getSimpleType(0);
507 MVT::SimpleValueType VT = RetVT;
508 if (InstPatNode->getNumChildren()) {
509 assert(InstPatNode->getChild(0)->getNumTypes() == 1);
510 VT = InstPatNode->getChild(0)->getSimpleType(0);
513 // For now, filter out any instructions with predicates.
514 if (!InstPatNode->getPredicateFns().empty())
517 // Check all the operands.
518 OperandsSignature Operands;
519 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
523 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
524 if (InstPatNode->getOperator()->getName() == "imm" ||
525 InstPatNode->getOperator()->getName() == "fpimm")
526 PhysRegInputs->push_back("");
528 // Compute the PhysRegs used by the given pattern, and check that
529 // the mapping from the src to dst patterns is simple.
530 bool FoundNonSimplePattern = false;
531 unsigned DstIndex = 0;
532 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
533 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
534 if (PhysReg.empty()) {
535 if (DstIndex >= Dst->getNumChildren() ||
536 Dst->getChild(DstIndex)->getName() !=
537 InstPatNode->getChild(i)->getName()) {
538 FoundNonSimplePattern = true;
544 PhysRegInputs->push_back(PhysReg);
547 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
548 FoundNonSimplePattern = true;
550 if (FoundNonSimplePattern)
554 // Check if the operands match one of the patterns handled by FastISel.
555 std::string ManglingSuffix;
556 raw_string_ostream SuffixOS(ManglingSuffix);
557 Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
559 if (!StringSwitch<bool>(ManglingSuffix)
560 .Cases("", "r", "rr", "ri", "i", "f", true)
564 // Get the predicate that guards this pattern.
565 std::string PredicateCheck = Pattern.getPredicateCheck();
567 // Ok, we found a pattern that we can handle. Remember it.
568 InstructionMemo Memo = {
569 Pattern.getDstPattern()->getOperator()->getName(),
576 int complexity = Pattern.getPatternComplexity(CGP);
578 if (SimplePatternsCheck[Operands][OpcodeName][VT]
579 [RetVT].count(PredicateCheck)) {
580 PrintFatalError(Pattern.getSrcRecord()->getLoc(),
581 "Duplicate predicate in FastISel table!");
583 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
584 std::make_pair(PredicateCheck, true));
586 // Note: Instructions with the same complexity will appear in the order
587 // that they are encountered.
588 SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
589 std::make_pair(complexity, Memo));
591 // If any of the operands were immediates with predicates on them, strip
592 // them down to a signature that doesn't have predicates so that we can
593 // associate them with the stripped predicate version.
594 if (Operands.hasAnyImmediateCodes()) {
595 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
596 .push_back(Operands);
601 void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
602 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
605 OS << "\n// FastEmit Immediate Predicate functions.\n";
606 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
607 E = ImmediatePredicates.end(); I != E; ++I) {
608 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
609 OS << I->getImmediatePredicateCode() << "\n}\n";
615 void FastISelMap::emitInstructionCode(raw_ostream &OS,
616 const OperandsSignature &Operands,
618 const std::string &RetVTName) {
619 // Emit code for each possible instruction. There may be
620 // multiple if there are subtarget concerns. A reverse iterator
621 // is used to produce the ones with highest complexity first.
623 bool OneHadNoPredicate = false;
624 for (PredMap::const_reverse_iterator PI = PM.rbegin(), PE = PM.rend();
626 const InstructionMemo &Memo = PI->second;
627 std::string PredicateCheck = Memo.PredicateCheck;
629 if (PredicateCheck.empty()) {
630 assert(!OneHadNoPredicate &&
631 "Multiple instructions match and more than one had "
633 OneHadNoPredicate = true;
635 if (OneHadNoPredicate) {
636 PrintFatalError("Multiple instructions match and one with no "
637 "predicate came before one with a predicate! "
638 "name:" + Memo.Name + " predicate: " + PredicateCheck);
640 OS << " if (" + PredicateCheck + ") {\n";
644 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
645 if ((*Memo.PhysRegs)[i] != "")
646 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
647 << "TII.get(TargetOpcode::COPY), "
648 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
651 OS << " return fastEmitInst_";
652 if (Memo.SubRegNo.empty()) {
653 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
654 ImmediatePredicates, true);
655 OS << "(" << InstNS << "::" << Memo.Name << ", ";
656 OS << "&" << InstNS << "::" << Memo.RC->getName() << "RegClass";
657 if (!Operands.empty())
659 Operands.PrintArguments(OS, *Memo.PhysRegs);
662 OS << "extractsubreg(" << RetVTName
663 << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
666 if (!PredicateCheck.empty()) {
670 // Return 0 if all of the possibilities had predicates but none
672 if (!OneHadNoPredicate)
673 OS << " return 0;\n";
679 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
680 // Now emit code for all the patterns that we collected.
681 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
682 OE = SimplePatterns.end(); OI != OE; ++OI) {
683 const OperandsSignature &Operands = OI->first;
684 const OpcodeTypeRetPredMap &OTM = OI->second;
686 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
688 const std::string &Opcode = I->first;
689 const TypeRetPredMap &TM = I->second;
691 OS << "// FastEmit functions for " << Opcode << ".\n";
694 // Emit one function for each opcode,type pair.
695 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
697 MVT::SimpleValueType VT = TI->first;
698 const RetPredMap &RM = TI->second;
699 if (RM.size() != 1) {
700 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
702 MVT::SimpleValueType RetVT = RI->first;
703 const PredMap &PM = RI->second;
705 OS << "unsigned fastEmit_"
706 << getLegalCName(Opcode)
707 << "_" << getLegalCName(getName(VT))
708 << "_" << getLegalCName(getName(RetVT)) << "_";
709 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
711 Operands.PrintParameters(OS);
714 emitInstructionCode(OS, Operands, PM, getName(RetVT));
717 // Emit one function for the type that demultiplexes on return type.
718 OS << "unsigned fastEmit_"
719 << getLegalCName(Opcode) << "_"
720 << getLegalCName(getName(VT)) << "_";
721 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
723 if (!Operands.empty())
725 Operands.PrintParameters(OS);
726 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
727 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
729 MVT::SimpleValueType RetVT = RI->first;
730 OS << " case " << getName(RetVT) << ": return fastEmit_"
731 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
732 << "_" << getLegalCName(getName(RetVT)) << "_";
733 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
735 Operands.PrintArguments(OS);
738 OS << " default: return 0;\n}\n}\n\n";
741 // Non-variadic return type.
742 OS << "unsigned fastEmit_"
743 << getLegalCName(Opcode) << "_"
744 << getLegalCName(getName(VT)) << "_";
745 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
747 if (!Operands.empty())
749 Operands.PrintParameters(OS);
752 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
753 << ")\n return 0;\n";
755 const PredMap &PM = RM.begin()->second;
757 emitInstructionCode(OS, Operands, PM, "RetVT");
761 // Emit one function for the opcode that demultiplexes based on the type.
762 OS << "unsigned fastEmit_"
763 << getLegalCName(Opcode) << "_";
764 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
765 OS << "(MVT VT, MVT RetVT";
766 if (!Operands.empty())
768 Operands.PrintParameters(OS);
770 OS << " switch (VT.SimpleTy) {\n";
771 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
773 MVT::SimpleValueType VT = TI->first;
774 std::string TypeName = getName(VT);
775 OS << " case " << TypeName << ": return fastEmit_"
776 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
777 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
779 if (!Operands.empty())
781 Operands.PrintArguments(OS);
784 OS << " default: return 0;\n";
790 OS << "// Top-level FastEmit function.\n";
793 // Emit one function for the operand signature that demultiplexes based
794 // on opcode and type.
795 OS << "unsigned fastEmit_";
796 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
797 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
798 if (!Operands.empty())
800 Operands.PrintParameters(OS);
802 if (!Operands.hasAnyImmediateCodes())
806 // If there are any forms of this signature available that operate on
807 // constrained forms of the immediate (e.g., 32-bit sext immediate in a
808 // 64-bit operand), check them first.
810 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
811 = SignaturesWithConstantForms.find(Operands);
812 if (MI != SignaturesWithConstantForms.end()) {
813 // Unique any duplicates out of the list.
814 std::sort(MI->second.begin(), MI->second.end());
815 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
818 // Check each in order it was seen. It would be nice to have a good
819 // relative ordering between them, but we're not going for optimality
821 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
823 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
824 OS << ")\n if (unsigned Reg = fastEmit_";
825 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
826 OS << "(VT, RetVT, Opcode";
827 if (!MI->second[i].empty())
829 MI->second[i].PrintArguments(OS);
830 OS << "))\n return Reg;\n\n";
833 // Done with this, remove it.
834 SignaturesWithConstantForms.erase(MI);
837 OS << " switch (Opcode) {\n";
838 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
840 const std::string &Opcode = I->first;
842 OS << " case " << Opcode << ": return fastEmit_"
843 << getLegalCName(Opcode) << "_";
844 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
846 if (!Operands.empty())
848 Operands.PrintArguments(OS);
851 OS << " default: return 0;\n";
857 // TODO: SignaturesWithConstantForms should be empty here.
862 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
863 CodeGenDAGPatterns CGP(RK);
864 const CodeGenTarget &Target = CGP.getTargetInfo();
865 emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
866 Target.getName().str() + " target", OS);
868 // Determine the target's namespace name.
869 StringRef InstNS = Target.getInstNamespace();
870 assert(!InstNS.empty() && "Can't determine target-specific namespace!");
872 FastISelMap F(InstNS);
873 F.collectPatterns(CGP);
874 F.printImmediatePredicates(OS);
875 F.printFunctionDefinitions(OS);
878 } // End llvm namespace