1 //===- InstrDocsEmitter.cpp - Opcode Documentation Generator --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // InstrDocsEmitter generates restructured text documentation for the opcodes
11 // that can be used by MachineInstr. For each opcode, the documentation lists:
14 // * Flags (e.g. mayLoad, isBranch, ...)
15 // * Operands, including type and name
16 // * Operand constraints
17 // * Implicit register uses & defs
20 //===----------------------------------------------------------------------===//
22 #include "CodeGenDAGPatterns.h"
23 #include "CodeGenInstruction.h"
24 #include "CodeGenTarget.h"
25 #include "TableGenBackends.h"
26 #include "llvm/TableGen/Record.h"
34 void writeTitle(StringRef Str, raw_ostream &OS, char Kind = '-') {
35 OS << std::string(Str.size(), Kind) << "\n" << Str << "\n"
36 << std::string(Str.size(), Kind) << "\n";
39 void writeHeader(StringRef Str, raw_ostream &OS, char Kind = '-') {
40 OS << Str << "\n" << std::string(Str.size(), Kind) << "\n";
43 std::string escapeForRST(StringRef Str) {
45 Result.reserve(Str.size() + 4);
48 // We want special characters to be shown as their C escape codes.
49 case '\n': Result += "\\n"; break;
50 case '\t': Result += "\\t"; break;
51 // Underscore at the end of a line has a special meaning in rst.
52 case '_': Result += "\\_"; break;
59 void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
60 CodeGenDAGPatterns CDP(RK);
61 CodeGenTarget &Target = CDP.getTargetInfo();
62 unsigned VariantCount = Target.getAsmParserVariantCount();
65 std::string Title = Target.getName();
66 Title += " Instructions";
67 writeTitle(Title, OS);
70 for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
71 Record *Inst = II->TheDef;
73 // Don't print the target-independent instructions.
74 if (II->Namespace == "TargetOpcode")
77 // Heading (instruction name).
78 writeHeader(escapeForRST(Inst->getName()), OS, '=');
81 // Assembly string(s).
82 if (!II->AsmString.empty()) {
83 for (unsigned VarNum = 0; VarNum < VariantCount; ++VarNum) {
84 Record *AsmVariant = Target.getAsmParserVariant(VarNum);
85 OS << "Assembly string";
86 if (VariantCount != 1)
87 OS << " (" << AsmVariant->getValueAsString("Name") << ")";
88 std::string AsmString =
89 CodeGenInstruction::FlattenAsmStringVariants(II->AsmString, VarNum);
90 // We trim spaces at each end of the asm string because rst needs the
91 // formatting backticks to be next to a non-whitespace character.
92 OS << ": ``" << escapeForRST(StringRef(AsmString).trim(" "))
98 std::vector<const char *> FlagStrings;
99 #define xstr(s) str(s)
101 #define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
103 FLAG(isEHScopeReturn)
105 FLAG(isIndirectBranch)
116 //FLAG(mayLoad_Unset) // Deliberately omitted.
118 //FLAG(mayStore_Unset) // Deliberately omitted.
120 FLAG(isConvertibleToThreeAddress)
123 FLAG(isReMaterializable)
125 FLAG(usesCustomInserter)
126 FLAG(hasPostISelHook)
128 FLAG(isNotDuplicable)
130 //FLAG(hasSideEffects_Unset) // Deliberately omitted.
131 FLAG(isAsCheapAsAMove)
132 FLAG(hasExtraSrcRegAllocReq)
133 FLAG(hasExtraDefRegAllocReq)
137 FLAG(isExtractSubreg)
140 FLAG(hasNoSchedulingInfo)
141 FLAG(variadicOpsAreDefs)
142 if (!FlagStrings.empty()) {
145 for (auto FlagString : FlagStrings) {
148 OS << "``" << FlagString << "``";
155 for (unsigned i = 0; i < II->Operands.size(); ++i) {
156 bool IsDef = i < II->Operands.NumDefs;
157 auto Op = II->Operands[i];
159 if (Op.MINumOperands > 1) {
160 // This operand corresponds to multiple operands on the
161 // MachineInstruction, so print all of them, showing the types and
162 // names of both the compound operand and the basic operands it
164 for (unsigned SubOpIdx = 0; SubOpIdx < Op.MINumOperands; ++SubOpIdx) {
166 cast<DefInit>(Op.MIOperandInfo->getArg(SubOpIdx))->getDef();
167 StringRef SubOpName = Op.MIOperandInfo->getArgNameStr(SubOpIdx);
168 StringRef SubOpTypeName = SubRec->getName();
170 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName()
171 << "/" << SubOpTypeName << ":$" << Op.Name << ".";
172 // Not all sub-operands are named, make up a name for these.
173 if (SubOpName.empty())
174 OS << "anon" << SubOpIdx;
180 // The operand corresponds to only one MachineInstruction operand.
181 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName()
182 << ":$" << Op.Name << "``\n\n";
187 StringRef Constraints = Inst->getValueAsString("Constraints");
188 if (!Constraints.empty()) {
189 OS << "Constraints: ``" << Constraints << "``\n\n";
192 // Implicit definitions.
193 if (!II->ImplicitDefs.empty()) {
194 OS << "Implicit defs: ";
196 for (Record *Def : II->ImplicitDefs) {
199 OS << "``" << Def->getName() << "``";
206 if (!II->ImplicitUses.empty()) {
207 OS << "Implicit uses: ";
209 for (Record *Use : II->ImplicitUses) {
212 OS << "``" << Use->getName() << "``";
219 std::vector<Record *> Predicates =
220 II->TheDef->getValueAsListOfDefs("Predicates");
221 if (!Predicates.empty()) {
222 OS << "Predicates: ";
224 for (Record *P : Predicates) {
227 OS << "``" << P->getName() << "``";
235 } // end llvm namespace