1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenDAGPatterns.h"
16 #include "CodeGenInstruction.h"
17 #include "CodeGenSchedule.h"
18 #include "CodeGenTarget.h"
19 #include "SequenceToOffsetTable.h"
20 #include "TableGenBackends.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/Support/Casting.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/TableGen/Error.h"
26 #include "llvm/TableGen/Record.h"
27 #include "llvm/TableGen/TableGenBackend.h"
39 class InstrInfoEmitter {
40 RecordKeeper &Records;
41 CodeGenDAGPatterns CDP;
42 const CodeGenSchedModels &SchedModels;
45 InstrInfoEmitter(RecordKeeper &R):
46 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
48 // run - Output the instruction set description.
49 void run(raw_ostream &OS);
52 void emitEnums(raw_ostream &OS);
54 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
56 /// The keys of this map are maps which have OpName enum values as their keys
57 /// and instruction operand indices as their values. The values of this map
58 /// are lists of instruction names.
59 typedef std::map<std::map<unsigned, unsigned>,
60 std::vector<std::string>> OpNameMapTy;
61 typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
62 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
64 std::map<std::vector<Record*>, unsigned> &EL,
65 const OperandInfoMapTy &OpInfo,
67 void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
68 void initOperandMapData(
69 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
71 std::map<std::string, unsigned> &Operands,
72 OpNameMapTy &OperandMap);
73 void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
74 ArrayRef<const CodeGenInstruction*> NumberedInstructions);
76 // Operand information.
77 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
78 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
81 } // end anonymous namespace
83 static void PrintDefList(const std::vector<Record*> &Uses,
84 unsigned Num, raw_ostream &OS) {
85 OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
86 for (Record *U : Uses)
87 OS << getQualifiedName(U) << ", ";
91 //===----------------------------------------------------------------------===//
92 // Operand Info Emission.
93 //===----------------------------------------------------------------------===//
95 std::vector<std::string>
96 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
97 std::vector<std::string> Result;
99 for (auto &Op : Inst.Operands) {
100 // Handle aggregate operands and normal operands the same way by expanding
101 // either case into a list of operands for this op.
102 std::vector<CGIOperandList::OperandInfo> OperandList;
104 // This might be a multiple operand thing. Targets like X86 have
105 // registers in their multi-operand operands. It may also be an anonymous
106 // operand, which has a single operand, but no declared class for the
108 DagInit *MIOI = Op.MIOperandInfo;
110 if (!MIOI || MIOI->getNumArgs() == 0) {
111 // Single, anonymous, operand.
112 OperandList.push_back(Op);
114 for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
115 OperandList.push_back(Op);
117 auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
118 OperandList.back().Rec = OpR;
122 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
123 Record *OpR = OperandList[j].Rec;
126 if (OpR->isSubClassOf("RegisterOperand"))
127 OpR = OpR->getValueAsDef("RegClass");
128 if (OpR->isSubClassOf("RegisterClass"))
129 Res += getQualifiedName(OpR) + "RegClassID, ";
130 else if (OpR->isSubClassOf("PointerLikeRegClass"))
131 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
133 // -1 means the operand does not have a fixed register class.
136 // Fill in applicable flags.
139 // Ptr value whose register class is resolved via callback.
140 if (OpR->isSubClassOf("PointerLikeRegClass"))
141 Res += "|(1<<MCOI::LookupPtrRegClass)";
143 // Predicate operands. Check to see if the original unexpanded operand
144 // was of type PredicateOp.
145 if (Op.Rec->isSubClassOf("PredicateOp"))
146 Res += "|(1<<MCOI::Predicate)";
148 // Optional def operands. Check to see if the original unexpanded operand
149 // was of type OptionalDefOperand.
150 if (Op.Rec->isSubClassOf("OptionalDefOperand"))
151 Res += "|(1<<MCOI::OptionalDef)";
153 // Fill in operand type.
155 assert(!Op.OperandType.empty() && "Invalid operand type.");
156 Res += Op.OperandType;
158 // Fill in constraint info.
161 const CGIOperandList::ConstraintInfo &Constraint =
163 if (Constraint.isNone())
165 else if (Constraint.isEarlyClobber())
166 Res += "(1 << MCOI::EARLY_CLOBBER)";
168 assert(Constraint.isTied());
169 Res += "((" + utostr(Constraint.getTiedOperand()) +
170 " << 16) | (1 << MCOI::TIED_TO))";
173 Result.push_back(Res);
180 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
181 OperandInfoMapTy &OperandInfoIDs) {
182 // ID #0 is for no operand info.
183 unsigned OperandListNum = 0;
184 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
187 const CodeGenTarget &Target = CDP.getTargetInfo();
188 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
189 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
190 unsigned &N = OperandInfoIDs[OperandInfo];
191 if (N != 0) continue;
193 N = ++OperandListNum;
194 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
195 for (const std::string &Info : OperandInfo)
196 OS << "{ " << Info << " }, ";
201 /// Initialize data structures for generating operand name mappings.
203 /// \param Operands [out] A map used to generate the OpName enum with operand
204 /// names as its keys and operand enum values as its values.
205 /// \param OperandMap [out] A map for representing the operand name mappings for
206 /// each instructions. This is used to generate the OperandMap table as
207 /// well as the getNamedOperandIdx() function.
208 void InstrInfoEmitter::initOperandMapData(
209 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
211 std::map<std::string, unsigned> &Operands,
212 OpNameMapTy &OperandMap) {
213 unsigned NumOperands = 0;
214 for (const CodeGenInstruction *Inst : NumberedInstructions) {
215 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
217 std::map<unsigned, unsigned> OpList;
218 for (const auto &Info : Inst->Operands) {
219 StrUintMapIter I = Operands.find(Info.Name);
221 if (I == Operands.end()) {
222 I = Operands.insert(Operands.begin(),
223 std::pair<std::string, unsigned>(Info.Name, NumOperands++));
225 OpList[I->second] = Info.MIOperandNo;
227 OperandMap[OpList].push_back(Namespace.str() + "::" +
228 Inst->TheDef->getName().str());
232 /// Generate a table and function for looking up the indices of operands by
235 /// This code generates:
236 /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
237 /// for each operand name.
238 /// - A 2-dimensional table called OperandMap for mapping OpName enum values to
240 /// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
241 /// for looking up the operand index for an instruction, given a value from
243 void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
244 const CodeGenTarget &Target,
245 ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
246 StringRef Namespace = Target.getInstNamespace();
247 std::string OpNameNS = "OpName";
248 // Map of operand names to their enumeration value. This will be used to
249 // generate the OpName enum.
250 std::map<std::string, unsigned> Operands;
251 OpNameMapTy OperandMap;
253 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
255 OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
256 OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
257 OS << "namespace llvm {\n";
258 OS << "namespace " << Namespace << " {\n";
259 OS << "namespace " << OpNameNS << " {\n";
261 for (const auto &Op : Operands)
262 OS << " " << Op.first << " = " << Op.second << ",\n";
264 OS << "OPERAND_LAST";
266 OS << "} // end namespace OpName\n";
267 OS << "} // end namespace " << Namespace << "\n";
268 OS << "} // end namespace llvm\n";
269 OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
271 OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
272 OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
273 OS << "namespace llvm {\n";
274 OS << "namespace " << Namespace << " {\n";
275 OS << "LLVM_READONLY\n";
276 OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
277 if (!Operands.empty()) {
278 OS << " static const int16_t OperandMap [][" << Operands.size()
280 for (const auto &Entry : OperandMap) {
281 const std::map<unsigned, unsigned> &OpList = Entry.first;
284 // Emit a row of the OperandMap table
285 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
286 OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
292 OS << " switch(Opcode) {\n";
293 unsigned TableIndex = 0;
294 for (const auto &Entry : OperandMap) {
295 for (const std::string &Name : Entry.second)
296 OS << " case " << Name << ":\n";
298 OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
300 OS << " default: return -1;\n";
303 // There are no operands, so no need to emit anything
304 OS << " return -1;\n";
307 OS << "} // end namespace " << Namespace << "\n";
308 OS << "} // end namespace llvm\n";
309 OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
312 /// Generate an enum for all the operand types for this target, under the
313 /// llvm::TargetNamespace::OpTypes namespace.
314 /// Operand types are all definitions derived of the Operand Target.td class.
315 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
316 const CodeGenTarget &Target) {
318 StringRef Namespace = Target.getInstNamespace();
319 std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
321 OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
322 OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
323 OS << "namespace llvm {\n";
324 OS << "namespace " << Namespace << " {\n";
325 OS << "namespace OpTypes {\n";
326 OS << "enum OperandType {\n";
328 unsigned EnumVal = 0;
329 for (const Record *Op : Operands) {
330 if (!Op->isAnonymous())
331 OS << " " << Op->getName() << " = " << EnumVal << ",\n";
335 OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
336 OS << "} // end namespace OpTypes\n";
337 OS << "} // end namespace " << Namespace << "\n";
338 OS << "} // end namespace llvm\n";
339 OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
342 //===----------------------------------------------------------------------===//
344 //===----------------------------------------------------------------------===//
346 // run - Emit the main instruction description records for the target...
347 void InstrInfoEmitter::run(raw_ostream &OS) {
348 emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
351 OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
352 OS << "#undef GET_INSTRINFO_MC_DESC\n";
354 OS << "namespace llvm {\n\n";
356 CodeGenTarget &Target = CDP.getTargetInfo();
357 const std::string &TargetName = Target.getName();
358 Record *InstrInfo = Target.getInstructionSet();
360 // Keep track of all of the def lists we have emitted already.
361 std::map<std::vector<Record*>, unsigned> EmittedLists;
362 unsigned ListNumber = 0;
364 // Emit all of the instruction's implicit uses and defs.
365 for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
366 Record *Inst = II->TheDef;
367 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
369 unsigned &IL = EmittedLists[Uses];
370 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
372 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
374 unsigned &IL = EmittedLists[Defs];
375 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
379 OperandInfoMapTy OperandInfoIDs;
381 // Emit all of the operand info records.
382 EmitOperandInfo(OS, OperandInfoIDs);
384 // Emit all of the MCInstrDesc records in their ENUM ordering.
386 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
387 ArrayRef<const CodeGenInstruction*> NumberedInstructions =
388 Target.getInstructionsByEnumValue();
390 SequenceToOffsetTable<std::string> InstrNames;
392 for (const CodeGenInstruction *Inst : NumberedInstructions) {
393 // Keep a list of the instruction names.
394 InstrNames.add(Inst->TheDef->getName());
395 // Emit the record into the table.
396 emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
400 // Emit the array of instruction names.
402 OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
403 InstrNames.emit(OS, printChar);
406 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
408 for (const CodeGenInstruction *Inst : NumberedInstructions) {
409 // Newline every eight entries.
412 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
418 // MCInstrInfo initialization routine.
419 OS << "static inline void Init" << TargetName
420 << "MCInstrInfo(MCInstrInfo *II) {\n";
421 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
422 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
423 << NumberedInstructions.size() << ");\n}\n\n";
425 OS << "} // end llvm namespace\n";
427 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
429 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
430 OS << "#ifdef GET_INSTRINFO_HEADER\n";
431 OS << "#undef GET_INSTRINFO_HEADER\n";
433 std::string ClassName = TargetName + "GenInstrInfo";
434 OS << "namespace llvm {\n";
435 OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
436 << " explicit " << ClassName
437 << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
438 << " ~" << ClassName << "() override = default;\n"
440 OS << "} // end llvm namespace\n";
442 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
444 OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
445 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
447 OS << "namespace llvm {\n";
448 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
449 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
450 OS << "extern const char " << TargetName << "InstrNameData[];\n";
451 OS << ClassName << "::" << ClassName
452 << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
453 << " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
454 << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
455 << "InstrNameIndices, " << TargetName << "InstrNameData, "
456 << NumberedInstructions.size() << ");\n}\n";
457 OS << "} // end llvm namespace\n";
459 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
461 emitOperandNameMappings(OS, Target, NumberedInstructions);
463 emitOperandTypesEnum(OS, Target);
466 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
468 std::map<std::vector<Record*>, unsigned> &EmittedLists,
469 const OperandInfoMapTy &OpInfo,
472 if (!Inst.Operands.empty())
473 // Each logical operand can be multiple MI operands.
474 MinOperands = Inst.Operands.back().MIOperandNo +
475 Inst.Operands.back().MINumOperands;
478 OS << Num << ",\t" << MinOperands << ",\t"
479 << Inst.Operands.NumDefs << ",\t"
480 << Inst.TheDef->getValueAsInt("Size") << ",\t"
481 << SchedModels.getSchedClassIdx(Inst) << ",\t0";
483 // Emit all of the target independent flags...
484 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
485 if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
486 if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
487 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
488 if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
489 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
490 if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
491 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
492 if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
493 if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
494 if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
495 if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
496 if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
497 if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
498 if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
499 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
500 if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
501 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
502 if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
503 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
504 if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
505 if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
506 if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
507 if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
508 if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
509 if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
510 if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
511 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
512 if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
513 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
514 if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
515 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
516 if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
518 // Emit all of the target-specific flags...
519 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
521 PrintFatalError("no TSFlags?");
523 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
524 if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
525 Value |= uint64_t(Bit->getValue()) << i;
527 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
533 // Emit the implicit uses and defs lists...
534 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
538 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
540 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
544 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
546 // Emit the operand info.
547 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
548 if (OperandInfo.empty())
551 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
553 CodeGenTarget &Target = CDP.getTargetInfo();
554 if (Inst.HasComplexDeprecationPredicate)
555 // Emit a function pointer to the complex predicate method.
557 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
558 else if (!Inst.DeprecatedReason.empty())
559 // Emit the Subtarget feature.
560 OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
563 // Instruction isn't deprecated.
564 OS << ", -1 ,nullptr";
566 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
569 // emitEnums - Print out enum values for all of the instructions.
570 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
571 OS << "#ifdef GET_INSTRINFO_ENUM\n";
572 OS << "#undef GET_INSTRINFO_ENUM\n";
574 OS << "namespace llvm {\n\n";
576 CodeGenTarget Target(Records);
578 // We must emit the PHI opcode first...
579 StringRef Namespace = Target.getInstNamespace();
581 if (Namespace.empty())
582 PrintFatalError("No instructions defined!");
584 OS << "namespace " << Namespace << " {\n";
587 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
588 OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
589 OS << " INSTRUCTION_LIST_END = " << Num << "\n";
591 OS << "} // end " << Namespace << " namespace\n";
592 OS << "} // end llvm namespace\n";
593 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
595 OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
596 OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
597 OS << "namespace llvm {\n\n";
598 OS << "namespace " << Namespace << " {\n";
599 OS << "namespace Sched {\n";
602 for (const auto &Class : SchedModels.explicit_classes())
603 OS << " " << Class.Name << "\t= " << Num++ << ",\n";
604 OS << " SCHED_LIST_END = " << Num << "\n";
606 OS << "} // end Sched namespace\n";
607 OS << "} // end " << Namespace << " namespace\n";
608 OS << "} // end llvm namespace\n";
610 OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
615 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
616 InstrInfoEmitter(RK).run(OS);
617 EmitMapTable(RK, OS);
620 } // end llvm namespace