1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/SparseBitVector.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/CodeGen/MachineValueType.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/Format.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/TableGen/Error.h"
32 #include "llvm/TableGen/Record.h"
33 #include "llvm/TableGen/SetTheory.h"
34 #include "llvm/TableGen/TableGenBackend.h"
49 class RegisterInfoEmitter {
50 RecordKeeper &Records;
53 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
55 // runEnums - Print out enum values for all of the registers.
56 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
58 // runMCDesc - Print out MC register descriptions.
59 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
61 // runTargetHeader - Emit a header fragment for the register info emitter.
62 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
63 CodeGenRegBank &Bank);
65 // runTargetDesc - Output the target register and register file descriptions.
66 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
67 CodeGenRegBank &Bank);
69 // run - Output the register file description.
70 void run(raw_ostream &o);
73 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
75 void EmitRegMappingTables(raw_ostream &o,
76 const std::deque<CodeGenRegister> &Regs,
78 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79 const std::string &ClassName);
80 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81 const std::string &ClassName);
82 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
83 const std::string &ClassName);
86 } // end anonymous namespace
88 // runEnums - Print out enum values for all of the registers.
89 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
90 CodeGenTarget &Target, CodeGenRegBank &Bank) {
91 const auto &Registers = Bank.getRegisters();
93 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
94 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
96 std::string Namespace =
97 Registers.front().TheDef->getValueAsString("Namespace");
99 emitSourceFileHeader("Target Register Enum Values", OS);
101 OS << "\n#ifdef GET_REGINFO_ENUM\n";
102 OS << "#undef GET_REGINFO_ENUM\n\n";
104 OS << "namespace llvm {\n\n";
106 OS << "class MCRegisterClass;\n"
107 << "extern const MCRegisterClass " << Target.getName()
108 << "MCRegisterClasses[];\n\n";
110 if (!Namespace.empty())
111 OS << "namespace " << Namespace << " {\n";
112 OS << "enum {\n NoRegister,\n";
114 for (const auto &Reg : Registers)
115 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
116 assert(Registers.size() == Registers.back().EnumValue &&
117 "Register enum value mismatch!");
118 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
120 if (!Namespace.empty())
121 OS << "} // end namespace " << Namespace << "\n";
123 const auto &RegisterClasses = Bank.getRegClasses();
124 if (!RegisterClasses.empty()) {
126 // RegisterClass enums are stored as uint16_t in the tables.
127 assert(RegisterClasses.size() <= 0xffff &&
128 "Too many register classes to fit in tables");
130 OS << "\n// Register classes\n\n";
131 if (!Namespace.empty())
132 OS << "namespace " << Namespace << " {\n";
134 for (const auto &RC : RegisterClasses)
135 OS << " " << RC.getName() << "RegClassID"
136 << " = " << RC.EnumValue << ",\n";
138 if (!Namespace.empty())
139 OS << "} // end namespace " << Namespace << "\n\n";
142 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
143 // If the only definition is the default NoRegAltName, we don't need to
145 if (RegAltNameIndices.size() > 1) {
146 OS << "\n// Register alternate name indices\n\n";
147 if (!Namespace.empty())
148 OS << "namespace " << Namespace << " {\n";
150 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
151 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
152 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
154 if (!Namespace.empty())
155 OS << "} // end namespace " << Namespace << "\n\n";
158 auto &SubRegIndices = Bank.getSubRegIndices();
159 if (!SubRegIndices.empty()) {
160 OS << "\n// Subregister indices\n\n";
161 std::string Namespace = SubRegIndices.front().getNamespace();
162 if (!Namespace.empty())
163 OS << "namespace " << Namespace << " {\n";
164 OS << "enum {\n NoSubRegister,\n";
166 for (const auto &Idx : SubRegIndices)
167 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
168 OS << " NUM_TARGET_SUBREGS\n};\n";
169 if (!Namespace.empty())
170 OS << "} // end namespace " << Namespace << "\n\n";
173 OS << "} // end namespace llvm\n\n";
174 OS << "#endif // GET_REGINFO_ENUM\n\n";
177 static void printInt(raw_ostream &OS, int Val) {
181 void RegisterInfoEmitter::
182 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
183 const std::string &ClassName) {
184 unsigned NumRCs = RegBank.getRegClasses().size();
185 unsigned NumSets = RegBank.getNumRegPressureSets();
187 OS << "/// Get the weight in units of pressure for this register class.\n"
188 << "const RegClassWeight &" << ClassName << "::\n"
189 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
190 << " static const RegClassWeight RCWeightTable[] = {\n";
191 for (const auto &RC : RegBank.getRegClasses()) {
192 const CodeGenRegister::Vec &Regs = RC.getMembers();
196 std::vector<unsigned> RegUnits;
197 RC.buildRegUnitSet(RegUnits);
198 OS << " {" << (*Regs.begin())->getWeight(RegBank)
199 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
201 OS << "}, \t// " << RC.getName() << "\n";
204 << " return RCWeightTable[RC->getID()];\n"
207 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
208 // bother generating a table.
209 bool RegUnitsHaveUnitWeight = true;
210 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
211 UnitIdx < UnitEnd; ++UnitIdx) {
212 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
213 RegUnitsHaveUnitWeight = false;
215 OS << "/// Get the weight in units of pressure for this register unit.\n"
216 << "unsigned " << ClassName << "::\n"
217 << "getRegUnitWeight(unsigned RegUnit) const {\n"
218 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
219 << " && \"invalid register unit\");\n";
220 if (!RegUnitsHaveUnitWeight) {
221 OS << " static const uint8_t RUWeightTable[] = {\n ";
222 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
223 UnitIdx < UnitEnd; ++UnitIdx) {
224 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
225 assert(RU.Weight < 256 && "RegUnit too heavy");
226 OS << RU.Weight << ", ";
229 << " return RUWeightTable[RegUnit];\n";
232 OS << " // All register units have unit weight.\n"
238 << "// Get the number of dimensions of register pressure.\n"
239 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
240 << " return " << NumSets << ";\n}\n\n";
242 OS << "// Get the name of this register unit pressure set.\n"
243 << "const char *" << ClassName << "::\n"
244 << "getRegPressureSetName(unsigned Idx) const {\n"
245 << " static const char *const PressureNameTable[] = {\n";
246 unsigned MaxRegUnitWeight = 0;
247 for (unsigned i = 0; i < NumSets; ++i ) {
248 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
249 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
250 OS << " \"" << RegUnits.Name << "\",\n";
253 << " return PressureNameTable[Idx];\n"
256 OS << "// Get the register unit pressure limit for this dimension.\n"
257 << "// This limit must be adjusted dynamically for reserved registers.\n"
258 << "unsigned " << ClassName << "::\n"
259 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const "
261 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32)
262 << " PressureLimitTable[] = {\n";
263 for (unsigned i = 0; i < NumSets; ++i ) {
264 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
265 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
266 << RegUnits.Name << "\n";
269 << " return PressureLimitTable[Idx];\n"
272 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
274 // This table may be larger than NumRCs if some register units needed a list
275 // of unit sets that did not correspond to a register class.
276 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
277 std::vector<std::vector<int>> PSets(NumRCUnitSets);
279 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
280 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
281 PSets[i].reserve(PSetIDs.size());
282 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
283 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
284 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
286 std::sort(PSets[i].begin(), PSets[i].end());
287 PSetsSeqs.add(PSets[i]);
292 OS << "/// Table of pressure sets per register class or unit.\n"
293 << "static const int RCSetsTable[] = {\n";
294 PSetsSeqs.emit(OS, printInt, "-1");
297 OS << "/// Get the dimensions of register pressure impacted by this "
298 << "register class.\n"
299 << "/// Returns a -1 terminated array of pressure set IDs\n"
300 << "const int* " << ClassName << "::\n"
301 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
302 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
303 << " RCSetStartTable[] = {\n ";
304 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
305 OS << PSetsSeqs.get(PSets[i]) << ",";
308 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
311 OS << "/// Get the dimensions of register pressure impacted by this "
312 << "register unit.\n"
313 << "/// Returns a -1 terminated array of pressure set IDs\n"
314 << "const int* " << ClassName << "::\n"
315 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
316 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
317 << " && \"invalid register unit\");\n";
318 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
319 << " RUSetStartTable[] = {\n ";
320 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
321 UnitIdx < UnitEnd; ++UnitIdx) {
322 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
326 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
330 void RegisterInfoEmitter::EmitRegMappingTables(
331 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
332 // Collect all information about dwarf register numbers
333 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
334 DwarfRegNumsMapTy DwarfRegNums;
336 // First, just pull all provided information to the map
337 unsigned maxLength = 0;
338 for (auto &RE : Regs) {
339 Record *Reg = RE.TheDef;
340 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
341 maxLength = std::max((size_t)maxLength, RegNums.size());
342 if (DwarfRegNums.count(Reg))
343 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
344 getQualifiedName(Reg) + "specified multiple times");
345 DwarfRegNums[Reg] = RegNums;
351 // Now we know maximal length of number list. Append -1's, where needed
352 for (DwarfRegNumsMapTy::iterator
353 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
354 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
355 I->second.push_back(-1);
357 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
359 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
361 // Emit reverse information about the dwarf register numbers.
362 for (unsigned j = 0; j < 2; ++j) {
363 for (unsigned i = 0, e = maxLength; i != e; ++i) {
364 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
365 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
366 OS << i << "Dwarf2L[]";
371 // Store the mapping sorted by the LLVM reg num so lookup can be done
372 // with a binary search.
373 std::map<uint64_t, Record*> Dwarf2LMap;
374 for (DwarfRegNumsMapTy::iterator
375 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
376 int DwarfRegNo = I->second[i];
379 Dwarf2LMap[DwarfRegNo] = I->first;
382 for (std::map<uint64_t, Record*>::iterator
383 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
384 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
392 // We have to store the size in a const global, it's used in multiple
394 OS << "extern const unsigned " << Namespace
395 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
397 OS << " = array_lengthof(" << Namespace
398 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
405 for (auto &RE : Regs) {
406 Record *Reg = RE.TheDef;
407 const RecordVal *V = Reg->getValue("DwarfAlias");
408 if (!V || !V->getValue())
411 DefInit *DI = cast<DefInit>(V->getValue());
412 Record *Alias = DI->getDef();
413 DwarfRegNums[Reg] = DwarfRegNums[Alias];
416 // Emit information about the dwarf register numbers.
417 for (unsigned j = 0; j < 2; ++j) {
418 for (unsigned i = 0, e = maxLength; i != e; ++i) {
419 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
420 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
421 OS << i << "L2Dwarf[]";
424 // Store the mapping sorted by the Dwarf reg num so lookup can be done
425 // with a binary search.
426 for (DwarfRegNumsMapTy::iterator
427 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
428 int RegNo = I->second[i];
429 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
432 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
440 // We have to store the size in a const global, it's used in multiple
442 OS << "extern const unsigned " << Namespace
443 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
445 OS << " = array_lengthof(" << Namespace
446 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
453 void RegisterInfoEmitter::EmitRegMapping(
454 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
455 // Emit the initializer so the tables from EmitRegMappingTables get wired up
456 // to the MCRegisterInfo object.
457 unsigned maxLength = 0;
458 for (auto &RE : Regs) {
459 Record *Reg = RE.TheDef;
460 maxLength = std::max((size_t)maxLength,
461 Reg->getValueAsListOfInts("DwarfNumbers").size());
467 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
469 // Emit reverse information about the dwarf register numbers.
470 for (unsigned j = 0; j < 2; ++j) {
473 OS << "DwarfFlavour";
478 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
480 for (unsigned i = 0, e = maxLength; i != e; ++i) {
481 OS << " case " << i << ":\n";
486 raw_string_ostream(Tmp) << Namespace
487 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
489 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
500 // Emit information about the dwarf register numbers.
501 for (unsigned j = 0; j < 2; ++j) {
504 OS << "DwarfFlavour";
509 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
511 for (unsigned i = 0, e = maxLength; i != e; ++i) {
512 OS << " case " << i << ":\n";
517 raw_string_ostream(Tmp) << Namespace
518 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
520 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
532 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
533 // Width is the number of bits per hex number.
534 static void printBitVectorAsHex(raw_ostream &OS,
535 const BitVector &Bits,
537 assert(Width <= 32 && "Width too large");
538 unsigned Digits = (Width + 3) / 4;
539 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
541 for (unsigned j = 0; j != Width && i + j != e; ++j)
542 Value |= Bits.test(i + j) << j;
543 OS << format("0x%0*x, ", Digits, Value);
547 // Helper to emit a set of bits into a constant byte array.
548 class BitVectorEmitter {
551 void add(unsigned v) {
552 if (v >= Values.size())
553 Values.resize(((v/8)+1)*8); // Round up to the next byte.
557 void print(raw_ostream &OS) {
558 printBitVectorAsHex(OS, Values, 8);
562 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
563 OS << getEnumName(VT);
566 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
567 OS << Idx->EnumValue;
570 // Differentially encoded register and regunit lists allow for better
571 // compression on regular register banks. The sequence is computed from the
572 // differential list as:
575 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
577 // The initial value depends on the specific list. The list is terminated by a
578 // 0 differential which means we can't encode repeated elements.
580 typedef SmallVector<uint16_t, 4> DiffVec;
581 typedef SmallVector<LaneBitmask, 4> MaskVec;
583 // Differentially encode a sequence of numbers into V. The starting value and
584 // terminating 0 are not added to V, so it will have the same size as List.
586 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) {
587 assert(V.empty() && "Clear DiffVec before diffEncode.");
588 uint16_t Val = uint16_t(InitVal);
590 for (uint16_t Cur : List) {
591 V.push_back(Cur - Val);
597 template<typename Iter>
599 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
600 assert(V.empty() && "Clear DiffVec before diffEncode.");
601 uint16_t Val = uint16_t(InitVal);
602 for (Iter I = Begin; I != End; ++I) {
603 uint16_t Cur = (*I)->EnumValue;
604 V.push_back(Cur - Val);
610 static void printDiff16(raw_ostream &OS, uint16_t Val) {
614 static void printMask(raw_ostream &OS, LaneBitmask Val) {
615 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')';
618 // Try to combine Idx's compose map into Vec if it is compatible.
619 // Return false if it's not possible.
620 static bool combine(const CodeGenSubRegIndex *Idx,
621 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
622 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
623 for (const auto &I : Map) {
624 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
625 if (Entry && Entry != I.second)
629 // All entries are compatible. Make it so.
630 for (const auto &I : Map) {
631 auto *&Entry = Vec[I.first->EnumValue - 1];
632 assert((!Entry || Entry == I.second) &&
633 "Expected EnumValue to be unique");
640 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
641 CodeGenRegBank &RegBank,
642 const std::string &ClName) {
643 const auto &SubRegIndices = RegBank.getSubRegIndices();
644 OS << "unsigned " << ClName
645 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
647 // Many sub-register indexes are composition-compatible, meaning that
649 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
651 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
652 // The illegal entries can be use as wildcards to compress the table further.
654 // Map each Sub-register index to a compatible table row.
655 SmallVector<unsigned, 4> RowMap;
656 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
658 auto SubRegIndicesSize =
659 std::distance(SubRegIndices.begin(), SubRegIndices.end());
660 for (const auto &Idx : SubRegIndices) {
661 unsigned Found = ~0u;
662 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
663 if (combine(&Idx, Rows[r])) {
670 Rows.resize(Found + 1);
671 Rows.back().resize(SubRegIndicesSize);
672 combine(&Idx, Rows.back());
674 RowMap.push_back(Found);
677 // Output the row map if there is multiple rows.
678 if (Rows.size() > 1) {
679 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32)
680 << " RowMap[" << SubRegIndicesSize << "] = {\n ";
681 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
682 OS << RowMap[i] << ", ";
687 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32)
688 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
689 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
691 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
693 OS << Rows[r][i]->EnumValue << ", ";
700 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
701 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
703 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
705 OS << " return Rows[0][IdxB];\n";
710 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
711 CodeGenRegBank &RegBank,
712 const std::string &ClName) {
713 // See the comments in computeSubRegLaneMasks() for our goal here.
714 const auto &SubRegIndices = RegBank.getSubRegIndices();
716 // Create a list of Mask+Rotate operations, with equivalent entries merged.
717 SmallVector<unsigned, 4> SubReg2SequenceIndexMap;
718 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;
719 for (const auto &Idx : SubRegIndices) {
720 const SmallVector<MaskRolPair, 1> &IdxSequence
721 = Idx.CompositionLaneMaskTransform;
723 unsigned Found = ~0u;
726 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {
727 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
728 NextSIdx = SIdx + Sequence.size() + 1;
729 if (Sequence == IdxSequence) {
735 Sequences.push_back(IdxSequence);
738 SubReg2SequenceIndexMap.push_back(Found);
741 OS << " struct MaskRolOp {\n"
742 " LaneBitmask Mask;\n"
743 " uint8_t RotateLeft;\n"
745 " static const MaskRolOp LaneMaskComposeSequences[] = {\n";
747 for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
749 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
750 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
751 const MaskRolPair &P = Sequence[p];
752 printMask(OS << "{ ", P.Mask);
753 OS << format(", %2u }, ", P.RotateLeft);
755 OS << "{ LaneBitmask::getNone(), 0 }";
758 OS << " // Sequence " << Idx << "\n";
759 Idx += Sequence.size() + 1;
762 " static const MaskRolOp *const CompositeSequences[] = {\n";
763 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
765 unsigned Idx = SubReg2SequenceIndexMap[i];
766 OS << format("&LaneMaskComposeSequences[%u]", Idx);
769 OS << " // to " << SubRegIndices[i].getName() << "\n";
773 OS << "LaneBitmask " << ClName
774 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
776 " --IdxA; assert(IdxA < " << SubRegIndices.size()
777 << " && \"Subregister index out of bounds\");\n"
778 " LaneBitmask Result;\n"
779 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
780 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n"
781 " if (unsigned S = Ops->RotateLeft)\n"
782 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n"
784 " Result |= LaneBitmask(M);\n"
789 OS << "LaneBitmask " << ClName
790 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "
791 " LaneBitmask LaneMask) const {\n"
792 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
793 " --IdxA; assert(IdxA < " << SubRegIndices.size()
794 << " && \"Subregister index out of bounds\");\n"
795 " LaneBitmask Result;\n"
796 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
797 " LaneBitmask::Type M = LaneMask.getAsInteger();\n"
798 " if (unsigned S = Ops->RotateLeft)\n"
799 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n"
801 " Result |= LaneBitmask(M);\n"
808 // runMCDesc - Print out MC register descriptions.
811 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
812 CodeGenRegBank &RegBank) {
813 emitSourceFileHeader("MC Register Information", OS);
815 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
816 OS << "#undef GET_REGINFO_MC_DESC\n\n";
818 const auto &Regs = RegBank.getRegisters();
820 auto &SubRegIndices = RegBank.getSubRegIndices();
821 // The lists of sub-registers and super-registers go in the same array. That
822 // allows us to share suffixes.
823 typedef std::vector<const CodeGenRegister*> RegVec;
825 // Differentially encoded lists.
826 SequenceToOffsetTable<DiffVec> DiffSeqs;
827 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
828 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
829 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
830 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
832 // List of lane masks accompanying register unit sequences.
833 SequenceToOffsetTable<MaskVec> LaneMaskSeqs;
834 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
836 // Keep track of sub-register names as well. These are not differentially
838 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
839 SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
840 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
842 SequenceToOffsetTable<std::string> RegStrings;
844 // Precompute register lists for the SequenceToOffsetTable.
846 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
847 const auto &Reg = *I;
848 RegStrings.add(Reg.getName());
850 // Compute the ordered sub-register list.
851 SetVector<const CodeGenRegister*> SR;
852 Reg.addSubRegsPreOrder(SR, RegBank);
853 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
854 DiffSeqs.add(SubRegLists[i]);
856 // Compute the corresponding sub-register indexes.
857 SubRegIdxVec &SRIs = SubRegIdxLists[i];
858 for (unsigned j = 0, je = SR.size(); j != je; ++j)
859 SRIs.push_back(Reg.getSubRegIndex(SR[j]));
860 SubRegIdxSeqs.add(SRIs);
862 // Super-registers are already computed.
863 const RegVec &SuperRegList = Reg.getSuperRegs();
864 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
866 DiffSeqs.add(SuperRegLists[i]);
868 // Differentially encode the register unit list, seeded by register number.
869 // First compute a scale factor that allows more diff-lists to be reused:
874 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
875 // value for the differential decoder is the register number multiplied by
878 // Check the neighboring registers for arithmetic progressions.
879 unsigned ScaleA = ~0u, ScaleB = ~0u;
880 SparseBitVector<> RUs = Reg.getNativeRegUnits();
881 if (I != Regs.begin() &&
882 std::prev(I)->getNativeRegUnits().count() == RUs.count())
883 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin();
884 if (std::next(I) != Regs.end() &&
885 std::next(I)->getNativeRegUnits().count() == RUs.count())
886 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin();
887 unsigned Scale = std::min(ScaleB, ScaleA);
888 // Default the scale to 0 if it can't be encoded in 4 bits.
891 RegUnitInitScale[i] = Scale;
892 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
894 const auto &RUMasks = Reg.getRegUnitLaneMasks();
895 MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
896 assert(LaneMaskVec.empty());
897 LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
898 // Terminator mask should not be used inside of the list.
900 for (LaneBitmask M : LaneMaskVec) {
901 assert(!M.all() && "terminator mask should not be part of the list");
904 LaneMaskSeqs.add(LaneMaskVec);
907 // Compute the final layout of the sequence table.
909 LaneMaskSeqs.layout();
910 SubRegIdxSeqs.layout();
912 OS << "namespace llvm {\n\n";
914 const std::string &TargetName = Target.getName();
916 // Emit the shared table of differential lists.
917 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
918 DiffSeqs.emit(OS, printDiff16);
921 // Emit the shared table of regunit lane mask sequences.
922 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
923 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()");
926 // Emit the table of sub-register indexes.
927 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
928 SubRegIdxSeqs.emit(OS, printSubRegIndex);
931 // Emit the table of sub-register index sizes.
932 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
933 << TargetName << "SubRegIdxRanges[] = {\n";
934 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
935 for (const auto &Idx : SubRegIndices) {
936 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
937 << Idx.getName() << "\n";
941 // Emit the string table.
943 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
944 RegStrings.emit(OS, printChar);
947 OS << "extern const MCRegisterDesc " << TargetName
948 << "RegDesc[] = { // Descriptors\n";
949 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
951 // Emit the register descriptors now.
953 for (const auto &Reg : Regs) {
954 OS << " { " << RegStrings.get(Reg.getName()) << ", "
955 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
956 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
957 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", "
958 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n";
961 OS << "};\n\n"; // End of register descriptors...
963 // Emit the table of register unit roots. Each regunit has one or two root
965 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
966 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
967 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
968 assert(!Roots.empty() && "All regunits must have a root register.");
969 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
970 OS << " { " << getQualifiedName(Roots.front()->TheDef);
971 for (unsigned r = 1; r != Roots.size(); ++r)
972 OS << ", " << getQualifiedName(Roots[r]->TheDef);
977 const auto &RegisterClasses = RegBank.getRegClasses();
979 // Loop over all of the register classes... emitting each one.
980 OS << "namespace { // Register classes...\n";
982 SequenceToOffsetTable<std::string> RegClassStrings;
984 // Emit the register enum value arrays for each RegisterClass
985 for (const auto &RC : RegisterClasses) {
986 ArrayRef<Record*> Order = RC.getOrder();
988 // Give the register class a legal C name if it's anonymous.
989 const std::string &Name = RC.getName();
991 RegClassStrings.add(Name);
993 // Emit the register list now.
994 OS << " // " << Name << " Register Class...\n"
995 << " const MCPhysReg " << Name
997 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
998 Record *Reg = Order[i];
999 OS << getQualifiedName(Reg) << ", ";
1003 OS << " // " << Name << " Bit set.\n"
1004 << " const uint8_t " << Name
1006 BitVectorEmitter BVE;
1007 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
1008 Record *Reg = Order[i];
1009 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1015 OS << "} // end anonymous namespace\n\n";
1017 RegClassStrings.layout();
1018 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
1019 RegClassStrings.emit(OS, printChar);
1022 OS << "extern const MCRegisterClass " << TargetName
1023 << "MCRegisterClasses[] = {\n";
1025 for (const auto &RC : RegisterClasses) {
1026 assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
1027 // Register size and spill size will become independent, but are not at
1028 // the moment. For now use SpillSize as the register size.
1029 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
1030 << RegClassStrings.get(RC.getName()) << ", "
1031 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
1032 << RC.getQualifiedName() + "RegClassID" << ", "
1033 << RC.SpillSize/8 << ", "
1034 << RC.CopyCost << ", "
1035 << ( RC.Allocatable ? "true" : "false" ) << " },\n";
1040 EmitRegMappingTables(OS, Regs, false);
1042 // Emit Reg encoding table
1043 OS << "extern const uint16_t " << TargetName;
1044 OS << "RegEncodingTable[] = {\n";
1045 // Add entry for NoRegister
1047 for (const auto &RE : Regs) {
1048 Record *Reg = RE.TheDef;
1049 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
1051 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
1052 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
1053 Value |= (uint64_t)B->getValue() << b;
1055 OS << " " << Value << ",\n";
1057 OS << "};\n"; // End of HW encoding table
1059 // MCRegisterInfo initialization routine.
1060 OS << "static inline void Init" << TargetName
1061 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
1062 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
1064 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
1065 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1066 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
1067 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1068 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
1069 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
1070 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
1071 << TargetName << "SubRegIdxRanges, " << TargetName
1072 << "RegEncodingTable);\n\n";
1074 EmitRegMapping(OS, Regs, false);
1078 OS << "} // end namespace llvm\n\n";
1079 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
1083 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
1084 CodeGenRegBank &RegBank) {
1085 emitSourceFileHeader("Register Information Header Fragment", OS);
1087 OS << "\n#ifdef GET_REGINFO_HEADER\n";
1088 OS << "#undef GET_REGINFO_HEADER\n\n";
1090 const std::string &TargetName = Target.getName();
1091 std::string ClassName = TargetName + "GenRegisterInfo";
1093 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
1095 OS << "namespace llvm {\n\n";
1097 OS << "class " << TargetName << "FrameLowering;\n\n";
1099 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
1100 << " explicit " << ClassName
1101 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n";
1102 if (!RegBank.getSubRegIndices().empty()) {
1103 OS << " unsigned composeSubRegIndicesImpl"
1104 << "(unsigned, unsigned) const override;\n"
1105 << " LaneBitmask composeSubRegIndexLaneMaskImpl"
1106 << "(unsigned, LaneBitmask) const override;\n"
1107 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
1108 << "(unsigned, LaneBitmask) const override;\n"
1109 << " const TargetRegisterClass *getSubClassWithSubReg"
1110 << "(const TargetRegisterClass*, unsigned) const override;\n";
1112 OS << " const RegClassWeight &getRegClassWeight("
1113 << "const TargetRegisterClass *RC) const override;\n"
1114 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
1115 << " unsigned getNumRegPressureSets() const override;\n"
1116 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
1117 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
1118 "Idx) const override;\n"
1119 << " const int *getRegClassPressureSets("
1120 << "const TargetRegisterClass *RC) const override;\n"
1121 << " const int *getRegUnitPressureSets("
1122 << "unsigned RegUnit) const override;\n"
1123 << " ArrayRef<const char *> getRegMaskNames() const override;\n"
1124 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n"
1125 << " /// Devirtualized TargetFrameLowering.\n"
1126 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n"
1127 << " const MachineFunction &MF);\n"
1130 const auto &RegisterClasses = RegBank.getRegClasses();
1132 if (!RegisterClasses.empty()) {
1133 OS << "namespace " << RegisterClasses.front().Namespace
1134 << " { // Register classes\n";
1136 for (const auto &RC : RegisterClasses) {
1137 const std::string &Name = RC.getName();
1139 // Output the extern for the instance.
1140 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1142 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
1144 OS << "} // end namespace llvm\n\n";
1145 OS << "#endif // GET_REGINFO_HEADER\n\n";
1149 // runTargetDesc - Output the target register and register file descriptions.
1152 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1153 CodeGenRegBank &RegBank){
1154 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1156 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1157 OS << "#undef GET_REGINFO_TARGET_DESC\n\n";
1159 OS << "namespace llvm {\n\n";
1161 // Get access to MCRegisterClass data.
1162 OS << "extern const MCRegisterClass " << Target.getName()
1163 << "MCRegisterClasses[];\n";
1165 // Start out by emitting each of the register classes.
1166 const auto &RegisterClasses = RegBank.getRegClasses();
1167 const auto &SubRegIndices = RegBank.getSubRegIndices();
1169 // Collect all registers belonging to any allocatable class.
1170 std::set<Record*> AllocatableRegs;
1172 // Collect allocatable registers.
1173 for (const auto &RC : RegisterClasses) {
1174 ArrayRef<Record*> Order = RC.getOrder();
1177 AllocatableRegs.insert(Order.begin(), Order.end());
1180 // Build a shared array of value types.
1181 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1182 for (const auto &RC : RegisterClasses)
1185 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1186 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1189 // Emit SubRegIndex names, skipping 0.
1190 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1192 for (const auto &Idx : SubRegIndices) {
1193 OS << Idx.getName();
1198 // Emit SubRegIndex lane masks, including 0.
1199 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n LaneBitmask::getAll(),\n";
1200 for (const auto &Idx : SubRegIndices) {
1201 printMask(OS << " ", Idx.LaneMask);
1202 OS << ", // " << Idx.getName() << '\n';
1208 // Now that all of the structs have been emitted, emit the instances.
1209 if (!RegisterClasses.empty()) {
1210 OS << "\nstatic const TargetRegisterClass *const "
1211 << "NullRegClasses[] = { nullptr };\n\n";
1213 // Emit register class bit mask tables. The first bit mask emitted for a
1214 // register class, RC, is the set of sub-classes, including RC itself.
1216 // If RC has super-registers, also create a list of subreg indices and bit
1217 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1218 // SuperRC, that satisfies:
1220 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1222 // The 0-terminated list of subreg indices starts at:
1224 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1226 // The corresponding bitmasks follow the sub-class mask in memory. Each
1227 // mask has RCMaskWords uint32_t entries.
1229 // Every bit mask present in the list has at least one bit set.
1231 // Compress the sub-reg index lists.
1232 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1233 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1234 SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs;
1235 BitVector MaskBV(RegisterClasses.size());
1237 for (const auto &RC : RegisterClasses) {
1238 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1239 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1241 // Emit super-reg class masks for any relevant SubRegIndices that can
1243 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1244 for (auto &Idx : SubRegIndices) {
1246 RC.getSuperRegClasses(&Idx, MaskBV);
1249 SRIList.push_back(&Idx);
1251 printBitVectorAsHex(OS, MaskBV, 32);
1252 OS << "// " << Idx.getName();
1254 SuperRegIdxSeqs.add(SRIList);
1258 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1259 SuperRegIdxSeqs.layout();
1260 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1263 // Emit NULL terminated super-class lists.
1264 for (const auto &RC : RegisterClasses) {
1265 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1267 // Skip classes without supers. We can reuse NullRegClasses.
1271 OS << "static const TargetRegisterClass *const "
1272 << RC.getName() << "Superclasses[] = {\n";
1273 for (const auto *Super : Supers)
1274 OS << " &" << Super->getQualifiedName() << "RegClass,\n";
1275 OS << " nullptr\n};\n\n";
1279 for (const auto &RC : RegisterClasses) {
1280 if (!RC.AltOrderSelect.empty()) {
1281 OS << "\nstatic inline unsigned " << RC.getName()
1282 << "AltOrderSelect(const MachineFunction &MF) {"
1283 << RC.AltOrderSelect << "}\n\n"
1284 << "static ArrayRef<MCPhysReg> " << RC.getName()
1285 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1286 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1287 ArrayRef<Record*> Elems = RC.getOrder(oi);
1288 if (!Elems.empty()) {
1289 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1290 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1291 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1295 OS << " const MCRegisterClass &MCR = " << Target.getName()
1296 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1297 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1298 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1299 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1300 if (RC.getOrder(oi).empty())
1301 OS << "),\n ArrayRef<MCPhysReg>(";
1303 OS << "),\n makeArrayRef(AltOrder" << oi;
1304 OS << ")\n };\n const unsigned Select = " << RC.getName()
1305 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1306 << ");\n return Order[Select];\n}\n";
1310 // Now emit the actual value-initialized register class instances.
1311 OS << "\nnamespace " << RegisterClasses.front().Namespace
1312 << " { // Register class instances\n";
1314 for (const auto &RC : RegisterClasses) {
1315 assert(isUInt<16>(RC.SpillSize/8) && "SpillSize too large.");
1316 assert(isUInt<16>(RC.SpillAlignment/8) && "SpillAlignment too large.");
1317 OS << " extern const TargetRegisterClass " << RC.getName()
1318 << "RegClass = {\n " << '&' << Target.getName()
1319 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1320 << RC.SpillSize/8 << ", /* SpillSize */\n "
1321 << RC.SpillAlignment/8 << ", /* SpillAlignment */\n "
1322 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
1323 << "SubClassMask,\n SuperRegIdxSeqs + "
1324 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1325 printMask(OS, RC.LaneMask);
1326 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
1327 << (RC.HasDisjunctSubRegs?"true":"false")
1328 << ", /* HasDisjunctSubRegs */\n "
1329 << (RC.CoveredBySubRegs?"true":"false")
1330 << ", /* CoveredBySubRegs */\n ";
1331 if (RC.getSuperClasses().empty())
1332 OS << "NullRegClasses,\n ";
1334 OS << RC.getName() << "Superclasses,\n ";
1335 if (RC.AltOrderSelect.empty())
1338 OS << RC.getName() << "GetRawAllocationOrder\n";
1342 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
1345 OS << "\nnamespace {\n";
1346 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1347 for (const auto &RC : RegisterClasses)
1348 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1350 OS << "} // end anonymous namespace\n";
1352 // Emit extra information about registers.
1353 const std::string &TargetName = Target.getName();
1354 OS << "\nstatic const TargetRegisterInfoDesc "
1355 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1356 OS << " { 0, false },\n";
1358 const auto &Regs = RegBank.getRegisters();
1359 for (const auto &Reg : Regs) {
1361 OS << Reg.CostPerUse << ", "
1362 << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" )
1365 OS << "};\n"; // End of register descriptors...
1368 std::string ClassName = Target.getName().str() + "GenRegisterInfo";
1370 auto SubRegIndicesSize =
1371 std::distance(SubRegIndices.begin(), SubRegIndices.end());
1373 if (!SubRegIndices.empty()) {
1374 emitComposeSubRegIndices(OS, RegBank, ClassName);
1375 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
1378 // Emit getSubClassWithSubReg.
1379 if (!SubRegIndices.empty()) {
1380 OS << "const TargetRegisterClass *" << ClassName
1381 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1383 // Use the smallest type that can hold a regclass ID with room for a
1385 if (RegisterClasses.size() < UINT8_MAX)
1386 OS << " static const uint8_t Table[";
1387 else if (RegisterClasses.size() < UINT16_MAX)
1388 OS << " static const uint16_t Table[";
1390 PrintFatalError("Too many register classes.");
1391 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1392 for (const auto &RC : RegisterClasses) {
1393 OS << " {\t// " << RC.getName() << "\n";
1394 for (auto &Idx : SubRegIndices) {
1395 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1396 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1397 << " -> " << SRC->getName() << "\n";
1399 OS << " 0,\t// " << Idx.getName() << "\n";
1403 OS << " };\n assert(RC && \"Missing regclass\");\n"
1404 << " if (!Idx) return RC;\n --Idx;\n"
1405 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1406 << " unsigned TV = Table[RC->getID()][Idx];\n"
1407 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1410 EmitRegUnitPressure(OS, RegBank, ClassName);
1412 // Emit the constructor of the class...
1413 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1414 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1415 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n";
1416 OS << "extern const char " << TargetName << "RegStrings[];\n";
1417 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1418 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1419 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1420 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1421 << TargetName << "SubRegIdxRanges[];\n";
1422 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1424 EmitRegMappingTables(OS, Regs, true);
1426 OS << ClassName << "::\n" << ClassName
1427 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1428 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1429 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1430 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, ";
1431 printMask(OS, RegBank.CoveringLanes);
1433 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1434 << ", RA, PC,\n " << TargetName
1435 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1436 << " " << TargetName << "RegUnitRoots,\n"
1437 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1438 << " " << TargetName << "RegDiffLists,\n"
1439 << " " << TargetName << "LaneMaskLists,\n"
1440 << " " << TargetName << "RegStrings,\n"
1441 << " " << TargetName << "RegClassStrings,\n"
1442 << " " << TargetName << "SubRegIdxLists,\n"
1443 << " " << SubRegIndicesSize + 1 << ",\n"
1444 << " " << TargetName << "SubRegIdxRanges,\n"
1445 << " " << TargetName << "RegEncodingTable);\n\n";
1447 EmitRegMapping(OS, Regs, true);
1451 // Emit CalleeSavedRegs information.
1452 std::vector<Record*> CSRSets =
1453 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1454 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1455 Record *CSRSet = CSRSets[i];
1456 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1457 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1459 // Emit the *_SaveList list of callee-saved registers.
1460 OS << "static const MCPhysReg " << CSRSet->getName()
1461 << "_SaveList[] = { ";
1462 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1463 OS << getQualifiedName((*Regs)[r]) << ", ";
1466 // Emit the *_RegMask bit mask of call-preserved registers.
1467 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1469 // Check for an optional OtherPreserved set.
1470 // Add those registers to RegMask, but not to SaveList.
1471 if (DagInit *OPDag =
1472 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1473 SetTheory::RecSet OPSet;
1474 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1475 Covered |= RegBank.computeCoveredRegisters(
1476 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1479 OS << "static const uint32_t " << CSRSet->getName()
1480 << "_RegMask[] = { ";
1481 printBitVectorAsHex(OS, Covered, 32);
1486 OS << "ArrayRef<const uint32_t *> " << ClassName
1487 << "::getRegMasks() const {\n";
1488 if (!CSRSets.empty()) {
1489 OS << " static const uint32_t *const Masks[] = {\n";
1490 for (Record *CSRSet : CSRSets)
1491 OS << " " << CSRSet->getName() << "_RegMask,\n";
1493 OS << " return makeArrayRef(Masks);\n";
1495 OS << " return None;\n";
1499 OS << "ArrayRef<const char *> " << ClassName
1500 << "::getRegMaskNames() const {\n";
1501 if (!CSRSets.empty()) {
1502 OS << " static const char *const Names[] = {\n";
1503 for (Record *CSRSet : CSRSets)
1504 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";
1506 OS << " return makeArrayRef(Names);\n";
1508 OS << " return None;\n";
1512 OS << "const " << TargetName << "FrameLowering *\n" << TargetName
1513 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n"
1514 << " return static_cast<const " << TargetName << "FrameLowering *>(\n"
1515 << " MF.getSubtarget().getFrameLowering());\n"
1518 OS << "} // end namespace llvm\n\n";
1519 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1522 void RegisterInfoEmitter::run(raw_ostream &OS) {
1523 CodeGenTarget Target(Records);
1524 CodeGenRegBank &RegBank = Target.getRegBank();
1525 RegBank.computeDerivedInfo();
1527 runEnums(OS, Target, RegBank);
1528 runMCDesc(OS, Target, RegBank);
1529 runTargetHeader(OS, Target, RegBank);
1530 runTargetDesc(OS, Target, RegBank);
1535 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1536 RegisterInfoEmitter(RK).run(OS);
1539 } // end namespace llvm