1 //===- WebAssemblyDisassemblerEmitter.cpp - Disassembler tables -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the WebAssembly Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // WebAssemblyDisassemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "WebAssemblyDisassemblerEmitter.h"
18 #include "llvm/TableGen/Record.h"
22 void emitWebAssemblyDisassemblerTables(
24 const ArrayRef<const CodeGenInstruction *> &NumberedInstructions) {
25 // First lets organize all opcodes by (prefix) byte. Prefix 0 is the
28 std::map<unsigned, std::pair<unsigned, const CodeGenInstruction *>>>
30 for (unsigned I = 0; I != NumberedInstructions.size(); ++I) {
31 auto &CGI = *NumberedInstructions[I];
32 auto &Def = *CGI.TheDef;
33 if (!Def.getValue("Inst"))
35 auto &Inst = *Def.getValueAsBitsInit("Inst");
36 auto Opc = static_cast<unsigned>(
37 reinterpret_cast<IntInit *>(Inst.convertInitializerTo(IntRecTy::get()))
39 if (Opc == 0xFFFFFFFF)
40 continue; // No opcode defined.
41 assert(Opc <= 0xFFFF);
42 auto Prefix = Opc >> 8;
44 auto &CGIP = OpcodeTable[Prefix][Opc];
46 // Make sure we store the variant with the least amount of operands,
47 // which is the one without explicit registers. Only few instructions
48 // have these currently, would be good to have for all of them.
49 // FIXME: this picks the first of many typed variants, which is
50 // currently the except_ref one, though this shouldn't matter for
51 // disassembly purposes.
52 CGIP.second->Operands.OperandList.size() >
53 CGI.Operands.OperandList.size()) {
54 CGIP = std::make_pair(I, &CGI);
57 OS << "#include \"MCTargetDesc/WebAssemblyMCTargetDesc.h\"\n";
59 OS << "namespace llvm {\n\n";
60 OS << "enum EntryType : uint8_t { ";
61 OS << "ET_Unused, ET_Prefix, ET_Instruction };\n\n";
62 OS << "struct WebAssemblyInstruction {\n";
63 OS << " uint16_t Opcode;\n";
64 OS << " EntryType ET;\n";
65 OS << " uint8_t NumOperands;\n";
66 OS << " uint8_t Operands[4];\n";
68 // Output one table per prefix.
69 for (auto &PrefixPair : OpcodeTable) {
70 if (PrefixPair.second.empty())
72 OS << "WebAssemblyInstruction InstructionTable" << PrefixPair.first;
74 for (unsigned I = 0; I <= 0xFF; I++) {
75 auto InstIt = PrefixPair.second.find(I);
76 if (InstIt != PrefixPair.second.end()) {
77 // Regular instruction.
78 assert(InstIt->second.second);
79 auto &CGI = *InstIt->second.second;
81 OS.write_hex(static_cast<unsigned long long>(I));
82 OS << ": " << CGI.AsmString << "\n";
83 OS << " { " << InstIt->second.first << ", ET_Instruction, ";
84 OS << CGI.Operands.OperandList.size() << ", {\n";
85 for (auto &Op : CGI.Operands.OperandList) {
86 OS << " " << Op.OperandType << ",\n";
90 auto PrefixIt = OpcodeTable.find(I);
91 // If we have a non-empty table for it that's not 0, this is a prefix.
92 if (PrefixIt != OpcodeTable.end() && I && !PrefixPair.first) {
93 OS << " { 0, ET_Prefix, 0, {}";
95 OS << " { 0, ET_Unused, 0, {}";
102 // Create a table of all extension tables:
103 OS << "struct { uint8_t Prefix; const WebAssemblyInstruction *Table; }\n";
104 OS << "PrefixTable[] = {\n";
105 for (auto &PrefixPair : OpcodeTable) {
106 if (PrefixPair.second.empty() || !PrefixPair.first)
108 OS << " { " << PrefixPair.first << ", InstructionTable"
112 OS << " { 0, nullptr }\n};\n\n";
113 OS << "} // End llvm namespace\n";