1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
18 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
20 #include "CodeGenTarget.h"
21 #include "X86DisassemblerTables.h"
22 #include "llvm/Support/DataTypes.h"
23 #include "llvm/TableGen/Record.h"
27 namespace X86Disassembler {
29 /// RecognizableInstr - Encapsulates all information required to decode a single
30 /// instruction, as extracted from the LLVM instruction tables. Has methods
31 /// to interpret the information available in the LLVM tables, and to emit the
32 /// instruction into DisassemblerTables.
33 class RecognizableInstr {
35 /// The opcode of the instruction, as used in an MCInst
37 /// The record from the .td files corresponding to this instruction
39 /// The OpPrefix field from the record
41 /// The OpMap field from the record
43 /// The opcode field from the record; this is the opcode used in the Intel
44 /// encoding and therefore distinct from the UID
46 /// The form field from the record
48 // The encoding field from the record
50 /// The OpSize field from the record
52 /// The AdSize field from the record
54 /// The hasREX_WPrefix field from the record
56 /// The hasVEX_4V field from the record
58 /// The hasVEX_WPrefix field from the record
60 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
62 /// The ignoreVEX_L field from the record
64 /// The hasEVEX_L2Prefix field from the record
65 bool HasEVEX_L2Prefix;
66 /// The hasEVEX_K field from the record
68 /// The hasEVEX_KZ field from the record
70 /// The hasEVEX_B field from the record
72 /// The isCodeGenOnly field from the record
74 /// The ForceDisassemble field from the record
75 bool ForceDisassemble;
76 // The CD8_Scale field from the record
78 // Whether the instruction has the predicate "In64BitMode"
80 // Whether the instruction has the predicate "In32BitMode"
83 /// The instruction name as listed in the tables
86 /// Indicates whether the instruction should be emitted into the decode
87 /// tables; regardless, it will be emitted into the instruction info table
90 /// The operands of the instruction, as listed in the CodeGenInstruction.
91 /// They are not one-to-one with operands listed in the MCInst; for example,
92 /// memory operands expand to 5 operands in the MCInst
93 const std::vector<CGIOperandList::OperandInfo>* Operands;
95 /// The description of the instruction that is emitted into the instruction
97 InstructionSpecifier* Spec;
99 /// insnContext - Returns the primary context in which the instruction is
102 /// @return - The context in which the instruction is valid.
103 InstructionContext insnContext() const;
105 /// typeFromString - Translates an operand type from the string provided in
106 /// the LLVM tables to an OperandType for use in the operand specifier.
108 /// @param s - The string, as extracted by calling Rec->getName()
109 /// on a CodeGenInstruction::OperandInfo.
110 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
111 /// prefix. If it does, 32-bit register operands stay
112 /// 32-bit regardless of the operand size.
113 /// @param OpSize Indicates the operand size of the instruction.
114 /// If register size does not match OpSize, then
115 /// register sizes keep their size.
116 /// @return - The operand's type.
117 static OperandType typeFromString(const std::string& s,
118 bool hasREX_WPrefix, uint8_t OpSize);
120 /// immediateEncodingFromString - Translates an immediate encoding from the
121 /// string provided in the LLVM tables to an OperandEncoding for use in
122 /// the operand specifier.
124 /// @param s - See typeFromString().
125 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
126 /// If it is not, then 16-bit immediate operands stay 16-bit.
127 /// @return - The operand's encoding.
128 static OperandEncoding immediateEncodingFromString(const std::string &s,
131 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
132 /// handles operands that are in the REG field of the ModR/M byte.
133 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
136 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
137 /// handles operands that are in the REG field of the ModR/M byte.
138 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
140 static OperandEncoding memoryEncodingFromString(const std::string &s,
142 static OperandEncoding relocationEncodingFromString(const std::string &s,
144 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
146 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
148 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
151 /// \brief Adjust the encoding type for an operand based on the instruction.
152 void adjustOperandEncoding(OperandEncoding &encoding);
154 /// handleOperand - Converts a single operand from the LLVM table format to
155 /// the emitted table format, handling any duplicate operands it encounters
156 /// and then one non-duplicate.
158 /// @param optional - Determines whether to assert that the
160 /// @param operandIndex - The index into the generated operand table.
161 /// Incremented by this function one or more
162 /// times to reflect possible duplicate
164 /// @param physicalOperandIndex - The index of the current operand into the
165 /// set of non-duplicate ('physical') operands.
166 /// Incremented by this function once.
167 /// @param numPhysicalOperands - The number of non-duplicate operands in the
169 /// @param operandMapping - The operand mapping, which has an entry for
170 /// each operand that indicates whether it is a
171 /// duplicate, and of what.
172 void handleOperand(bool optional,
173 unsigned &operandIndex,
174 unsigned &physicalOperandIndex,
175 unsigned numPhysicalOperands,
176 const unsigned *operandMapping,
177 OperandEncoding (*encodingFromString)
181 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
182 /// filters out many instructions, at various points in decoding we
183 /// determine that the instruction should not actually be decodable. In
184 /// particular, MMX MOV instructions aren't emitted, but they're only
185 /// identified during operand parsing.
187 /// @return - true if at this point we believe the instruction should be
188 /// emitted; false if not. This will return false if filter() returns false
189 /// once emitInstructionSpecifier() has been called.
190 bool shouldBeEmitted() const {
191 return ShouldBeEmitted;
194 /// emitInstructionSpecifier - Loads the instruction specifier for the current
195 /// instruction into a DisassemblerTables.
197 void emitInstructionSpecifier();
199 /// emitDecodePath - Populates the proper fields in the decode tables
200 /// corresponding to the decode paths for this instruction.
202 /// \param tables The DisassemblerTables to populate with the decode
203 /// decode information for the current instruction.
204 void emitDecodePath(DisassemblerTables &tables) const;
206 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
207 /// from a CodeGenInstruction.
209 /// \param tables The DisassemblerTables that the specifier will be added to.
210 /// \param insn The CodeGenInstruction to extract information from.
211 /// \param uid The unique ID of the current instruction.
212 RecognizableInstr(DisassemblerTables &tables,
213 const CodeGenInstruction &insn,
216 /// processInstr - Accepts a CodeGenInstruction and loads decode information
217 /// for it into a DisassemblerTables if appropriate.
219 /// \param tables The DiassemblerTables to be populated with decode
221 /// \param insn The CodeGenInstruction to be used as a source for this
223 /// \param uid The unique ID of the instruction.
224 static void processInstr(DisassemblerTables &tables,
225 const CodeGenInstruction &insn,
229 } // namespace X86Disassembler