1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
18 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
20 #include "CodeGenTarget.h"
21 #include "X86DisassemblerTables.h"
22 #include "llvm/Support/DataTypes.h"
23 #include "llvm/TableGen/Record.h"
27 namespace X86Disassembler {
29 /// RecognizableInstr - Encapsulates all information required to decode a single
30 /// instruction, as extracted from the LLVM instruction tables. Has methods
31 /// to interpret the information available in the LLVM tables, and to emit the
32 /// instruction into DisassemblerTables.
33 class RecognizableInstr {
35 /// The opcode of the instruction, as used in an MCInst
37 /// The record from the .td files corresponding to this instruction
39 /// The OpPrefix field from the record
41 /// The OpMap field from the record
43 /// The opcode field from the record; this is the opcode used in the Intel
44 /// encoding and therefore distinct from the UID
46 /// The form field from the record
48 // The encoding field from the record
50 /// The OpSize field from the record
52 /// The AdSize field from the record
54 /// The hasREX_WPrefix field from the record
56 /// The hasVEX_4V field from the record
58 /// The hasVEX_4VOp3 field from the record
60 /// The hasVEX_WPrefix field from the record
62 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
64 /// The hasMemOp4Prefix field from the record
66 /// The ignoreVEX_L field from the record
68 /// The hasEVEX_L2Prefix field from the record
69 bool HasEVEX_L2Prefix;
70 /// The hasEVEX_K field from the record
72 /// The hasEVEX_KZ field from the record
74 /// The hasEVEX_B field from the record
76 /// The isCodeGenOnly field from the record
78 /// The ForceDisassemble field from the record
79 bool ForceDisassemble;
80 // The CD8_Scale field from the record
82 // Whether the instruction has the predicate "In64BitMode"
84 // Whether the instruction has the predicate "In32BitMode"
87 /// The instruction name as listed in the tables
90 /// Indicates whether the instruction should be emitted into the decode
91 /// tables; regardless, it will be emitted into the instruction info table
94 /// The operands of the instruction, as listed in the CodeGenInstruction.
95 /// They are not one-to-one with operands listed in the MCInst; for example,
96 /// memory operands expand to 5 operands in the MCInst
97 const std::vector<CGIOperandList::OperandInfo>* Operands;
99 /// The description of the instruction that is emitted into the instruction
101 InstructionSpecifier* Spec;
103 /// insnContext - Returns the primary context in which the instruction is
106 /// @return - The context in which the instruction is valid.
107 InstructionContext insnContext() const;
109 /// typeFromString - Translates an operand type from the string provided in
110 /// the LLVM tables to an OperandType for use in the operand specifier.
112 /// @param s - The string, as extracted by calling Rec->getName()
113 /// on a CodeGenInstruction::OperandInfo.
114 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
115 /// prefix. If it does, 32-bit register operands stay
116 /// 32-bit regardless of the operand size.
117 /// @param OpSize Indicates the operand size of the instruction.
118 /// If register size does not match OpSize, then
119 /// register sizes keep their size.
120 /// @return - The operand's type.
121 static OperandType typeFromString(const std::string& s,
122 bool hasREX_WPrefix, uint8_t OpSize);
124 /// immediateEncodingFromString - Translates an immediate encoding from the
125 /// string provided in the LLVM tables to an OperandEncoding for use in
126 /// the operand specifier.
128 /// @param s - See typeFromString().
129 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
130 /// If it is not, then 16-bit immediate operands stay 16-bit.
131 /// @return - The operand's encoding.
132 static OperandEncoding immediateEncodingFromString(const std::string &s,
135 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
136 /// handles operands that are in the REG field of the ModR/M byte.
137 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
140 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
141 /// handles operands that are in the REG field of the ModR/M byte.
142 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
144 static OperandEncoding memoryEncodingFromString(const std::string &s,
146 static OperandEncoding relocationEncodingFromString(const std::string &s,
148 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
150 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
152 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
155 /// \brief Adjust the encoding type for an operand based on the instruction.
156 void adjustOperandEncoding(OperandEncoding &encoding);
158 /// handleOperand - Converts a single operand from the LLVM table format to
159 /// the emitted table format, handling any duplicate operands it encounters
160 /// and then one non-duplicate.
162 /// @param optional - Determines whether to assert that the
164 /// @param operandIndex - The index into the generated operand table.
165 /// Incremented by this function one or more
166 /// times to reflect possible duplicate
168 /// @param physicalOperandIndex - The index of the current operand into the
169 /// set of non-duplicate ('physical') operands.
170 /// Incremented by this function once.
171 /// @param numPhysicalOperands - The number of non-duplicate operands in the
173 /// @param operandMapping - The operand mapping, which has an entry for
174 /// each operand that indicates whether it is a
175 /// duplicate, and of what.
176 void handleOperand(bool optional,
177 unsigned &operandIndex,
178 unsigned &physicalOperandIndex,
179 unsigned numPhysicalOperands,
180 const unsigned *operandMapping,
181 OperandEncoding (*encodingFromString)
185 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
186 /// filters out many instructions, at various points in decoding we
187 /// determine that the instruction should not actually be decodable. In
188 /// particular, MMX MOV instructions aren't emitted, but they're only
189 /// identified during operand parsing.
191 /// @return - true if at this point we believe the instruction should be
192 /// emitted; false if not. This will return false if filter() returns false
193 /// once emitInstructionSpecifier() has been called.
194 bool shouldBeEmitted() const {
195 return ShouldBeEmitted;
198 /// emitInstructionSpecifier - Loads the instruction specifier for the current
199 /// instruction into a DisassemblerTables.
201 void emitInstructionSpecifier();
203 /// emitDecodePath - Populates the proper fields in the decode tables
204 /// corresponding to the decode paths for this instruction.
206 /// \param tables The DisassemblerTables to populate with the decode
207 /// decode information for the current instruction.
208 void emitDecodePath(DisassemblerTables &tables) const;
210 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
211 /// from a CodeGenInstruction.
213 /// \param tables The DisassemblerTables that the specifier will be added to.
214 /// \param insn The CodeGenInstruction to extract information from.
215 /// \param uid The unique ID of the current instruction.
216 RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
220 /// processInstr - Accepts a CodeGenInstruction and loads decode information
221 /// for it into a DisassemblerTables if appropriate.
223 /// \param tables The DiassemblerTables to be populated with decode
225 /// \param insn The CodeGenInstruction to be used as a source for this
227 /// \param uid The unique ID of the instruction.
228 static void processInstr(DisassemblerTables &tables,
229 const CodeGenInstruction &insn,
233 } // namespace X86Disassembler