1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the TableGen definitions from which the ARM NEON header
10 // file will be generated. See ARM document DUI0348B.
12 //===----------------------------------------------------------------------===//
14 include "arm_neon_incl.td"
16 def OP_ADD : Op<(op "+", $p0, $p1)>;
17 def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>;
18 def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0),
19 (call "vmovl_high", $p1))>;
20 def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>;
21 def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>;
22 def OP_SUB : Op<(op "-", $p0, $p1)>;
23 def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>;
24 def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0),
25 (call "vmovl_high", $p1))>;
26 def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>;
27 def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>;
28 def OP_MUL : Op<(op "*", $p0, $p1)>;
29 def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>;
30 def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>;
31 def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0),
32 (call "vget_high", $p1))>;
33 def OP_MULLHi_P64 : Op<(call "vmull",
34 (cast "poly64_t", (call "vget_high", $p0)),
35 (cast "poly64_t", (call "vget_high", $p1)))>;
36 def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>;
37 def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1),
38 (call "vget_high", $p2))>;
39 def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>;
40 def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>;
41 def OP_FMLS : Op<(call "vfma", $p0, (op "-", $p1), $p2)>;
42 def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>;
43 def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1),
44 (call "vget_high", $p2))>;
45 def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
46 def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>;
47 def OP_MULX_N : Op<(call "vmulx", $p0, (dup $p1))>;
48 def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>;
49 def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>;
50 def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>;
51 def OP_FMLS_N : Op<(call "vfma", $p0, (op "-", $p1), (dup $p2))>;
52 def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>;
53 def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>;
54 def OP_MUL_LN : Op<(op "*", $p0, (call_mangled "splat_lane", $p1, $p2))>;
55 def OP_MULX_LN : Op<(call "vmulx", $p0, (call_mangled "splat_lane", $p1, $p2))>;
56 def OP_MULL_N : Op<(call "vmull", $p0, (dup $p1))>;
57 def OP_MULL_LN : Op<(call "vmull", $p0, (call_mangled "splat_lane", $p1, $p2))>;
58 def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (call_mangled "splat_lane", $p1, $p2))>;
59 def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
60 def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
61 def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
62 def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1),
63 (call_mangled "splat_lane", $p2, $p3)))>;
64 def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
65 def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1),
66 (call_mangled "splat_lane", $p2, $p3)))>;
67 def OP_QDMULL_N : Op<(call "vqdmull", $p0, (dup $p1))>;
68 def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (call_mangled "splat_lane", $p1, $p2))>;
69 def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0),
70 (call_mangled "splat_lane", $p1, $p2))>;
71 def OP_QDMLAL_N : Op<(call "vqdmlal", $p0, $p1, (dup $p2))>;
72 def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (call_mangled "splat_lane", $p2, $p3))>;
73 def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
74 (call_mangled "splat_lane", $p2, $p3))>;
75 def OP_QDMLSL_N : Op<(call "vqdmlsl", $p0, $p1, (dup $p2))>;
76 def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (call_mangled "splat_lane", $p2, $p3))>;
77 def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
78 (call_mangled "splat_lane", $p2, $p3))>;
79 def OP_QDMULH_N : Op<(call "vqdmulh", $p0, (dup $p1))>;
80 def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (call_mangled "splat_lane", $p1, $p2))>;
81 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (call_mangled "splat_lane", $p1, $p2))>;
82 def OP_QRDMULH_N : Op<(call "vqrdmulh", $p0, (dup $p1))>;
83 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>;
84 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>;
85 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
86 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (call_mangled "splat_lane", $p2, $p3)))>;
87 def OP_FMS_LN : Op<(call "vfma_lane", $p0, (op "-", $p1), $p2, $p3)>;
88 def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, (op "-", $p1), $p2, $p3)>;
89 def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2),
90 (decimate mask1, 2)))>;
91 def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>;
92 def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2),
93 (decimate mask1, 2)))>;
94 def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave
95 (decimate (rotl mask0, 1), 2),
96 (decimate (rotl mask1, 1), 2)))>;
97 def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>;
98 def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2),
99 (decimate (rotl mask1, 1), 2)))>;
100 def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>;
101 def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>;
102 def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>;
103 def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>;
104 def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>;
105 def OP_NEG : Op<(op "-", $p0)>;
106 def OP_NOT : Op<(op "~", $p0)>;
107 def OP_AND : Op<(op "&", $p0, $p1)>;
108 def OP_OR : Op<(op "|", $p0, $p1)>;
109 def OP_XOR : Op<(op "^", $p0, $p1)>;
110 def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>;
111 def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>;
112 def OP_CAST : LOp<[(save_temp $promote, $p0),
113 (cast "R", $promote)]>;
114 def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>;
115 def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>;
116 def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>;
117 def OP_DUP : Op<(dup $p0)>;
118 def OP_DUP_LN : Op<(call_mangled "splat_lane", $p0, $p1)>;
119 def OP_SEL : Op<(cast "R", (op "|",
120 (op "&", $p0, (cast $p0, $p1)),
121 (op "&", (op "~", $p0), (cast $p0, $p2))))>;
122 def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>;
123 def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>;
124 def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>;
125 def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>;
126 def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0),
127 (call "vqmovun", $p1))>;
128 def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>;
129 def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>;
130 def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>;
131 def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>;
132 def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>;
133 def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>;
134 def OP_REINT : Op<(cast "R", $p0)>;
135 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
136 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>;
137 def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>;
138 def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>;
139 def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U",
140 (call "vabd", $p0, $p1))))>;
141 def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0),
142 (call "vget_high", $p1))>;
143 def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>;
144 def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>;
145 def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1),
146 (call "vget_high", $p2))>;
147 def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0),
148 (call "vget_high", $p1))>;
149 def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>;
150 def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1),
151 (call "vget_high", $p2))>;
152 def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>;
153 def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
154 (call "vget_high", $p2))>;
155 def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
156 def OP_DIV : Op<(op "/", $p0, $p1)>;
157 def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"),
158 (call "vget_high", $p0), $p1))>;
159 def OP_NARROW_HI : Op<(cast "R", (call "vcombine",
160 (cast "R", "H", $p0),
162 (call (name_replace "_high_", "_"),
164 def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)),
166 (call "vshll_n", $a1, (literal "int32_t", "0")))]>;
167 def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>;
168 def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>;
169 def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>;
170 def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0,
171 (literal "int32_t", "0"))),
172 (save_temp $y, (call "vget_lane", $p1, $p2)),
173 (save_temp $z, (call "vmulx", $x, $y)),
174 (call "vset_lane", $z, $p0, $p2)]>;
175 def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0,
176 (literal "int32_t", "0"))),
177 (save_temp $y, (call "vget_lane", $p1, $p2)),
178 (save_temp $z, (call "vmulx", $x, $y)),
179 (call "vset_lane", $z, $p0, (literal "int32_t",
181 class ScalarMulOp<string opname> :
182 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>;
184 def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">;
185 def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">;
186 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
188 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
189 (call "vget_lane", $p2, $p3)))>;
190 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
191 (call "vget_lane", $p2, $p3)))>;
193 def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
195 (bitcast "int16x4_t", $p0), $p1))>;
196 def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
198 (bitcast "int16x8_t", $p0), $p1))>;
199 def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
201 (bitcast "int16_t", $p0),
202 (bitcast "int16x4_t", $p1), $p2))>;
203 def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
205 (bitcast "int16_t", $p0),
206 (bitcast "int16x8_t", $p1), $p2))>;
209 : Op<(call "vdot", $p0, $p1,
210 (bitcast $p1, (call_mangled "splat_lane", (bitcast "32", $p2), $p3)))>;
212 : Op<(call "vdot", $p0, $p1,
213 (bitcast $p1, (call_mangled "splat_lane", (bitcast "32", $p2), $p3)))>;
215 def OP_FMLAL_LN : Op<(call "vfmlal_low", $p0, $p1,
216 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
217 def OP_FMLSL_LN : Op<(call "vfmlsl_low", $p0, $p1,
218 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
219 def OP_FMLAL_LN_Hi : Op<(call "vfmlal_high", $p0, $p1,
220 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
221 def OP_FMLSL_LN_Hi : Op<(call "vfmlsl_high", $p0, $p1,
222 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
225 : Op<(call "vusdot", $p0, $p1,
226 (cast "8", "S", (call_mangled "splat_lane", (bitcast "int32x2_t", $p2), $p3)))>;
228 : Op<(call "vusdot", $p0, $p1,
229 (cast "8", "S", (call_mangled "splat_lane", (bitcast "int32x4_t", $p2), $p3)))>;
231 // sudot splats the second vector and then calls vusdot
233 : Op<(call "vusdot", $p0,
234 (cast "8", "U", (call_mangled "splat_lane", (bitcast "int32x2_t", $p2), $p3)), $p1)>;
236 : Op<(call "vusdot", $p0,
237 (cast "8", "U", (call_mangled "splat_lane", (bitcast "int32x4_t", $p2), $p3)), $p1)>;
240 : Op<(call "vbfdot", $p0, $p1,
241 (bitcast $p1, (call_mangled "splat_lane", (bitcast "float32x2_t", $p2), $p3)))>;
244 : Op<(call "vbfdot", $p0, $p1,
245 (bitcast $p1, (call_mangled "splat_lane", (bitcast "float32x4_t", $p2), $p3)))>;
248 : Op<(call "vbfmlalb", $p0, $p1,
249 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
252 : Op<(call "vbfmlalt", $p0, $p1,
253 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
257 (call "vshll_n", (bitcast "int16x4_t", $p0),
258 (literal "int32_t", "16")))>;
259 def OP_VCVT_F32_BF16_LO
260 : Op<(call "vcvt_f32_bf16", (call "vget_low", $p0))>;
261 def OP_VCVT_F32_BF16_HI
262 : Op<(call "vcvt_f32_bf16", (call "vget_high", $p0))>;
264 def OP_VCVT_BF16_F32_LO_A64
265 : Op<(call "__a64_vcvtq_low_bf16", $p0)>;
266 def OP_VCVT_BF16_F32_A64
267 : Op<(call "vget_low", (call "__a64_vcvtq_low_bf16", $p0))>;
269 def OP_VCVT_BF16_F32_A32
270 : Op<(call "__a32_vcvt_bf16", $p0)>;
272 def OP_VCVT_BF16_F32_LO_A32
273 : Op<(call "vcombine", (cast "bfloat16x4_t", (literal "uint64_t", "0ULL")),
274 (call "__a32_vcvt_bf16", $p0))>;
275 def OP_VCVT_BF16_F32_HI_A32
276 : Op<(call "vcombine", (call "__a32_vcvt_bf16", $p1),
277 (call "vget_low", $p0))>;
280 : Op<(bitcast "R", (op "<<", (bitcast "int32_t", $p0),
281 (literal "int32_t", "16")))>;
283 //===----------------------------------------------------------------------===//
284 // Auxiliary Instructions
285 //===----------------------------------------------------------------------===//
287 // Splat operation - performs a range-checked splat over a vector
288 def SPLAT : WInst<"splat_lane", ".(!q)I",
289 "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl">;
290 def SPLATQ : WInst<"splat_laneq", ".(!Q)I",
291 "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
294 let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
295 def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb">;
296 def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
305 ////////////////////////////////////////////////////////////////////////////////
307 def VADD : IOpInst<"vadd", "...",
308 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
309 def VADDL : SOpInst<"vaddl", "(>Q)..", "csiUcUsUi", OP_ADDL>;
310 def VADDW : SOpInst<"vaddw", "(>Q)(>Q).", "csiUcUsUi", OP_ADDW>;
311 def VHADD : SInst<"vhadd", "...", "csiUcUsUiQcQsQiQUcQUsQUi">;
312 def VRHADD : SInst<"vrhadd", "...", "csiUcUsUiQcQsQiQUcQUsQUi">;
313 def VQADD : SInst<"vqadd", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
314 def VADDHN : IInst<"vaddhn", "<QQ", "silUsUiUl">;
315 def VRADDHN : IInst<"vraddhn", "<QQ", "silUsUiUl">;
317 ////////////////////////////////////////////////////////////////////////////////
318 // E.3.2 Multiplication
319 def VMUL : IOpInst<"vmul", "...", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
320 def VMULP : SInst<"vmul", "...", "PcQPc">;
321 def VMLA : IOpInst<"vmla", "....", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
322 def VMLAL : SOpInst<"vmlal", "(>Q)(>Q)..", "csiUcUsUi", OP_MLAL>;
323 def VMLS : IOpInst<"vmls", "....", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
324 def VMLSL : SOpInst<"vmlsl", "(>Q)(>Q)..", "csiUcUsUi", OP_MLSL>;
325 def VQDMULH : SInst<"vqdmulh", "...", "siQsQi">;
326 def VQRDMULH : SInst<"vqrdmulh", "...", "siQsQi">;
328 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
329 def VQRDMLAH : SOpInst<"vqrdmlah", "....", "siQsQi", OP_QRDMLAH>;
330 def VQRDMLSH : SOpInst<"vqrdmlsh", "....", "siQsQi", OP_QRDMLSH>;
333 def VQDMLAL : SInst<"vqdmlal", "(>Q)(>Q)..", "si">;
334 def VQDMLSL : SInst<"vqdmlsl", "(>Q)(>Q)..", "si">;
335 def VMULL : SInst<"vmull", "(>Q)..", "csiUcUsUiPc">;
336 def VQDMULL : SInst<"vqdmull", "(>Q)..", "si">;
338 ////////////////////////////////////////////////////////////////////////////////
340 def VSUB : IOpInst<"vsub", "...",
341 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
342 def VSUBL : SOpInst<"vsubl", "(>Q)..", "csiUcUsUi", OP_SUBL>;
343 def VSUBW : SOpInst<"vsubw", "(>Q)(>Q).", "csiUcUsUi", OP_SUBW>;
344 def VQSUB : SInst<"vqsub", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
345 def VHSUB : SInst<"vhsub", "...", "csiUcUsUiQcQsQiQUcQUsQUi">;
346 def VSUBHN : IInst<"vsubhn", "<QQ", "silUsUiUl">;
347 def VRSUBHN : IInst<"vrsubhn", "<QQ", "silUsUiUl">;
349 ////////////////////////////////////////////////////////////////////////////////
351 def VCEQ : IOpInst<"vceq", "U..", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>;
352 def VCGE : SOpInst<"vcge", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
353 let InstName = "vcge" in
354 def VCLE : SOpInst<"vcle", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
355 def VCGT : SOpInst<"vcgt", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
356 let InstName = "vcgt" in
357 def VCLT : SOpInst<"vclt", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
358 let InstName = "vacge" in {
359 def VCAGE : IInst<"vcage", "U..", "fQf">;
360 def VCALE : IInst<"vcale", "U..", "fQf">;
362 let InstName = "vacgt" in {
363 def VCAGT : IInst<"vcagt", "U..", "fQf">;
364 def VCALT : IInst<"vcalt", "U..", "fQf">;
366 def VTST : WInst<"vtst", "U..", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
368 ////////////////////////////////////////////////////////////////////////////////
369 // E.3.5 Absolute Difference
370 def VABD : SInst<"vabd", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
371 def VABDL : SOpInst<"vabdl", "(>Q)..", "csiUcUsUi", OP_ABDL>;
372 def VABA : SOpInst<"vaba", "....", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>;
373 def VABAL : SOpInst<"vabal", "(>Q)(>Q)..", "csiUcUsUi", OP_ABAL>;
375 ////////////////////////////////////////////////////////////////////////////////
377 def VMAX : SInst<"vmax", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
378 def VMIN : SInst<"vmin", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
380 ////////////////////////////////////////////////////////////////////////////////
381 // E.3.7 Pairwise Addition
382 def VPADD : IInst<"vpadd", "...", "csiUcUsUif">;
383 def VPADDL : SInst<"vpaddl", ">.", "csiUcUsUiQcQsQiQUcQUsQUi">;
384 def VPADAL : SInst<"vpadal", ">>.", "csiUcUsUiQcQsQiQUcQUsQUi">;
386 ////////////////////////////////////////////////////////////////////////////////
387 // E.3.8-9 Folding Max/Min
388 def VPMAX : SInst<"vpmax", "...", "csiUcUsUif">;
389 def VPMIN : SInst<"vpmin", "...", "csiUcUsUif">;
391 ////////////////////////////////////////////////////////////////////////////////
392 // E.3.10 Reciprocal/Sqrt
393 def VRECPS : IInst<"vrecps", "...", "fQf">;
394 def VRSQRTS : IInst<"vrsqrts", "...", "fQf">;
396 ////////////////////////////////////////////////////////////////////////////////
397 // E.3.11 Shifts by signed variable
398 def VSHL : SInst<"vshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
399 def VQSHL : SInst<"vqshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
400 def VRSHL : SInst<"vrshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
401 def VQRSHL : SInst<"vqrshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
403 ////////////////////////////////////////////////////////////////////////////////
404 // E.3.12 Shifts by constant
406 def VSHR_N : SInst<"vshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
407 def VSHL_N : IInst<"vshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
408 def VRSHR_N : SInst<"vrshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
409 def VSRA_N : SInst<"vsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
410 def VRSRA_N : SInst<"vrsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
411 def VQSHL_N : SInst<"vqshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
412 def VQSHLU_N : SInst<"vqshlu_n", "U.I", "csilQcQsQiQl">;
413 def VSHRN_N : IInst<"vshrn_n", "<QI", "silUsUiUl">;
414 def VQSHRUN_N : SInst<"vqshrun_n", "(<U)QI", "sil">;
415 def VQRSHRUN_N : SInst<"vqrshrun_n", "(<U)QI", "sil">;
416 def VQSHRN_N : SInst<"vqshrn_n", "<QI", "silUsUiUl">;
417 def VRSHRN_N : IInst<"vrshrn_n", "<QI", "silUsUiUl">;
418 def VQRSHRN_N : SInst<"vqrshrn_n", "<QI", "silUsUiUl">;
419 def VSHLL_N : SInst<"vshll_n", "(>Q).I", "csiUcUsUi">;
421 ////////////////////////////////////////////////////////////////////////////////
422 // E.3.13 Shifts with insert
423 def VSRI_N : WInst<"vsri_n", "...I",
424 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
425 def VSLI_N : WInst<"vsli_n", "...I",
426 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
429 ////////////////////////////////////////////////////////////////////////////////
430 // E.3.14 Loads and stores of a single vector
431 def VLD1 : WInst<"vld1", ".(c*!)",
432 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
433 def VLD1_X2 : WInst<"vld1_x2", "2(c*!)",
434 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
435 def VLD1_X3 : WInst<"vld1_x3", "3(c*!)",
436 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
437 def VLD1_X4 : WInst<"vld1_x4", "4(c*!)",
438 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
439 def VLD1_LANE : WInst<"vld1_lane", ".(c*!).I",
440 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
441 def VLD1_DUP : WInst<"vld1_dup", ".(c*!)",
442 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
443 def VST1 : WInst<"vst1", "v*(.!)",
444 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
445 def VST1_X2 : WInst<"vst1_x2", "v*(2!)",
446 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
447 def VST1_X3 : WInst<"vst1_x3", "v*(3!)",
448 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
449 def VST1_X4 : WInst<"vst1_x4", "v*(4!)",
450 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
451 def VST1_LANE : WInst<"vst1_lane", "v*(.!)I",
452 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
453 let ArchGuard = "(__ARM_FP & 2)" in {
454 def VLD1_F16 : WInst<"vld1", ".(c*!)", "hQh">;
455 def VLD1_X2_F16 : WInst<"vld1_x2", "2(c*!)", "hQh">;
456 def VLD1_X3_F16 : WInst<"vld1_x3", "3(c*!)", "hQh">;
457 def VLD1_X4_F16 : WInst<"vld1_x4", "4(c*!)", "hQh">;
458 def VLD1_LANE_F16 : WInst<"vld1_lane", ".(c*!).I", "hQh">;
459 def VLD1_DUP_F16 : WInst<"vld1_dup", ".(c*!)", "hQh">;
460 def VST1_F16 : WInst<"vst1", "v*(.!)", "hQh">;
461 def VST1_X2_F16 : WInst<"vst1_x2", "v*(2!)", "hQh">;
462 def VST1_X3_F16 : WInst<"vst1_x3", "v*(3!)", "hQh">;
463 def VST1_X4_F16 : WInst<"vst1_x4", "v*(4!)", "hQh">;
464 def VST1_LANE_F16 : WInst<"vst1_lane", "v*(.!)I", "hQh">;
467 ////////////////////////////////////////////////////////////////////////////////
468 // E.3.15 Loads and stores of an N-element structure
469 def VLD2 : WInst<"vld2", "2(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
470 def VLD3 : WInst<"vld3", "3(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
471 def VLD4 : WInst<"vld4", "4(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
472 def VLD2_DUP : WInst<"vld2_dup", "2(c*!)",
473 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
474 def VLD3_DUP : WInst<"vld3_dup", "3(c*!)",
475 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
476 def VLD4_DUP : WInst<"vld4_dup", "4(c*!)",
477 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
478 def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
479 def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
480 def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
481 def VST2 : WInst<"vst2", "v*(2!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
482 def VST3 : WInst<"vst3", "v*(3!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
483 def VST4 : WInst<"vst4", "v*(4!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
484 def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
485 def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
486 def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
487 let ArchGuard = "(__ARM_FP & 2)" in {
488 def VLD2_F16 : WInst<"vld2", "2(c*!)", "hQh">;
489 def VLD3_F16 : WInst<"vld3", "3(c*!)", "hQh">;
490 def VLD4_F16 : WInst<"vld4", "4(c*!)", "hQh">;
491 def VLD2_DUP_F16 : WInst<"vld2_dup", "2(c*!)", "hQh">;
492 def VLD3_DUP_F16 : WInst<"vld3_dup", "3(c*!)", "hQh">;
493 def VLD4_DUP_F16 : WInst<"vld4_dup", "4(c*!)", "hQh">;
494 def VLD2_LANE_F16 : WInst<"vld2_lane", "2(c*!)2I", "hQh">;
495 def VLD3_LANE_F16 : WInst<"vld3_lane", "3(c*!)3I", "hQh">;
496 def VLD4_LANE_F16 : WInst<"vld4_lane", "4(c*!)4I", "hQh">;
497 def VST2_F16 : WInst<"vst2", "v*(2!)", "hQh">;
498 def VST3_F16 : WInst<"vst3", "v*(3!)", "hQh">;
499 def VST4_F16 : WInst<"vst4", "v*(4!)", "hQh">;
500 def VST2_LANE_F16 : WInst<"vst2_lane", "v*(2!)I", "hQh">;
501 def VST3_LANE_F16 : WInst<"vst3_lane", "v*(3!)I", "hQh">;
502 def VST4_LANE_F16 : WInst<"vst4_lane", "v*(4!)I", "hQh">;
505 ////////////////////////////////////////////////////////////////////////////////
506 // E.3.16 Extract lanes from a vector
507 let InstName = "vmov" in
508 def VGET_LANE : IInst<"vget_lane", "1.I",
509 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
511 ////////////////////////////////////////////////////////////////////////////////
512 // E.3.17 Set lanes within a vector
513 let InstName = "vmov" in
514 def VSET_LANE : IInst<"vset_lane", ".1.I",
515 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
517 ////////////////////////////////////////////////////////////////////////////////
518 // E.3.18 Initialize a vector from bit pattern
519 def VCREATE : NoTestOpInst<"vcreate", ".(IU>)", "csihfUcUsUiUlPcPsl", OP_CAST> {
520 let BigEndianSafe = 1;
523 ////////////////////////////////////////////////////////////////////////////////
524 // E.3.19 Set all lanes to same value
525 let InstName = "vmov" in {
526 def VDUP_N : WOpInst<"vdup_n", ".1",
527 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
529 def VMOV_N : WOpInst<"vmov_n", ".1",
530 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl",
534 def VDUP_LANE: WOpInst<"vdup_lane", ".qI",
535 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
538 ////////////////////////////////////////////////////////////////////////////////
539 // E.3.20 Combining vectors
540 def VCOMBINE : NoTestOpInst<"vcombine", "Q..", "csilhfUcUsUiUlPcPs", OP_CONC>;
542 ////////////////////////////////////////////////////////////////////////////////
543 // E.3.21 Splitting vectors
544 // Note that the ARM NEON Reference 2.0 mistakenly document the vget_high_f16()
545 // and vget_low_f16() intrinsics as AArch64-only. We (and GCC) support all
546 // versions of these intrinsics in both AArch32 and AArch64 architectures. See
547 // D45668 for more details.
548 let InstName = "vmov" in {
549 def VGET_HIGH : NoTestOpInst<"vget_high", ".Q", "csilhfUcUsUiUlPcPs", OP_HI>;
550 def VGET_LOW : NoTestOpInst<"vget_low", ".Q", "csilhfUcUsUiUlPcPs", OP_LO>;
553 ////////////////////////////////////////////////////////////////////////////////
554 // E.3.22 Converting vectors
556 let ArchGuard = "(__ARM_FP & 2)" in {
557 def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "(<q)(.!)", "Hf">;
558 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "(>Q)(.!)", "h">;
561 def VCVT_S32 : SInst<"vcvt_s32", "S.", "fQf">;
562 def VCVT_U32 : SInst<"vcvt_u32", "U.", "fQf">;
563 def VCVT_F32 : SInst<"vcvt_f32", "F(.!)", "iUiQiQUi">;
564 let isVCVT_N = 1 in {
565 def VCVT_N_S32 : SInst<"vcvt_n_s32", "S.I", "fQf">;
566 def VCVT_N_U32 : SInst<"vcvt_n_u32", "U.I", "fQf">;
567 def VCVT_N_F32 : SInst<"vcvt_n_f32", "F(.!)I", "iUiQiQUi">;
570 def VMOVN : IInst<"vmovn", "<Q", "silUsUiUl">;
571 def VMOVL : SInst<"vmovl", "(>Q).", "csiUcUsUi">;
572 def VQMOVN : SInst<"vqmovn", "<Q", "silUsUiUl">;
573 def VQMOVUN : SInst<"vqmovun", "(<U)Q", "sil">;
575 ////////////////////////////////////////////////////////////////////////////////
576 // E.3.23-24 Table lookup, Extended table lookup
577 let InstName = "vtbl" in {
578 def VTBL1 : WInst<"vtbl1", "..p", "UccPc">;
579 def VTBL2 : WInst<"vtbl2", ".2p", "UccPc">;
580 def VTBL3 : WInst<"vtbl3", ".3p", "UccPc">;
581 def VTBL4 : WInst<"vtbl4", ".4p", "UccPc">;
583 let InstName = "vtbx" in {
584 def VTBX1 : WInst<"vtbx1", "...p", "UccPc">;
585 def VTBX2 : WInst<"vtbx2", "..2p", "UccPc">;
586 def VTBX3 : WInst<"vtbx3", "..3p", "UccPc">;
587 def VTBX4 : WInst<"vtbx4", "..4p", "UccPc">;
590 ////////////////////////////////////////////////////////////////////////////////
591 // E.3.25 Operations with a scalar value
592 def VMLA_LANE : IOpInst<"vmla_lane", "...qI",
593 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
594 def VMLAL_LANE : SOpInst<"vmlal_lane", "(>Q)(>Q)..I", "siUsUi", OP_MLAL_LN>;
595 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "(>Q)(>Q)..I", "si", OP_QDMLAL_LN>;
596 def VMLS_LANE : IOpInst<"vmls_lane", "...qI",
597 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
598 def VMLSL_LANE : SOpInst<"vmlsl_lane", "(>Q)(>Q)..I", "siUsUi", OP_MLSL_LN>;
599 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "(>Q)(>Q)..I", "si", OP_QDMLSL_LN>;
600 def VMUL_N : IOpInst<"vmul_n", "..1", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
601 def VMUL_LANE : IOpInst<"vmul_lane", "..qI",
602 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
603 def VMULL_N : SOpInst<"vmull_n", "(>Q).1", "siUsUi", OP_MULL_N>;
604 def VMULL_LANE : SOpInst<"vmull_lane", "(>Q)..I", "siUsUi", OP_MULL_LN>;
605 def VQDMULL_N : SOpInst<"vqdmull_n", "(>Q).1", "si", OP_QDMULL_N>;
606 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "(>Q)..I", "si", OP_QDMULL_LN>;
607 def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>;
608 def VQRDMULH_N : SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>;
610 let ArchGuard = "!defined(__aarch64__)" in {
611 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
612 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
614 let ArchGuard = "defined(__aarch64__)" in {
615 def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
616 def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
619 let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
620 def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "...qI", "siQsQi", OP_QRDMLAH_LN>;
621 def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "...qI", "siQsQi", OP_QRDMLSH_LN>;
624 def VMLA_N : IOpInst<"vmla_n", "...1", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
625 def VMLAL_N : SOpInst<"vmlal_n", "(>Q)(>Q).1", "siUsUi", OP_MLAL_N>;
626 def VQDMLAL_N : SOpInst<"vqdmlal_n", "(>Q)(>Q).1", "si", OP_QDMLAL_N>;
627 def VMLS_N : IOpInst<"vmls_n", "...1", "siUsUifQsQiQUsQUiQf", OP_MLS_N>;
628 def VMLSL_N : SOpInst<"vmlsl_n", "(>Q)(>Q).1", "siUsUi", OP_MLSL_N>;
629 def VQDMLSL_N : SOpInst<"vqdmlsl_n", "(>Q)(>Q).1", "si", OP_QDMLSL_N>;
631 ////////////////////////////////////////////////////////////////////////////////
632 // E.3.26 Vector Extract
633 def VEXT : WInst<"vext", "...I",
634 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
636 ////////////////////////////////////////////////////////////////////////////////
637 // E.3.27 Reverse vector elements
638 def VREV64 : WOpInst<"vrev64", "..", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
640 def VREV32 : WOpInst<"vrev32", "..", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
641 def VREV16 : WOpInst<"vrev16", "..", "cUcPcQcQUcQPc", OP_REV16>;
643 ////////////////////////////////////////////////////////////////////////////////
644 // E.3.28 Other single operand arithmetic
645 def VABS : SInst<"vabs", "..", "csifQcQsQiQf">;
646 def VQABS : SInst<"vqabs", "..", "csiQcQsQi">;
647 def VNEG : SOpInst<"vneg", "..", "csifQcQsQiQf", OP_NEG>;
648 def VQNEG : SInst<"vqneg", "..", "csiQcQsQi">;
649 def VCLS : SInst<"vcls", "..", "csiQcQsQi">;
650 def VCLZ : IInst<"vclz", "..", "csiUcUsUiQcQsQiQUcQUsQUi">;
651 def VCNT : WInst<"vcnt", "..", "UccPcQUcQcQPc">;
652 def VRECPE : SInst<"vrecpe", "..", "fUiQfQUi">;
653 def VRSQRTE : SInst<"vrsqrte", "..", "fUiQfQUi">;
655 ////////////////////////////////////////////////////////////////////////////////
656 // E.3.29 Logical operations
657 def VMVN : LOpInst<"vmvn", "..", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
658 def VAND : LOpInst<"vand", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
659 def VORR : LOpInst<"vorr", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
660 def VEOR : LOpInst<"veor", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
661 def VBIC : LOpInst<"vbic", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
662 def VORN : LOpInst<"vorn", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
663 let isHiddenLInst = 1 in
664 def VBSL : SInst<"vbsl", ".U..",
665 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
667 ////////////////////////////////////////////////////////////////////////////////
668 // E.3.30 Transposition operations
669 def VTRN : WInst<"vtrn", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
670 def VZIP : WInst<"vzip", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
671 def VUZP : WInst<"vuzp", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
673 ////////////////////////////////////////////////////////////////////////////////
675 class REINTERPRET_CROSS_SELF<string Types> :
676 NoTestOpInst<"vreinterpret", "..", Types, OP_REINT> {
677 let CartesianProductWith = Types;
680 multiclass REINTERPRET_CROSS_TYPES<string TypesA, string TypesB> {
681 def AXB: NoTestOpInst<"vreinterpret", "..", TypesA, OP_REINT> {
682 let CartesianProductWith = TypesB;
684 def BXA: NoTestOpInst<"vreinterpret", "..", TypesB, OP_REINT> {
685 let CartesianProductWith = TypesA;
689 // E.3.31 Vector reinterpret cast operations
690 def VREINTERPRET : REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs"> {
691 let ArchGuard = "!defined(__aarch64__)";
692 let BigEndianSafe = 1;
695 ////////////////////////////////////////////////////////////////////////////////
696 // Vector fused multiply-add operations
698 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
699 def VFMA : SInst<"vfma", "....", "fQf">;
700 def VFMS : SOpInst<"vfms", "....", "fQf", OP_FMLS>;
701 def FMLA_N_F32 : SOpInst<"vfma_n", "...1", "fQf", OP_FMLA_N>;
704 ////////////////////////////////////////////////////////////////////////////////
705 // fp16 vector operations
706 def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "1.I", "h", OP_SCALAR_HALF_GET_LN>;
707 def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", ".1.I", "h", OP_SCALAR_HALF_SET_LN>;
708 def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "1.I", "Qh", OP_SCALAR_HALF_GET_LNQ>;
709 def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", ".1.I", "Qh", OP_SCALAR_HALF_SET_LNQ>;
711 ////////////////////////////////////////////////////////////////////////////////
712 // AArch64 Intrinsics
714 let ArchGuard = "defined(__aarch64__)" in {
716 ////////////////////////////////////////////////////////////////////////////////
718 def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPl">;
719 def LD2 : WInst<"vld2", "2(c*!)", "QUlQldQdPlQPl">;
720 def LD3 : WInst<"vld3", "3(c*!)", "QUlQldQdPlQPl">;
721 def LD4 : WInst<"vld4", "4(c*!)", "QUlQldQdPlQPl">;
722 def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">;
723 def ST2 : WInst<"vst2", "v*(2!)", "QUlQldQdPlQPl">;
724 def ST3 : WInst<"vst3", "v*(3!)", "QUlQldQdPlQPl">;
725 def ST4 : WInst<"vst4", "v*(4!)", "QUlQldQdPlQPl">;
727 def LD1_X2 : WInst<"vld1_x2", "2(c*!)",
729 def LD1_X3 : WInst<"vld1_x3", "3(c*!)",
731 def LD1_X4 : WInst<"vld1_x4", "4(c*!)",
734 def ST1_X2 : WInst<"vst1_x2", "v*(2!)", "dQdPlQPl">;
735 def ST1_X3 : WInst<"vst1_x3", "v*(3!)", "dQdPlQPl">;
736 def ST1_X4 : WInst<"vst1_x4", "v*(4!)", "dQdPlQPl">;
738 def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPl">;
739 def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPl">;
740 def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPl">;
741 def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPl">;
742 def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPl">;
743 def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
744 def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
745 def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
747 def LD1_DUP : WInst<"vld1_dup", ".(c*!)", "dQdPlQPl">;
748 def LD2_DUP : WInst<"vld2_dup", "2(c*!)", "dQdPlQPl">;
749 def LD3_DUP : WInst<"vld3_dup", "3(c*!)", "dQdPlQPl">;
750 def LD4_DUP : WInst<"vld4_dup", "4(c*!)", "dQdPlQPl">;
752 def VLDRQ : WInst<"vldrq", "1(c*!)", "Pk">;
753 def VSTRQ : WInst<"vstrq", "v*(1!)", "Pk">;
755 ////////////////////////////////////////////////////////////////////////////////
757 def ADD : IOpInst<"vadd", "...", "dQd", OP_ADD>;
759 ////////////////////////////////////////////////////////////////////////////////
761 def SUB : IOpInst<"vsub", "...", "dQd", OP_SUB>;
763 ////////////////////////////////////////////////////////////////////////////////
765 def MUL : IOpInst<"vmul", "...", "dQd", OP_MUL>;
766 def MLA : IOpInst<"vmla", "....", "dQd", OP_MLA>;
767 def MLS : IOpInst<"vmls", "....", "dQd", OP_MLS>;
769 ////////////////////////////////////////////////////////////////////////////////
770 // Multiplication Extended
771 def MULX : SInst<"vmulx", "...", "fdQfQd">;
773 ////////////////////////////////////////////////////////////////////////////////
775 def FDIV : IOpInst<"vdiv", "...", "fdQfQd", OP_DIV>;
777 ////////////////////////////////////////////////////////////////////////////////
778 // Vector fused multiply-add operations
779 def FMLA : SInst<"vfma", "....", "dQd">;
780 def FMLS : SOpInst<"vfms", "....", "dQd", OP_FMLS>;
782 ////////////////////////////////////////////////////////////////////////////////
783 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
784 def VMUL_N_A64 : IOpInst<"vmul_n", "..1", "Qd", OP_MUL_N>;
786 def FMLA_N : SOpInst<"vfma_n", "...1", "dQd", OP_FMLA_N>;
787 def FMLS_N : SOpInst<"vfms_n", "...1", "fdQfQd", OP_FMLS_N>;
789 def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>;
790 def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>;
792 ////////////////////////////////////////////////////////////////////////////////
793 // Logical operations
794 def BSL : SInst<"vbsl", ".U..", "dPlQdQPl">;
796 ////////////////////////////////////////////////////////////////////////////////
797 // Absolute Difference
798 def ABD : SInst<"vabd", "...", "dQd">;
800 ////////////////////////////////////////////////////////////////////////////////
801 // saturating absolute/negate
802 def ABS : SInst<"vabs", "..", "dQdlQl">;
803 def QABS : SInst<"vqabs", "..", "lQl">;
804 def NEG : SOpInst<"vneg", "..", "dlQdQl", OP_NEG>;
805 def QNEG : SInst<"vqneg", "..", "lQl">;
807 ////////////////////////////////////////////////////////////////////////////////
808 // Signed Saturating Accumulated of Unsigned Value
809 def SUQADD : SInst<"vuqadd", "..U", "csilQcQsQiQl">;
811 ////////////////////////////////////////////////////////////////////////////////
812 // Unsigned Saturating Accumulated of Signed Value
813 def USQADD : SInst<"vsqadd", "..S", "UcUsUiUlQUcQUsQUiQUl">;
815 ////////////////////////////////////////////////////////////////////////////////
817 def FRECPS : IInst<"vrecps", "...", "dQd">;
818 def FRSQRTS : IInst<"vrsqrts", "...", "dQd">;
819 def FRECPE : SInst<"vrecpe", "..", "dQd">;
820 def FRSQRTE : SInst<"vrsqrte", "..", "dQd">;
821 def FSQRT : SInst<"vsqrt", "..", "fdQfQd">;
823 ////////////////////////////////////////////////////////////////////////////////
825 def RBIT : IInst<"vrbit", "..", "cUcPcQcQUcQPc">;
827 ////////////////////////////////////////////////////////////////////////////////
828 // Integer extract and narrow to high
829 def XTN2 : SOpInst<"vmovn_high", "(<Q)<Q", "silUsUiUl", OP_XTN>;
831 ////////////////////////////////////////////////////////////////////////////////
832 // Signed integer saturating extract and unsigned narrow to high
833 def SQXTUN2 : SOpInst<"vqmovun_high", "(<U)(<q).", "HsHiHl", OP_SQXTUN>;
835 ////////////////////////////////////////////////////////////////////////////////
836 // Integer saturating extract and narrow to high
837 def QXTN2 : SOpInst<"vqmovn_high", "(<Q)<Q", "silUsUiUl", OP_QXTN>;
839 ////////////////////////////////////////////////////////////////////////////////
840 // Converting vectors
842 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "(<q).", "Qd">;
843 def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "(>Q).", "f">;
845 def VCVT_S64 : SInst<"vcvt_s64", "S.", "dQd">;
846 def VCVT_U64 : SInst<"vcvt_u64", "U.", "dQd">;
847 def VCVT_F64 : SInst<"vcvt_f64", "F(.!)", "lUlQlQUl">;
849 def VCVT_HIGH_F16_F32 : SOpInst<"vcvt_high_f16", "<(<q!)Q", "Hf", OP_VCVT_NA_HI_F16>;
850 def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "(>Q)(Q!)", "h", OP_VCVT_EX_HI_F32>;
851 def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "(<Q)(F<!)Q", "d", OP_VCVT_NA_HI_F32>;
852 def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "(>Q)(Q!)", "f", OP_VCVT_EX_HI_F64>;
854 def VCVTX_F32_F64 : SInst<"vcvtx_f32", "(F<)(Q!)", "d">;
855 def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "(<Q)(F<!)Q", "d", OP_VCVTX_HI>;
857 ////////////////////////////////////////////////////////////////////////////////
859 def FCAGE : IInst<"vcage", "U..", "dQd">;
860 def FCAGT : IInst<"vcagt", "U..", "dQd">;
861 def FCALE : IInst<"vcale", "U..", "dQd">;
862 def FCALT : IInst<"vcalt", "U..", "dQd">;
863 def CMTST : WInst<"vtst", "U..", "lUlPlQlQUlQPl">;
864 def CFMEQ : SOpInst<"vceq", "U..", "lUldQdQlQUlPlQPl", OP_EQ>;
865 def CFMGE : SOpInst<"vcge", "U..", "lUldQdQlQUl", OP_GE>;
866 def CFMLE : SOpInst<"vcle", "U..", "lUldQdQlQUl", OP_LE>;
867 def CFMGT : SOpInst<"vcgt", "U..", "lUldQdQlQUl", OP_GT>;
868 def CFMLT : SOpInst<"vclt", "U..", "lUldQdQlQUl", OP_LT>;
870 def CMEQ : SInst<"vceqz", "U.",
871 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
872 def CMGE : SInst<"vcgez", "U.", "csilfdQcQsQiQlQfQd">;
873 def CMLE : SInst<"vclez", "U.", "csilfdQcQsQiQlQfQd">;
874 def CMGT : SInst<"vcgtz", "U.", "csilfdQcQsQiQlQfQd">;
875 def CMLT : SInst<"vcltz", "U.", "csilfdQcQsQiQlQfQd">;
877 ////////////////////////////////////////////////////////////////////////////////
879 def MAX : SInst<"vmax", "...", "dQd">;
880 def MIN : SInst<"vmin", "...", "dQd">;
882 ////////////////////////////////////////////////////////////////////////////////
884 def MAXP : SInst<"vpmax", "...", "QcQsQiQUcQUsQUiQfQd">;
885 def MINP : SInst<"vpmin", "...", "QcQsQiQUcQUsQUiQfQd">;
887 ////////////////////////////////////////////////////////////////////////////////
888 // Pairwise MaxNum/MinNum Floating Point
889 def FMAXNMP : SInst<"vpmaxnm", "...", "fQfQd">;
890 def FMINNMP : SInst<"vpminnm", "...", "fQfQd">;
892 ////////////////////////////////////////////////////////////////////////////////
894 def ADDP : IInst<"vpadd", "...", "QcQsQiQlQUcQUsQUiQUlQfQd">;
896 ////////////////////////////////////////////////////////////////////////////////
897 // Shifts by constant
899 // Left shift long high
900 def SHLL_HIGH_N : SOpInst<"vshll_high_n", ">.I", "HcHsHiHUcHUsHUi",
903 ////////////////////////////////////////////////////////////////////////////////
904 def SRI_N : WInst<"vsri_n", "...I", "PlQPl">;
905 def SLI_N : WInst<"vsli_n", "...I", "PlQPl">;
907 // Right shift narrow high
908 def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "<(<q).I",
909 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
910 def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "<(<q).I",
911 "HsHiHl", OP_NARROW_HI>;
912 def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "<(<q).I",
913 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
914 def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "<(<q).I",
915 "HsHiHl", OP_NARROW_HI>;
916 def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "<(<q).I",
917 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
918 def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "<(<q).I",
919 "HsHiHlHUsHUiHUl", OP_NARROW_HI>;
922 ////////////////////////////////////////////////////////////////////////////////
923 // Converting vectors
924 def VMOVL_HIGH : SOpInst<"vmovl_high", ">.", "HcHsHiHUcHUsHUi", OP_MOVL_HI>;
926 let isVCVT_N = 1 in {
927 def CVTF_N_F64 : SInst<"vcvt_n_f64", "F(.!)I", "lUlQlQUl">;
928 def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "S.I", "dQd">;
929 def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "U.I", "dQd">;
932 ////////////////////////////////////////////////////////////////////////////////
933 // 3VDiff class using high 64-bit in operands
934 def VADDL_HIGH : SOpInst<"vaddl_high", "(>Q)QQ", "csiUcUsUi", OP_ADDLHi>;
935 def VADDW_HIGH : SOpInst<"vaddw_high", "(>Q)(>Q)Q", "csiUcUsUi", OP_ADDWHi>;
936 def VSUBL_HIGH : SOpInst<"vsubl_high", "(>Q)QQ", "csiUcUsUi", OP_SUBLHi>;
937 def VSUBW_HIGH : SOpInst<"vsubw_high", "(>Q)(>Q)Q", "csiUcUsUi", OP_SUBWHi>;
939 def VABDL_HIGH : SOpInst<"vabdl_high", "(>Q)QQ", "csiUcUsUi", OP_ABDLHi>;
940 def VABAL_HIGH : SOpInst<"vabal_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_ABALHi>;
942 def VMULL_HIGH : SOpInst<"vmull_high", "(>Q)QQ", "csiUcUsUiPc", OP_MULLHi>;
943 def VMULL_HIGH_N : SOpInst<"vmull_high_n", "(>Q)Q1", "siUsUi", OP_MULLHi_N>;
944 def VMLAL_HIGH : SOpInst<"vmlal_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_MLALHi>;
945 def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "(>Q)(>Q)Q1", "siUsUi", OP_MLALHi_N>;
946 def VMLSL_HIGH : SOpInst<"vmlsl_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_MLSLHi>;
947 def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "(>Q)(>Q)Q1", "siUsUi", OP_MLSLHi_N>;
949 def VADDHN_HIGH : SOpInst<"vaddhn_high", "(<Q)<QQ", "silUsUiUl", OP_ADDHNHi>;
950 def VRADDHN_HIGH : SOpInst<"vraddhn_high", "(<Q)<QQ", "silUsUiUl", OP_RADDHNHi>;
951 def VSUBHN_HIGH : SOpInst<"vsubhn_high", "(<Q)<QQ", "silUsUiUl", OP_SUBHNHi>;
952 def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "(<Q)<QQ", "silUsUiUl", OP_RSUBHNHi>;
954 def VQDMULL_HIGH : SOpInst<"vqdmull_high", "(>Q)QQ", "si", OP_QDMULLHi>;
955 def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "(>Q)Q1", "si", OP_QDMULLHi_N>;
956 def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "(>Q)(>Q)QQ", "si", OP_QDMLALHi>;
957 def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLALHi_N>;
958 def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "(>Q)(>Q)QQ", "si", OP_QDMLSLHi>;
959 def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLSLHi_N>;
960 def VMULL_P64 : SInst<"vmull", "(1>)11", "Pl">;
961 def VMULL_HIGH_P64 : SOpInst<"vmull_high", "(1>)..", "HPl", OP_MULLHi_P64>;
964 ////////////////////////////////////////////////////////////////////////////////
965 // Extract or insert element from vector
966 def GET_LANE : IInst<"vget_lane", "1.I", "dQdPlQPl">;
967 def SET_LANE : IInst<"vset_lane", ".1.I", "dQdPlQPl">;
968 def COPY_LANE : IOpInst<"vcopy_lane", "..I.I",
969 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>;
970 def COPYQ_LANE : IOpInst<"vcopy_lane", "..IqI",
971 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
972 def COPY_LANEQ : IOpInst<"vcopy_laneq", "..IQI",
973 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN> {
976 def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "..I.I",
977 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN> {
981 ////////////////////////////////////////////////////////////////////////////////
982 // Set all lanes to same value
983 def VDUP_LANE1: WOpInst<"vdup_lane", ".qI", "hdQhQdPlQPl", OP_DUP_LN>;
984 def VDUP_LANE2: WOpInst<"vdup_laneq", ".QI",
985 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
989 def DUP_N : WOpInst<"vdup_n", ".1", "dQdPlQPl", OP_DUP>;
990 def MOV_N : WOpInst<"vmov_n", ".1", "dQdPlQPl", OP_DUP>;
992 ////////////////////////////////////////////////////////////////////////////////
993 def COMBINE : NoTestOpInst<"vcombine", "Q..", "dPl", OP_CONC>;
995 ////////////////////////////////////////////////////////////////////////////////
996 //Initialize a vector from bit pattern
997 def CREATE : NoTestOpInst<"vcreate", ".(IU>)", "dPl", OP_CAST> {
998 let BigEndianSafe = 1;
1001 ////////////////////////////////////////////////////////////////////////////////
1003 def VMLA_LANEQ : IOpInst<"vmla_laneq", "...QI",
1004 "siUsUifQsQiQUsQUiQf", OP_MLA_LN> {
1007 def VMLS_LANEQ : IOpInst<"vmls_laneq", "...QI",
1008 "siUsUifQsQiQUsQUiQf", OP_MLS_LN> {
1012 def VFMA_LANE : IInst<"vfma_lane", "...qI", "fdQfQd">;
1013 def VFMA_LANEQ : IInst<"vfma_laneq", "...QI", "fdQfQd"> {
1016 def VFMS_LANE : IOpInst<"vfms_lane", "...qI", "fdQfQd", OP_FMS_LN>;
1017 def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ> {
1021 def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN> {
1024 def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
1026 def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
1030 def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN> {
1033 def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
1035 def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
1040 def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si", OP_QDMLAL_LN> {
1043 def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "(>Q)(>Q)Q.I", "si",
1045 def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "(>Q)(>Q)QQI", "si",
1049 def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "(>Q)(>Q).QI", "si", OP_QDMLSL_LN> {
1052 def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "(>Q)(>Q)Q.I", "si",
1054 def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "(>Q)(>Q)QQI", "si",
1059 // Newly add double parameter for vmul_lane in aarch64
1060 // Note: d type is handled by SCALAR_VMUL_LANE
1061 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "..qI", "Qd", OP_MUL_LN>;
1063 // Note: d type is handled by SCALAR_VMUL_LANEQ
1064 def VMUL_LANEQ : IOpInst<"vmul_laneq", "..QI",
1065 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN> {
1068 def VMULL_LANEQ : SOpInst<"vmull_laneq", "(>Q).QI", "siUsUi", OP_MULL_LN> {
1071 def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "(>Q)Q.I", "siUsUi",
1073 def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "(>Q)QQI", "siUsUi",
1078 def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(>Q).QI", "si", OP_QDMULL_LN> {
1081 def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "(>Q)Q.I", "si",
1083 def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "(>Q)QQI", "si",
1088 let isLaneQ = 1 in {
1089 def VQDMULH_LANEQ : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
1090 def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
1092 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
1093 def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN> {
1096 def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", OP_QRDMLSH_LN> {
1101 // Note: d type implemented by SCALAR_VMULX_LANE
1102 def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>;
1103 // Note: d type is implemented by SCALAR_VMULX_LANEQ
1104 def VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "fQfQd", OP_MULX_LN> {
1108 ////////////////////////////////////////////////////////////////////////////////
1109 // Across vectors class
1110 def VADDLV : SInst<"vaddlv", "(1>).", "csiUcUsUiQcQsQiQUcQUsQUi">;
1111 def VMAXV : SInst<"vmaxv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
1112 def VMINV : SInst<"vminv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
1113 def VADDV : SInst<"vaddv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
1114 def FMAXNMV : SInst<"vmaxnmv", "1.", "fQfQd">;
1115 def FMINNMV : SInst<"vminnmv", "1.", "fQfQd">;
1117 ////////////////////////////////////////////////////////////////////////////////
1118 // Newly added Vector Extract for f64
1119 def VEXT_A64 : WInst<"vext", "...I", "dQdPlQPl">;
1121 ////////////////////////////////////////////////////////////////////////////////
1123 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
1124 def AESE : SInst<"vaese", "...", "QUc">;
1125 def AESD : SInst<"vaesd", "...", "QUc">;
1126 def AESMC : SInst<"vaesmc", "..", "QUc">;
1127 def AESIMC : SInst<"vaesimc", "..", "QUc">;
1129 def SHA1H : SInst<"vsha1h", "11", "Ui">;
1130 def SHA1SU1 : SInst<"vsha1su1", "...", "QUi">;
1131 def SHA256SU0 : SInst<"vsha256su0", "...", "QUi">;
1133 def SHA1C : SInst<"vsha1c", "..1.", "QUi">;
1134 def SHA1P : SInst<"vsha1p", "..1.", "QUi">;
1135 def SHA1M : SInst<"vsha1m", "..1.", "QUi">;
1136 def SHA1SU0 : SInst<"vsha1su0", "....", "QUi">;
1137 def SHA256H : SInst<"vsha256h", "....", "QUi">;
1138 def SHA256H2 : SInst<"vsha256h2", "....", "QUi">;
1139 def SHA256SU1 : SInst<"vsha256su1", "....", "QUi">;
1142 ////////////////////////////////////////////////////////////////////////////////
1143 // Float -> Int conversions with explicit rounding mode
1145 let ArchGuard = "__ARM_ARCH >= 8" in {
1146 def FCVTNS_S32 : SInst<"vcvtn_s32", "S.", "fQf">;
1147 def FCVTNU_S32 : SInst<"vcvtn_u32", "U.", "fQf">;
1148 def FCVTPS_S32 : SInst<"vcvtp_s32", "S.", "fQf">;
1149 def FCVTPU_S32 : SInst<"vcvtp_u32", "U.", "fQf">;
1150 def FCVTMS_S32 : SInst<"vcvtm_s32", "S.", "fQf">;
1151 def FCVTMU_S32 : SInst<"vcvtm_u32", "U.", "fQf">;
1152 def FCVTAS_S32 : SInst<"vcvta_s32", "S.", "fQf">;
1153 def FCVTAU_S32 : SInst<"vcvta_u32", "U.", "fQf">;
1156 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
1157 def FCVTNS_S64 : SInst<"vcvtn_s64", "S.", "dQd">;
1158 def FCVTNU_S64 : SInst<"vcvtn_u64", "U.", "dQd">;
1159 def FCVTPS_S64 : SInst<"vcvtp_s64", "S.", "dQd">;
1160 def FCVTPU_S64 : SInst<"vcvtp_u64", "U.", "dQd">;
1161 def FCVTMS_S64 : SInst<"vcvtm_s64", "S.", "dQd">;
1162 def FCVTMU_S64 : SInst<"vcvtm_u64", "U.", "dQd">;
1163 def FCVTAS_S64 : SInst<"vcvta_s64", "S.", "dQd">;
1164 def FCVTAU_S64 : SInst<"vcvta_u64", "U.", "dQd">;
1167 ////////////////////////////////////////////////////////////////////////////////
1168 // Round to Integral
1170 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1171 def FRINTN_S32 : SInst<"vrndn", "..", "fQf">;
1172 def FRINTA_S32 : SInst<"vrnda", "..", "fQf">;
1173 def FRINTP_S32 : SInst<"vrndp", "..", "fQf">;
1174 def FRINTM_S32 : SInst<"vrndm", "..", "fQf">;
1175 def FRINTX_S32 : SInst<"vrndx", "..", "fQf">;
1176 def FRINTZ_S32 : SInst<"vrnd", "..", "fQf">;
1177 def FRINTI_S32 : SInst<"vrndi", "..", "fQf">;
1180 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1181 def FRINTN_S64 : SInst<"vrndn", "..", "dQd">;
1182 def FRINTA_S64 : SInst<"vrnda", "..", "dQd">;
1183 def FRINTP_S64 : SInst<"vrndp", "..", "dQd">;
1184 def FRINTM_S64 : SInst<"vrndm", "..", "dQd">;
1185 def FRINTX_S64 : SInst<"vrndx", "..", "dQd">;
1186 def FRINTZ_S64 : SInst<"vrnd", "..", "dQd">;
1187 def FRINTI_S64 : SInst<"vrndi", "..", "dQd">;
1190 ////////////////////////////////////////////////////////////////////////////////
1191 // MaxNum/MinNum Floating Point
1193 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1194 def FMAXNM_S32 : SInst<"vmaxnm", "...", "fQf">;
1195 def FMINNM_S32 : SInst<"vminnm", "...", "fQf">;
1198 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1199 def FMAXNM_S64 : SInst<"vmaxnm", "...", "dQd">;
1200 def FMINNM_S64 : SInst<"vminnm", "...", "dQd">;
1203 ////////////////////////////////////////////////////////////////////////////////
1205 def VTRN1 : SOpInst<"vtrn1", "...",
1206 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>;
1207 def VZIP1 : SOpInst<"vzip1", "...",
1208 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>;
1209 def VUZP1 : SOpInst<"vuzp1", "...",
1210 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>;
1211 def VTRN2 : SOpInst<"vtrn2", "...",
1212 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>;
1213 def VZIP2 : SOpInst<"vzip2", "...",
1214 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>;
1215 def VUZP2 : SOpInst<"vuzp2", "...",
1216 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>;
1218 ////////////////////////////////////////////////////////////////////////////////
1220 let InstName = "vtbl" in {
1221 def VQTBL1_A64 : WInst<"vqtbl1", ".QU", "UccPcQUcQcQPc">;
1222 def VQTBL2_A64 : WInst<"vqtbl2", ".(2Q)U", "UccPcQUcQcQPc">;
1223 def VQTBL3_A64 : WInst<"vqtbl3", ".(3Q)U", "UccPcQUcQcQPc">;
1224 def VQTBL4_A64 : WInst<"vqtbl4", ".(4Q)U", "UccPcQUcQcQPc">;
1226 let InstName = "vtbx" in {
1227 def VQTBX1_A64 : WInst<"vqtbx1", "..QU", "UccPcQUcQcQPc">;
1228 def VQTBX2_A64 : WInst<"vqtbx2", "..(2Q)U", "UccPcQUcQcQPc">;
1229 def VQTBX3_A64 : WInst<"vqtbx3", "..(3Q)U", "UccPcQUcQcQPc">;
1230 def VQTBX4_A64 : WInst<"vqtbx4", "..(4Q)U", "UccPcQUcQcQPc">;
1233 ////////////////////////////////////////////////////////////////////////////////
1234 // Vector reinterpret cast operations
1236 // NeonEmitter implicitly takes the cartesian product of the type string with
1237 // itself during generation so, unlike all other intrinsics, this one should
1238 // include *all* types, not just additional ones.
1239 def VVREINTERPRET : REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk"> {
1240 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)";
1241 let BigEndianSafe = 1;
1244 ////////////////////////////////////////////////////////////////////////////////
1245 // Scalar Intrinsics
1246 // Scalar Arithmetic
1249 def SCALAR_ADD : SInst<"vadd", "111", "SlSUl">;
1250 // Scalar Saturating Add
1251 def SCALAR_QADD : SInst<"vqadd", "111", "ScSsSiSlSUcSUsSUiSUl">;
1253 // Scalar Subtraction
1254 def SCALAR_SUB : SInst<"vsub", "111", "SlSUl">;
1255 // Scalar Saturating Sub
1256 def SCALAR_QSUB : SInst<"vqsub", "111", "ScSsSiSlSUcSUsSUiSUl">;
1258 let InstName = "vmov" in {
1259 def VGET_HIGH_A64 : NoTestOpInst<"vget_high", ".Q", "dPl", OP_HI>;
1260 def VGET_LOW_A64 : NoTestOpInst<"vget_low", ".Q", "dPl", OP_LO>;
1263 ////////////////////////////////////////////////////////////////////////////////
1265 // Scalar Shift Left
1266 def SCALAR_SHL: SInst<"vshl", "111", "SlSUl">;
1267 // Scalar Saturating Shift Left
1268 def SCALAR_QSHL: SInst<"vqshl", "111", "ScSsSiSlSUcSUsSUiSUl">;
1269 // Scalar Saturating Rounding Shift Left
1270 def SCALAR_QRSHL: SInst<"vqrshl", "111", "ScSsSiSlSUcSUsSUiSUl">;
1271 // Scalar Shift Rounding Left
1272 def SCALAR_RSHL: SInst<"vrshl", "111", "SlSUl">;
1274 ////////////////////////////////////////////////////////////////////////////////
1275 // Scalar Shift (Immediate)
1276 let isScalarShift = 1 in {
1277 // Signed/Unsigned Shift Right (Immediate)
1278 def SCALAR_SSHR_N: SInst<"vshr_n", "11I", "SlSUl">;
1279 // Signed/Unsigned Rounding Shift Right (Immediate)
1280 def SCALAR_SRSHR_N: SInst<"vrshr_n", "11I", "SlSUl">;
1282 // Signed/Unsigned Shift Right and Accumulate (Immediate)
1283 def SCALAR_SSRA_N: SInst<"vsra_n", "111I", "SlSUl">;
1284 // Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
1285 def SCALAR_SRSRA_N: SInst<"vrsra_n", "111I", "SlSUl">;
1287 // Shift Left (Immediate)
1288 def SCALAR_SHL_N: SInst<"vshl_n", "11I", "SlSUl">;
1289 // Signed/Unsigned Saturating Shift Left (Immediate)
1290 def SCALAR_SQSHL_N: SInst<"vqshl_n", "11I", "ScSsSiSlSUcSUsSUiSUl">;
1291 // Signed Saturating Shift Left Unsigned (Immediate)
1292 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "11I", "ScSsSiSl">;
1294 // Shift Right And Insert (Immediate)
1295 def SCALAR_SRI_N: SInst<"vsri_n", "111I", "SlSUl">;
1296 // Shift Left And Insert (Immediate)
1297 def SCALAR_SLI_N: SInst<"vsli_n", "111I", "SlSUl">;
1299 let isScalarNarrowShift = 1 in {
1300 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
1301 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">;
1302 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
1303 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">;
1304 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
1305 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1<)1I", "SsSiSl">;
1306 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
1307 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1<)1I", "SsSiSl">;
1310 ////////////////////////////////////////////////////////////////////////////////
1311 // Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate)
1312 def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "(1F)(1!)I", "SiSUi">;
1313 def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "(1F)(1!)I", "SlSUl">;
1315 ////////////////////////////////////////////////////////////////////////////////
1316 // Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate)
1317 def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "(1S)1I", "Sf">;
1318 def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "(1U)1I", "Sf">;
1319 def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "(1S)1I", "Sd">;
1320 def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "(1U)1I", "Sd">;
1323 ////////////////////////////////////////////////////////////////////////////////
1324 // Scalar Floating-point Round to Integral
1325 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1326 def SCALAR_FRINTN_S32 : SInst<"vrndn", "11", "Sf">;
1329 ////////////////////////////////////////////////////////////////////////////////
1330 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
1331 def SCALAR_ADDP : SInst<"vpadd", "1.", "SfSHlSHdSHUl">;
1333 ////////////////////////////////////////////////////////////////////////////////
1334 // Scalar Reduce Floating Point Pairwise Max/Min
1335 def SCALAR_FMAXP : SInst<"vpmax", "1.", "SfSQd">;
1337 def SCALAR_FMINP : SInst<"vpmin", "1.", "SfSQd">;
1339 ////////////////////////////////////////////////////////////////////////////////
1340 // Scalar Reduce Floating Point Pairwise maxNum/minNum
1341 def SCALAR_FMAXNMP : SInst<"vpmaxnm", "1.", "SfSQd">;
1342 def SCALAR_FMINNMP : SInst<"vpminnm", "1.", "SfSQd">;
1344 ////////////////////////////////////////////////////////////////////////////////
1345 // Scalar Integer Saturating Doubling Multiply Half High
1346 def SCALAR_SQDMULH : SInst<"vqdmulh", "111", "SsSi">;
1348 ////////////////////////////////////////////////////////////////////////////////
1349 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1350 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "111", "SsSi">;
1352 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
1353 ////////////////////////////////////////////////////////////////////////////////
1354 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1355 def SCALAR_SQRDMLAH : SOpInst<"vqrdmlah", "1111", "SsSi", OP_QRDMLAH>;
1357 ////////////////////////////////////////////////////////////////////////////////
1358 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
1359 def SCALAR_SQRDMLSH : SOpInst<"vqrdmlsh", "1111", "SsSi", OP_QRDMLSH>;
1362 ////////////////////////////////////////////////////////////////////////////////
1363 // Scalar Floating-point Multiply Extended
1364 def SCALAR_FMULX : IInst<"vmulx", "111", "SfSd">;
1366 ////////////////////////////////////////////////////////////////////////////////
1367 // Scalar Floating-point Reciprocal Step
1368 def SCALAR_FRECPS : IInst<"vrecps", "111", "SfSd">;
1370 ////////////////////////////////////////////////////////////////////////////////
1371 // Scalar Floating-point Reciprocal Square Root Step
1372 def SCALAR_FRSQRTS : IInst<"vrsqrts", "111", "SfSd">;
1374 ////////////////////////////////////////////////////////////////////////////////
1375 // Scalar Signed Integer Convert To Floating-point
1376 def SCALAR_SCVTFS : SInst<"vcvt_f32", "(1F)(1!)", "Si">;
1377 def SCALAR_SCVTFD : SInst<"vcvt_f64", "(1F)(1!)", "Sl">;
1379 ////////////////////////////////////////////////////////////////////////////////
1380 // Scalar Unsigned Integer Convert To Floating-point
1381 def SCALAR_UCVTFS : SInst<"vcvt_f32", "(1F)(1!)", "SUi">;
1382 def SCALAR_UCVTFD : SInst<"vcvt_f64", "(1F)(1!)", "SUl">;
1384 ////////////////////////////////////////////////////////////////////////////////
1385 // Scalar Floating-point Converts
1386 def SCALAR_FCVTXN : IInst<"vcvtx_f32", "(1F<)(1!)", "Sd">;
1387 def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "(1S)1", "Sf">;
1388 def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "(1U)1", "Sf">;
1389 def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "(1S)1", "Sd">;
1390 def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "(1U)1", "Sd">;
1391 def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "(1S)1", "Sf">;
1392 def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "(1U)1", "Sf">;
1393 def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "(1S)1", "Sd">;
1394 def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "(1U)1", "Sd">;
1395 def SCALAR_FCVTASS : SInst<"vcvta_s32", "(1S)1", "Sf">;
1396 def SCALAR_FCVTAUS : SInst<"vcvta_u32", "(1U)1", "Sf">;
1397 def SCALAR_FCVTASD : SInst<"vcvta_s64", "(1S)1", "Sd">;
1398 def SCALAR_FCVTAUD : SInst<"vcvta_u64", "(1U)1", "Sd">;
1399 def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "(1S)1", "Sf">;
1400 def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "(1U)1", "Sf">;
1401 def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "(1S)1", "Sd">;
1402 def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "(1U)1", "Sd">;
1403 def SCALAR_FCVTZSS : SInst<"vcvt_s32", "(1S)1", "Sf">;
1404 def SCALAR_FCVTZUS : SInst<"vcvt_u32", "(1U)1", "Sf">;
1405 def SCALAR_FCVTZSD : SInst<"vcvt_s64", "(1S)1", "Sd">;
1406 def SCALAR_FCVTZUD : SInst<"vcvt_u64", "(1U)1", "Sd">;
1408 ////////////////////////////////////////////////////////////////////////////////
1409 // Scalar Floating-point Reciprocal Estimate
1410 def SCALAR_FRECPE : IInst<"vrecpe", "11", "SfSd">;
1412 ////////////////////////////////////////////////////////////////////////////////
1413 // Scalar Floating-point Reciprocal Exponent
1414 def SCALAR_FRECPX : IInst<"vrecpx", "11", "SfSd">;
1416 ////////////////////////////////////////////////////////////////////////////////
1417 // Scalar Floating-point Reciprocal Square Root Estimate
1418 def SCALAR_FRSQRTE : IInst<"vrsqrte", "11", "SfSd">;
1420 ////////////////////////////////////////////////////////////////////////////////
1421 // Scalar Integer Comparison
1422 def SCALAR_CMEQ : SInst<"vceq", "111", "SlSUl">;
1423 def SCALAR_CMEQZ : SInst<"vceqz", "11", "SlSUl">;
1424 def SCALAR_CMGE : SInst<"vcge", "111", "Sl">;
1425 def SCALAR_CMGEZ : SInst<"vcgez", "11", "Sl">;
1426 def SCALAR_CMHS : SInst<"vcge", "111", "SUl">;
1427 def SCALAR_CMLE : SInst<"vcle", "111", "SlSUl">;
1428 def SCALAR_CMLEZ : SInst<"vclez", "11", "Sl">;
1429 def SCALAR_CMLT : SInst<"vclt", "111", "SlSUl">;
1430 def SCALAR_CMLTZ : SInst<"vcltz", "11", "Sl">;
1431 def SCALAR_CMGT : SInst<"vcgt", "111", "Sl">;
1432 def SCALAR_CMGTZ : SInst<"vcgtz", "11", "Sl">;
1433 def SCALAR_CMHI : SInst<"vcgt", "111", "SUl">;
1434 def SCALAR_CMTST : SInst<"vtst", "111", "SlSUl">;
1436 ////////////////////////////////////////////////////////////////////////////////
1437 // Scalar Floating-point Comparison
1438 def SCALAR_FCMEQ : IInst<"vceq", "(1U)11", "SfSd">;
1439 def SCALAR_FCMEQZ : IInst<"vceqz", "(1U)1", "SfSd">;
1440 def SCALAR_FCMGE : IInst<"vcge", "(1U)11", "SfSd">;
1441 def SCALAR_FCMGEZ : IInst<"vcgez", "(1U)1", "SfSd">;
1442 def SCALAR_FCMGT : IInst<"vcgt", "(1U)11", "SfSd">;
1443 def SCALAR_FCMGTZ : IInst<"vcgtz", "(1U)1", "SfSd">;
1444 def SCALAR_FCMLE : IInst<"vcle", "(1U)11", "SfSd">;
1445 def SCALAR_FCMLEZ : IInst<"vclez", "(1U)1", "SfSd">;
1446 def SCALAR_FCMLT : IInst<"vclt", "(1U)11", "SfSd">;
1447 def SCALAR_FCMLTZ : IInst<"vcltz", "(1U)1", "SfSd">;
1449 ////////////////////////////////////////////////////////////////////////////////
1450 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
1451 def SCALAR_FACGE : IInst<"vcage", "(1U)11", "SfSd">;
1452 def SCALAR_FACLE : IInst<"vcale", "(1U)11", "SfSd">;
1454 ////////////////////////////////////////////////////////////////////////////////
1455 // Scalar Floating-point Absolute Compare Mask Greater Than
1456 def SCALAR_FACGT : IInst<"vcagt", "(1U)11", "SfSd">;
1457 def SCALAR_FACLT : IInst<"vcalt", "(1U)11", "SfSd">;
1459 ////////////////////////////////////////////////////////////////////////////////
1460 // Scalar Absolute Value
1461 def SCALAR_ABS : SInst<"vabs", "11", "Sl">;
1463 ////////////////////////////////////////////////////////////////////////////////
1464 // Scalar Absolute Difference
1465 def SCALAR_ABD : IInst<"vabd", "111", "SfSd">;
1467 ////////////////////////////////////////////////////////////////////////////////
1468 // Scalar Signed Saturating Absolute Value
1469 def SCALAR_SQABS : SInst<"vqabs", "11", "ScSsSiSl">;
1471 ////////////////////////////////////////////////////////////////////////////////
1473 def SCALAR_NEG : SInst<"vneg", "11", "Sl">;
1475 ////////////////////////////////////////////////////////////////////////////////
1476 // Scalar Signed Saturating Negate
1477 def SCALAR_SQNEG : SInst<"vqneg", "11", "ScSsSiSl">;
1479 ////////////////////////////////////////////////////////////////////////////////
1480 // Scalar Signed Saturating Accumulated of Unsigned Value
1481 def SCALAR_SUQADD : SInst<"vuqadd", "11(1U)", "ScSsSiSl">;
1483 ////////////////////////////////////////////////////////////////////////////////
1484 // Scalar Unsigned Saturating Accumulated of Signed Value
1485 def SCALAR_USQADD : SInst<"vsqadd", "11(1S)", "SUcSUsSUiSUl">;
1487 ////////////////////////////////////////////////////////////////////////////////
1488 // Signed Saturating Doubling Multiply-Add Long
1489 def SCALAR_SQDMLAL : SInst<"vqdmlal", "(1>)(1>)11", "SsSi">;
1491 ////////////////////////////////////////////////////////////////////////////////
1492 // Signed Saturating Doubling Multiply-Subtract Long
1493 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "(1>)(1>)11", "SsSi">;
1495 ////////////////////////////////////////////////////////////////////////////////
1496 // Signed Saturating Doubling Multiply Long
1497 def SCALAR_SQDMULL : SInst<"vqdmull", "(1>)11", "SsSi">;
1499 ////////////////////////////////////////////////////////////////////////////////
1500 // Scalar Signed Saturating Extract Unsigned Narrow
1501 def SCALAR_SQXTUN : SInst<"vqmovun", "(1<)1", "SsSiSl">;
1503 ////////////////////////////////////////////////////////////////////////////////
1504 // Scalar Signed Saturating Extract Narrow
1505 def SCALAR_SQXTN : SInst<"vqmovn", "(1<)1", "SsSiSl">;
1507 ////////////////////////////////////////////////////////////////////////////////
1508 // Scalar Unsigned Saturating Extract Narrow
1509 def SCALAR_UQXTN : SInst<"vqmovn", "(1<)1", "SUsSUiSUl">;
1511 // Scalar Floating Point multiply (scalar, by element)
1512 def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "11.I", "SfSd", OP_SCALAR_MUL_LN>;
1513 def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "11QI", "SfSd", OP_SCALAR_MUL_LN> {
1517 // Scalar Floating Point multiply extended (scalar, by element)
1518 def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "11.I", "SfSd", OP_SCALAR_MULX_LN>;
1519 def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "11QI", "SfSd", OP_SCALAR_MULX_LN> {
1523 def SCALAR_VMUL_N : IInst<"vmul_n", "..1", "d">;
1525 // VMUL_LANE_A64 d type implemented using scalar mul lane
1526 def SCALAR_VMUL_LANE : IInst<"vmul_lane", "..qI", "d">;
1528 // VMUL_LANEQ d type implemented using scalar mul lane
1529 def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "..QI", "d"> {
1533 // VMULX_LANE d type implemented using scalar vmulx_lane
1534 def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "d", OP_SCALAR_VMULX_LN>;
1536 // VMULX_LANEQ d type implemented using scalar vmulx_laneq
1537 def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "d", OP_SCALAR_VMULX_LNQ> {
1541 // Scalar Floating Point fused multiply-add (scalar, by element)
1542 def SCALAR_FMLA_LANE : IInst<"vfma_lane", "111.I", "SfSd">;
1543 def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "111QI", "SfSd"> {
1547 // Scalar Floating Point fused multiply-subtract (scalar, by element)
1548 def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "111.I", "SfSd", OP_FMS_LN>;
1549 def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "111QI", "SfSd", OP_FMS_LNQ> {
1553 // Signed Saturating Doubling Multiply Long (scalar by element)
1554 def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "(1>)1.I", "SsSi", OP_SCALAR_QDMULL_LN>;
1555 def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(1>)1QI", "SsSi", OP_SCALAR_QDMULL_LN> {
1559 // Signed Saturating Doubling Multiply-Add Long (scalar by element)
1560 def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "(1>)(1>)1.I", "SsSi">;
1561 def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "(1>)(1>)1QI", "SsSi"> {
1565 // Signed Saturating Doubling Multiply-Subtract Long (scalar by element)
1566 def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "(1>)(1>)1.I", "SsSi">;
1567 def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "(1>)(1>)1QI", "SsSi"> {
1571 // Scalar Integer Saturating Doubling Multiply Half High (scalar by element)
1572 def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "11.I", "SsSi", OP_SCALAR_QDMULH_LN>;
1573 def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QDMULH_LN> {
1577 // Scalar Integer Saturating Rounding Doubling Multiply Half High
1578 def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "11.I", "SsSi", OP_SCALAR_QRDMULH_LN>;
1579 def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QRDMULH_LN> {
1583 let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
1584 // Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
1585 def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "111.I", "SsSi", OP_SCALAR_QRDMLAH_LN>;
1586 def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLAH_LN> {
1590 // Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
1591 def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "111.I", "SsSi", OP_SCALAR_QRDMLSH_LN>;
1592 def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLSH_LN> {
1597 def SCALAR_VDUP_LANE : IInst<"vdup_lane", "1.I", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
1598 def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs"> {
1603 // ARMv8.2-A FP16 vector intrinsics for A32/A64.
1604 let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1606 // ARMv8.2-A FP16 one-operand vector intrinsics.
1609 def CMEQH : SInst<"vceqz", "U.", "hQh">;
1610 def CMGEH : SInst<"vcgez", "U.", "hQh">;
1611 def CMGTH : SInst<"vcgtz", "U.", "hQh">;
1612 def CMLEH : SInst<"vclez", "U.", "hQh">;
1613 def CMLTH : SInst<"vcltz", "U.", "hQh">;
1615 // Vector conversion
1616 def VCVT_F16 : SInst<"vcvt_f16", "F(.!)", "sUsQsQUs">;
1617 def VCVT_S16 : SInst<"vcvt_s16", "S.", "hQh">;
1618 def VCVT_U16 : SInst<"vcvt_u16", "U.", "hQh">;
1619 def VCVTA_S16 : SInst<"vcvta_s16", "S.", "hQh">;
1620 def VCVTA_U16 : SInst<"vcvta_u16", "U.", "hQh">;
1621 def VCVTM_S16 : SInst<"vcvtm_s16", "S.", "hQh">;
1622 def VCVTM_U16 : SInst<"vcvtm_u16", "U.", "hQh">;
1623 def VCVTN_S16 : SInst<"vcvtn_s16", "S.", "hQh">;
1624 def VCVTN_U16 : SInst<"vcvtn_u16", "U.", "hQh">;
1625 def VCVTP_S16 : SInst<"vcvtp_s16", "S.", "hQh">;
1626 def VCVTP_U16 : SInst<"vcvtp_u16", "U.", "hQh">;
1629 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1630 def FRINTZH : SInst<"vrnd", "..", "hQh">;
1631 def FRINTNH : SInst<"vrndn", "..", "hQh">;
1632 def FRINTAH : SInst<"vrnda", "..", "hQh">;
1633 def FRINTPH : SInst<"vrndp", "..", "hQh">;
1634 def FRINTMH : SInst<"vrndm", "..", "hQh">;
1635 def FRINTXH : SInst<"vrndx", "..", "hQh">;
1639 def VABSH : SInst<"vabs", "..", "hQh">;
1640 def VNEGH : SOpInst<"vneg", "..", "hQh", OP_NEG>;
1641 def VRECPEH : SInst<"vrecpe", "..", "hQh">;
1642 def FRSQRTEH : SInst<"vrsqrte", "..", "hQh">;
1644 // ARMv8.2-A FP16 two-operands vector intrinsics.
1647 def VADDH : SOpInst<"vadd", "...", "hQh", OP_ADD>;
1648 def VABDH : SInst<"vabd", "...", "hQh">;
1649 def VSUBH : SOpInst<"vsub", "...", "hQh", OP_SUB>;
1652 let InstName = "vacge" in {
1653 def VCAGEH : SInst<"vcage", "U..", "hQh">;
1654 def VCALEH : SInst<"vcale", "U..", "hQh">;
1656 let InstName = "vacgt" in {
1657 def VCAGTH : SInst<"vcagt", "U..", "hQh">;
1658 def VCALTH : SInst<"vcalt", "U..", "hQh">;
1660 def VCEQH : SOpInst<"vceq", "U..", "hQh", OP_EQ>;
1661 def VCGEH : SOpInst<"vcge", "U..", "hQh", OP_GE>;
1662 def VCGTH : SOpInst<"vcgt", "U..", "hQh", OP_GT>;
1663 let InstName = "vcge" in
1664 def VCLEH : SOpInst<"vcle", "U..", "hQh", OP_LE>;
1665 let InstName = "vcgt" in
1666 def VCLTH : SOpInst<"vclt", "U..", "hQh", OP_LT>;
1668 // Vector conversion
1669 let isVCVT_N = 1 in {
1670 def VCVT_N_F16 : SInst<"vcvt_n_f16", "F(.!)I", "sUsQsQUs">;
1671 def VCVT_N_S16 : SInst<"vcvt_n_s16", "S.I", "hQh">;
1672 def VCVT_N_U16 : SInst<"vcvt_n_u16", "U.I", "hQh">;
1676 def VMAXH : SInst<"vmax", "...", "hQh">;
1677 def VMINH : SInst<"vmin", "...", "hQh">;
1678 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1679 def FMAXNMH : SInst<"vmaxnm", "...", "hQh">;
1680 def FMINNMH : SInst<"vminnm", "...", "hQh">;
1683 // Multiplication/Division
1684 def VMULH : SOpInst<"vmul", "...", "hQh", OP_MUL>;
1686 // Pairwise addition
1687 def VPADDH : SInst<"vpadd", "...", "h">;
1690 def VPMAXH : SInst<"vpmax", "...", "h">;
1691 def VPMINH : SInst<"vpmin", "...", "h">;
1694 def VRECPSH : SInst<"vrecps", "...", "hQh">;
1695 def VRSQRTSH : SInst<"vrsqrts", "...", "hQh">;
1697 // ARMv8.2-A FP16 three-operands vector intrinsics.
1699 // Vector fused multiply-add operations
1700 def VFMAH : SInst<"vfma", "....", "hQh">;
1701 def VFMSH : SOpInst<"vfms", "....", "hQh", OP_FMLS>;
1703 // ARMv8.2-A FP16 lane vector intrinsics.
1706 def VMUL_LANEH : IOpInst<"vmul_lane", "..qI", "hQh", OP_MUL_LN>;
1707 def VMUL_NH : IOpInst<"vmul_n", "..1", "hQh", OP_MUL_N>;
1709 // Data processing intrinsics - section 5
1711 // Logical operations
1712 let isHiddenLInst = 1 in
1713 def VBSLH : SInst<"vbsl", ".U..", "hQh">;
1715 // Transposition operations
1716 def VZIPH : WInst<"vzip", "2..", "hQh">;
1717 def VUZPH : WInst<"vuzp", "2..", "hQh">;
1718 def VTRNH : WInst<"vtrn", "2..", "hQh">;
1721 let ArchGuard = "!defined(__aarch64__)" in {
1722 // Set all lanes to same value.
1723 // Already implemented prior to ARMv8.2-A.
1724 def VMOV_NH : WOpInst<"vmov_n", ".1", "hQh", OP_DUP>;
1725 def VDUP_NH : WOpInst<"vdup_n", ".1", "hQh", OP_DUP>;
1726 def VDUP_LANE1H : WOpInst<"vdup_lane", ".qI", "hQh", OP_DUP_LN>;
1730 def VEXTH : WInst<"vext", "...I", "hQh">;
1732 // Reverse vector elements
1733 def VREV64H : WOpInst<"vrev64", "..", "hQh", OP_REV64>;
1736 // ARMv8.2-A FP16 vector intrinsics for A64 only.
1737 let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {
1740 def FRINTIH : SInst<"vrndi", "..", "hQh">;
1743 def FSQRTH : SInst<"vsqrt", "..", "hQh">;
1745 // Multiplication/Division
1746 def MULXH : SInst<"vmulx", "...", "hQh">;
1747 def FDIVH : IOpInst<"vdiv", "...", "hQh", OP_DIV>;
1749 // Pairwise addition
1750 def VPADDH1 : SInst<"vpadd", "...", "Qh">;
1753 def VPMAXH1 : SInst<"vpmax", "...", "Qh">;
1754 def VPMINH1 : SInst<"vpmin", "...", "Qh">;
1756 // Pairwise MaxNum/MinNum
1757 def FMAXNMPH : SInst<"vpmaxnm", "...", "hQh">;
1758 def FMINNMPH : SInst<"vpminnm", "...", "hQh">;
1760 // ARMv8.2-A FP16 lane vector intrinsics.
1763 def VFMA_LANEH : IInst<"vfma_lane", "...qI", "hQh">;
1764 def VFMA_LANEQH : IInst<"vfma_laneq", "...QI", "hQh"> {
1768 // FMA lane with scalar argument
1769 def FMLA_NH : SOpInst<"vfma_n", "...1", "hQh", OP_FMLA_N>;
1770 // Scalar floating point fused multiply-add (scalar, by element)
1771 def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "111.I", "Sh">;
1772 def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "111QI", "Sh"> {
1777 def VFMS_LANEH : IOpInst<"vfms_lane", "...qI", "hQh", OP_FMS_LN>;
1778 def VFMS_LANEQH : IOpInst<"vfms_laneq", "...QI", "hQh", OP_FMS_LNQ> {
1781 // FMS lane with scalar argument
1782 def FMLS_NH : SOpInst<"vfms_n", "...1", "hQh", OP_FMLS_N>;
1783 // Scalar floating foint fused multiply-subtract (scalar, by element)
1784 def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "111.I", "Sh", OP_FMS_LN>;
1785 def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "111QI", "Sh", OP_FMS_LNQ> {
1790 def VMUL_LANEQH : IOpInst<"vmul_laneq", "..QI", "hQh", OP_MUL_LN> {
1793 // Scalar floating point multiply (scalar, by element)
1794 def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "11.I", "Sh", OP_SCALAR_MUL_LN>;
1795 def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "11QI", "Sh", OP_SCALAR_MUL_LN> {
1800 def VMULX_LANEH : IOpInst<"vmulx_lane", "..qI", "hQh", OP_MULX_LN>;
1801 def VMULX_LANEQH : IOpInst<"vmulx_laneq", "..QI", "hQh", OP_MULX_LN> {
1804 def VMULX_NH : IOpInst<"vmulx_n", "..1", "hQh", OP_MULX_N>;
1805 // Scalar floating point mulx (scalar, by element)
1806 def SCALAR_FMULX_LANEH : IInst<"vmulx_lane", "11.I", "Sh">;
1807 def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "11QI", "Sh"> {
1811 // ARMv8.2-A FP16 reduction vector intrinsics.
1812 def VMAXVH : SInst<"vmaxv", "1.", "hQh">;
1813 def VMINVH : SInst<"vminv", "1.", "hQh">;
1814 def FMAXNMVH : SInst<"vmaxnmv", "1.", "hQh">;
1815 def FMINNMVH : SInst<"vminnmv", "1.", "hQh">;
1818 def VTRN1H : SOpInst<"vtrn1", "...", "hQh", OP_TRN1>;
1819 def VZIP1H : SOpInst<"vzip1", "...", "hQh", OP_ZIP1>;
1820 def VUZP1H : SOpInst<"vuzp1", "...", "hQh", OP_UZP1>;
1821 def VTRN2H : SOpInst<"vtrn2", "...", "hQh", OP_TRN2>;
1822 def VZIP2H : SOpInst<"vzip2", "...", "hQh", OP_ZIP2>;
1823 def VUZP2H : SOpInst<"vuzp2", "...", "hQh", OP_UZP2>;
1825 def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "1.I", "Sh">;
1826 def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "1QI", "Sh"> {
1831 // v8.2-A dot product instructions.
1832 let ArchGuard = "defined(__ARM_FEATURE_DOTPROD)" in {
1833 def DOT : SInst<"vdot", "..(<<)(<<)", "iQiUiQUi">;
1834 def DOT_LANE : SOpInst<"vdot_lane", "..(<<)(<<q)I", "iUiQiQUi", OP_DOT_LN>;
1836 let ArchGuard = "defined(__ARM_FEATURE_DOTPROD) && defined(__aarch64__)" in {
1837 // Variants indexing into a 128-bit vector are A64 only.
1838 def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ> {
1843 // v8.2-A FP16 fused multiply-add long instructions.
1844 let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in {
1845 def VFMLAL_LOW : SInst<"vfmlal_low", ">>..", "hQh">;
1846 def VFMLSL_LOW : SInst<"vfmlsl_low", ">>..", "hQh">;
1847 def VFMLAL_HIGH : SInst<"vfmlal_high", ">>..", "hQh">;
1848 def VFMLSL_HIGH : SInst<"vfmlsl_high", ">>..", "hQh">;
1850 def VFMLAL_LANE_LOW : SOpInst<"vfmlal_lane_low", "(F>)(F>)F(Fq)I", "hQh", OP_FMLAL_LN>;
1851 def VFMLSL_LANE_LOW : SOpInst<"vfmlsl_lane_low", "(F>)(F>)F(Fq)I", "hQh", OP_FMLSL_LN>;
1852 def VFMLAL_LANE_HIGH : SOpInst<"vfmlal_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLAL_LN_Hi>;
1853 def VFMLSL_LANE_HIGH : SOpInst<"vfmlsl_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLSL_LN_Hi>;
1855 def VFMLAL_LANEQ_LOW : SOpInst<"vfmlal_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN> {
1858 def VFMLSL_LANEQ_LOW : SOpInst<"vfmlsl_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN> {
1861 def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi> {
1864 def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi> {
1869 let ArchGuard = "defined(__ARM_FEATURE_MATMUL_INT8)" in {
1870 def VMMLA : SInst<"vmmla", "..(<<)(<<)", "QUiQi">;
1871 def VUSMMLA : SInst<"vusmmla", "..(<<U)(<<)", "Qi">;
1873 def VUSDOT : SInst<"vusdot", "..(<<U)(<<)", "iQi">;
1875 def VUSDOT_LANE : SOpInst<"vusdot_lane", "..(<<U)(<<q)I", "iQi", OP_USDOT_LN>;
1876 def VSUDOT_LANE : SOpInst<"vsudot_lane", "..(<<)(<<qU)I", "iQi", OP_SUDOT_LN>;
1878 let ArchGuard = "defined(__aarch64__)" in {
1879 let isLaneQ = 1 in {
1880 def VUSDOT_LANEQ : SOpInst<"vusdot_laneq", "..(<<U)(<<Q)I", "iQi", OP_USDOT_LNQ>;
1881 def VSUDOT_LANEQ : SOpInst<"vsudot_laneq", "..(<<)(<<QU)I", "iQi", OP_SUDOT_LNQ>;
1886 let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
1887 def VDOT_BF : SInst<"vbfdot", "..BB", "fQf">;
1888 def VDOT_LANE_BF : SOpInst<"vbfdot_lane", "..B(Bq)I", "fQf", OP_BFDOT_LN>;
1889 def VDOT_LANEQ_BF : SOpInst<"vbfdot_laneq", "..B(BQ)I", "fQf", OP_BFDOT_LNQ> {
1893 def VFMMLA_BF : SInst<"vbfmmla", "..BB", "Qf">;
1895 def VFMLALB_BF : SInst<"vbfmlalb", "..BB", "Qf">;
1896 def VFMLALT_BF : SInst<"vbfmlalt", "..BB", "Qf">;
1898 def VFMLALB_LANE_BF : SOpInst<"vbfmlalb_lane", "..B(Bq)I", "Qf", OP_BFMLALB_LN>;
1899 def VFMLALB_LANEQ_BF : SOpInst<"vbfmlalb_laneq", "..B(BQ)I", "Qf", OP_BFMLALB_LN>;
1901 def VFMLALT_LANE_BF : SOpInst<"vbfmlalt_lane", "..B(Bq)I", "Qf", OP_BFMLALT_LN>;
1902 def VFMLALT_LANEQ_BF : SOpInst<"vbfmlalt_laneq", "..B(BQ)I", "Qf", OP_BFMLALT_LN>;
1905 // v8.3-A Vector complex addition intrinsics
1906 let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
1907 def VCADD_ROT90_FP16 : SInst<"vcadd_rot90", "...", "h">;
1908 def VCADD_ROT270_FP16 : SInst<"vcadd_rot270", "...", "h">;
1909 def VCADDQ_ROT90_FP16 : SInst<"vcaddq_rot90", "QQQ", "h">;
1910 def VCADDQ_ROT270_FP16 : SInst<"vcaddq_rot270", "QQQ", "h">;
1912 let ArchGuard = "defined(__ARM_FEATURE_COMPLEX)" in {
1913 def VCADD_ROT90 : SInst<"vcadd_rot90", "...", "f">;
1914 def VCADD_ROT270 : SInst<"vcadd_rot270", "...", "f">;
1915 def VCADDQ_ROT90 : SInst<"vcaddq_rot90", "QQQ", "f">;
1916 def VCADDQ_ROT270 : SInst<"vcaddq_rot270", "QQQ", "f">;
1918 let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__aarch64__)" in {
1919 def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
1920 def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
1923 // V8.2-A BFloat intrinsics
1924 let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
1925 def VCREATE_BF : NoTestOpInst<"vcreate", ".(IU>)", "b", OP_CAST> {
1926 let BigEndianSafe = 1;
1929 def VDUP_N_BF : WOpInst<"vdup_n", ".1", "bQb", OP_DUP>;
1931 def VDUP_LANE_BF : WOpInst<"vdup_lane", ".qI", "bQb", OP_DUP_LN>;
1932 def VDUP_LANEQ_BF: WOpInst<"vdup_laneq", ".QI", "bQb", OP_DUP_LN> {
1936 def VCOMBINE_BF : NoTestOpInst<"vcombine", "Q..", "b", OP_CONC>;
1938 def VGET_HIGH_BF : NoTestOpInst<"vget_high", ".Q", "b", OP_HI>;
1939 def VGET_LOW_BF : NoTestOpInst<"vget_low", ".Q", "b", OP_LO>;
1941 def VGET_LANE_BF : IInst<"vget_lane", "1.I", "bQb">;
1942 def VSET_LANE_BF : IInst<"vset_lane", ".1.I", "bQb">;
1943 def SCALAR_VDUP_LANE_BF : IInst<"vdup_lane", "1.I", "Sb">;
1944 def SCALAR_VDUP_LANEQ_BF : IInst<"vdup_laneq", "1QI", "Sb"> {
1948 def VLD1_BF : WInst<"vld1", ".(c*!)", "bQb">;
1949 def VLD2_BF : WInst<"vld2", "2(c*!)", "bQb">;
1950 def VLD3_BF : WInst<"vld3", "3(c*!)", "bQb">;
1951 def VLD4_BF : WInst<"vld4", "4(c*!)", "bQb">;
1953 def VST1_BF : WInst<"vst1", "v*(.!)", "bQb">;
1954 def VST2_BF : WInst<"vst2", "v*(2!)", "bQb">;
1955 def VST3_BF : WInst<"vst3", "v*(3!)", "bQb">;
1956 def VST4_BF : WInst<"vst4", "v*(4!)", "bQb">;
1958 def VLD1_X2_BF : WInst<"vld1_x2", "2(c*!)", "bQb">;
1959 def VLD1_X3_BF : WInst<"vld1_x3", "3(c*!)", "bQb">;
1960 def VLD1_X4_BF : WInst<"vld1_x4", "4(c*!)", "bQb">;
1962 def VST1_X2_BF : WInst<"vst1_x2", "v*(2!)", "bQb">;
1963 def VST1_X3_BF : WInst<"vst1_x3", "v*(3!)", "bQb">;
1964 def VST1_X4_BF : WInst<"vst1_x4", "v*(4!)", "bQb">;
1966 def VLD1_LANE_BF : WInst<"vld1_lane", ".(c*!).I", "bQb">;
1967 def VLD2_LANE_BF : WInst<"vld2_lane", "2(c*!)2I", "bQb">;
1968 def VLD3_LANE_BF : WInst<"vld3_lane", "3(c*!)3I", "bQb">;
1969 def VLD4_LANE_BF : WInst<"vld4_lane", "4(c*!)4I", "bQb">;
1970 def VST1_LANE_BF : WInst<"vst1_lane", "v*(.!)I", "bQb">;
1971 def VST2_LANE_BF : WInst<"vst2_lane", "v*(2!)I", "bQb">;
1972 def VST3_LANE_BF : WInst<"vst3_lane", "v*(3!)I", "bQb">;
1973 def VST4_LANE_BF : WInst<"vst4_lane", "v*(4!)I", "bQb">;
1975 def VLD1_DUP_BF : WInst<"vld1_dup", ".(c*!)", "bQb">;
1976 def VLD2_DUP_BF : WInst<"vld2_dup", "2(c*!)", "bQb">;
1977 def VLD3_DUP_BF : WInst<"vld3_dup", "3(c*!)", "bQb">;
1978 def VLD4_DUP_BF : WInst<"vld4_dup", "4(c*!)", "bQb">;
1980 def VCVT_F32_BF16 : SOpInst<"vcvt_f32_bf16", "(F>)(Bq!)", "Qb", OP_VCVT_F32_BF16>;
1981 def VCVT_LOW_F32_BF16 : SOpInst<"vcvt_low_f32", "(F>)(BQ!)", "Qb", OP_VCVT_F32_BF16_LO>;
1982 def VCVT_HIGH_F32_BF16 : SOpInst<"vcvt_high_f32", "(F>)(BQ!)", "Qb", OP_VCVT_F32_BF16_HI>;
1984 def SCALAR_CVT_BF16_F32 : SInst<"vcvth_bf16", "(1B)1", "f">;
1985 def SCALAR_CVT_F32_BF16 : SOpInst<"vcvtah_f32", "(1F>)(1!)", "b", OP_CVT_F32_BF16>;
1988 let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && !defined(__aarch64__)" in {
1989 def VCVT_BF16_F32_A32_INTERNAL : WInst<"__a32_vcvt_bf16", "BQ", "f">;
1990 def VCVT_BF16_F32_A32 : SOpInst<"vcvt_bf16", "BQ", "f", OP_VCVT_BF16_F32_A32>;
1991 def VCVT_LOW_BF16_F32_A32 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A32>;
1992 def VCVT_HIGH_BF16_F32_A32 : SOpInst<"vcvt_high_bf16", "BBQ", "Qf", OP_VCVT_BF16_F32_HI_A32>;
1995 let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {
1996 def VCVT_LOW_BF16_F32_A64_INTERNAL : WInst<"__a64_vcvtq_low_bf16", "BQ", "Hf">;
1997 def VCVT_LOW_BF16_F32_A64 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A64>;
1998 def VCVT_HIGH_BF16_F32_A64 : SInst<"vcvt_high_bf16", "BBQ", "Qf">;
1999 def VCVT_BF16_F32 : SOpInst<"vcvt_bf16", "BQ", "f", OP_VCVT_BF16_F32_A64>;
2001 def COPY_LANE_BF16 : IOpInst<"vcopy_lane", "..I.I", "b", OP_COPY_LN>;
2002 def COPYQ_LANE_BF16 : IOpInst<"vcopy_lane", "..IqI", "Qb", OP_COPY_LN>;
2003 def COPY_LANEQ_BF16 : IOpInst<"vcopy_laneq", "..IQI", "b", OP_COPY_LN>;
2004 def COPYQ_LANEQ_BF16 : IOpInst<"vcopy_laneq", "..I.I", "Qb", OP_COPY_LN>;
2007 let ArchGuard = "defined(__ARM_FEATURE_BF16) && !defined(__aarch64__)" in {
2008 let BigEndianSafe = 1 in {
2009 defm VREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
2010 "csilUcUsUiUlhfPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQPcQPsQPl", "bQb">;
2014 let ArchGuard = "defined(__ARM_FEATURE_BF16) && defined(__aarch64__)" in {
2015 let BigEndianSafe = 1 in {
2016 defm VVREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
2017 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", "bQb">;