contrib/llvm-project/clang/lib/Basic/Targets/Mips.cpp

   1 //===--- Mips.cpp - Implement Mips target feature support -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements Mips TargetInfo objects.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "Mips.h"
  14 #include "Targets.h"
  15 #include "clang/Basic/Diagnostic.h"
  16 #include "clang/Basic/MacroBuilder.h"
  17 #include "clang/Basic/TargetBuiltins.h"
  18 #include "llvm/ADT/StringSwitch.h"
  19
  20 using namespace clang;
  21 using namespace clang::targets;
  22
  23 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
  24 #define BUILTIN(ID, TYPE, ATTRS)                                               \
  25   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
  26 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
  27   {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
  28 #include "clang/Basic/BuiltinsMips.def"
  29 };
  30
  31 bool MipsTargetInfo::processorSupportsGPR64() const {
  32   return llvm::StringSwitch<bool>(CPU)
  33       .Case("mips3", true)
  34       .Case("mips4", true)
  35       .Case("mips5", true)
  36       .Case("mips64", true)
  37       .Case("mips64r2", true)
  38       .Case("mips64r3", true)
  39       .Case("mips64r5", true)
  40       .Case("mips64r6", true)
  41       .Case("octeon", true)
  42       .Case("octeon+", true)
  43       .Default(false);
  44   return false;
  45 }
  46
  47 static constexpr llvm::StringLiteral ValidCPUNames[] = {
  48     {"mips1"},  {"mips2"},    {"mips3"},    {"mips4"},    {"mips5"},
  49     {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
  50     {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
  51     {"octeon"}, {"octeon+"}, {"p5600"}};
  52
  53 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
  54   return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
  55 }
  56
  57 void MipsTargetInfo::fillValidCPUList(
  58     SmallVectorImpl<StringRef> &Values) const {
  59   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
  60 }
  61
  62 unsigned MipsTargetInfo::getISARev() const {
  63   return llvm::StringSwitch<unsigned>(getCPU())
  64              .Cases("mips32", "mips64", 1)
  65              .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
  66              .Cases("mips32r3", "mips64r3", 3)
  67              .Cases("mips32r5", "mips64r5", 5)
  68              .Cases("mips32r6", "mips64r6", 6)
  69              .Default(0);
  70 }
  71
  72 void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
  73                                       MacroBuilder &Builder) const {
  74   if (BigEndian) {
  75     DefineStd(Builder, "MIPSEB", Opts);
  76     Builder.defineMacro("_MIPSEB");
  77   } else {
  78     DefineStd(Builder, "MIPSEL", Opts);
  79     Builder.defineMacro("_MIPSEL");
  80   }
  81
  82   Builder.defineMacro("__mips__");
  83   Builder.defineMacro("_mips");
  84   if (Opts.GNUMode)
  85     Builder.defineMacro("mips");
  86
  87   if (ABI == "o32") {
  88     Builder.defineMacro("__mips", "32");
  89     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
  90   } else {
  91     Builder.defineMacro("__mips", "64");
  92     Builder.defineMacro("__mips64");
  93     Builder.defineMacro("__mips64__");
  94     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
  95   }
  96
  97   const std::string ISARev = std::to_string(getISARev());
  98
  99   if (!ISARev.empty())
 100     Builder.defineMacro("__mips_isa_rev", ISARev);
 101
 102   if (ABI == "o32") {
 103     Builder.defineMacro("__mips_o32");
 104     Builder.defineMacro("_ABIO32", "1");
 105     Builder.defineMacro("_MIPS_SIM", "_ABIO32");
 106   } else if (ABI == "n32") {
 107     Builder.defineMacro("__mips_n32");
 108     Builder.defineMacro("_ABIN32", "2");
 109     Builder.defineMacro("_MIPS_SIM", "_ABIN32");
 110   } else if (ABI == "n64") {
 111     Builder.defineMacro("__mips_n64");
 112     Builder.defineMacro("_ABI64", "3");
 113     Builder.defineMacro("_MIPS_SIM", "_ABI64");
 114   } else
 115     llvm_unreachable("Invalid ABI.");
 116
 117   if (!IsNoABICalls) {
 118     Builder.defineMacro("__mips_abicalls");
 119     if (CanUseBSDABICalls)
 120       Builder.defineMacro("__ABICALLS__");
 121   }
 122
 123   Builder.defineMacro("__REGISTER_PREFIX__", "");
 124
 125   switch (FloatABI) {
 126   case HardFloat:
 127     Builder.defineMacro("__mips_hard_float", Twine(1));
 128     break;
 129   case SoftFloat:
 130     Builder.defineMacro("__mips_soft_float", Twine(1));
 131     break;
 132   }
 133
 134   if (IsSingleFloat)
 135     Builder.defineMacro("__mips_single_float", Twine(1));
 136
 137   switch (FPMode) {
 138   case FPXX:
 139     Builder.defineMacro("__mips_fpr", Twine(0));
 140     break;
 141   case FP32:
 142     Builder.defineMacro("__mips_fpr", Twine(32));
 143     break;
 144   case FP64:
 145     Builder.defineMacro("__mips_fpr", Twine(64));
 146     break;
 147 }
 148
 149   if (FPMode == FP64 || IsSingleFloat)
 150     Builder.defineMacro("_MIPS_FPSET", Twine(32));
 151   else
 152     Builder.defineMacro("_MIPS_FPSET", Twine(16));
 153
 154   if (IsMips16)
 155     Builder.defineMacro("__mips16", Twine(1));
 156
 157   if (IsMicromips)
 158     Builder.defineMacro("__mips_micromips", Twine(1));
 159
 160   if (IsNan2008)
 161     Builder.defineMacro("__mips_nan2008", Twine(1));
 162
 163   if (IsAbs2008)
 164     Builder.defineMacro("__mips_abs2008", Twine(1));
 165
 166   switch (DspRev) {
 167   default:
 168     break;
 169   case DSP1:
 170     Builder.defineMacro("__mips_dsp_rev", Twine(1));
 171     Builder.defineMacro("__mips_dsp", Twine(1));
 172     break;
 173   case DSP2:
 174     Builder.defineMacro("__mips_dsp_rev", Twine(2));
 175     Builder.defineMacro("__mips_dspr2", Twine(1));
 176     Builder.defineMacro("__mips_dsp", Twine(1));
 177     break;
 178   }
 179
 180   if (HasMSA)
 181     Builder.defineMacro("__mips_msa", Twine(1));
 182
 183   if (DisableMadd4)
 184     Builder.defineMacro("__mips_no_madd4", Twine(1));
 185
 186   Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
 187   Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
 188   Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
 189
 190   Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
 191   if (CPU == "octeon+")
 192     Builder.defineMacro("_MIPS_ARCH_OCTEONP");
 193   else
 194     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
 195
 196   if (StringRef(CPU).startswith("octeon"))
 197     Builder.defineMacro("__OCTEON__");
 198
 199   // These shouldn't be defined for MIPS-I but there's no need to check
 200   // for that since MIPS-I isn't supported.
 201   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 202   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
 203   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
 204
 205   // 32-bit MIPS processors don't have the necessary lld/scd instructions
 206   // found in 64-bit processors. In the case of O32 on a 64-bit processor,
 207   // the instructions exist but using them violates the ABI since they
 208   // require 64-bit GPRs and O32 only supports 32-bit GPRs.
 209   if (ABI == "n32" || ABI == "n64")
 210     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
 211 }
 212
 213 bool MipsTargetInfo::hasFeature(StringRef Feature) const {
 214   return llvm::StringSwitch<bool>(Feature)
 215       .Case("mips", true)
 216       .Case("fp64", FPMode == FP64)
 217       .Default(false);
 218 }
 219
 220 ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
 221   return llvm::makeArrayRef(BuiltinInfo, clang::Mips::LastTSBuiltin -
 222                                              Builtin::FirstTSBuiltin);
 223 }
 224
 225 unsigned MipsTargetInfo::getUnwindWordWidth() const {
 226   return llvm::StringSwitch<unsigned>(ABI)
 227       .Case("o32", 32)
 228       .Case("n32", 64)
 229       .Case("n64", 64)
 230       .Default(getPointerWidth(0));
 231 }
 232
 233 bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
 234   // microMIPS64R6 backend was removed.
 235   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
 236     Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
 237     return false;
 238   }
 239   // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
 240   //        this yet. It's better to fail here than on the backend assertion.
 241   if (processorSupportsGPR64() && ABI == "o32") {
 242     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
 243     return false;
 244   }
 245
 246   // 64-bit ABI's require 64-bit CPU's.
 247   if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
 248     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
 249     return false;
 250   }
 251
 252   // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
 253   //        can't handle this yet. It's better to fail here than on the
 254   //        backend assertion.
 255   if (getTriple().isMIPS64() && ABI == "o32") {
 256     Diags.Report(diag::err_target_unsupported_abi_for_triple)
 257         << ABI << getTriple().str();
 258     return false;
 259   }
 260
 261   // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
 262   //        can't handle this yet. It's better to fail here than on the
 263   //        backend assertion.
 264   if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
 265     Diags.Report(diag::err_target_unsupported_abi_for_triple)
 266         << ABI << getTriple().str();
 267     return false;
 268   }
 269
 270   // -fpxx is valid only for the o32 ABI
 271   if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
 272     Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
 273     return false;
 274   }
 275
 276   // -mfp32 and n32/n64 ABIs are incompatible
 277   if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
 278       (ABI == "n32" || ABI == "n64")) {
 279     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
 280     return false;
 281   }
 282   // Mips revision 6 and -mfp32 are incompatible
 283   if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
 284       CPU == "mips64r6")) {
 285     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
 286     return false;
 287   }
 288   // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
 289   if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
 290       getISARev() < 2) && ABI == "o32") {
 291     Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
 292     return false;
 293   }
 294
 295   return true;
 296 }