1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares PPC TargetInfo objects.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
18 #include "clang/Basic/TargetOptions.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
29 /// Flags for architecture specific defines.
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefineFuture = 1 << 15,
48 ArchDefineA2 = 1 << 16,
49 ArchDefineA2q = 1 << 17,
50 ArchDefineE500 = 1 << 18
53 ArchDefineTypes ArchDefs = ArchDefineNone;
54 static const Builtin::Info BuiltinInfo[];
55 static const char *const GCCRegNames[];
56 static const TargetInfo::GCCRegAlias GCCRegAliases[];
58 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
60 // Target cpu features.
61 bool HasAltivec = false;
63 bool HasP8Vector = false;
64 bool HasP8Crypto = false;
65 bool HasDirectMove = false;
68 bool HasBPERMD = false;
69 bool HasExtDiv = false;
70 bool HasP9Vector = false;
72 bool HasP10Vector = false;
73 bool HasPCRelativeMemops = false;
79 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
80 : TargetInfo(Triple) {
82 SimdDefaultAlign = 128;
83 LongDoubleWidth = LongDoubleAlign = 128;
84 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
87 // Set the language option for altivec based on our value.
88 void adjust(LangOptions &Opts) override;
90 // Note: GCC recognizes the following additional cpus:
91 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
92 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
93 bool isValidCPUName(StringRef Name) const override;
94 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
96 bool setCPU(const std::string &Name) override {
97 bool CPUKnown = isValidCPUName(Name);
101 // CPU identification.
103 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
104 .Case("440", ArchDefineName)
105 .Case("450", ArchDefineName | ArchDefine440)
106 .Case("601", ArchDefineName)
107 .Case("602", ArchDefineName | ArchDefinePpcgr)
108 .Case("603", ArchDefineName | ArchDefinePpcgr)
109 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
110 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
111 .Case("604", ArchDefineName | ArchDefinePpcgr)
112 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
113 .Case("620", ArchDefineName | ArchDefinePpcgr)
114 .Case("630", ArchDefineName | ArchDefinePpcgr)
115 .Case("7400", ArchDefineName | ArchDefinePpcgr)
116 .Case("7450", ArchDefineName | ArchDefinePpcgr)
117 .Case("750", ArchDefineName | ArchDefinePpcgr)
118 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
120 .Case("a2", ArchDefineA2)
121 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
122 .Cases("power3", "pwr3", ArchDefinePpcgr)
123 .Cases("power4", "pwr4",
124 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
125 .Cases("power5", "pwr5",
126 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
128 .Cases("power5x", "pwr5x",
129 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
130 ArchDefinePpcgr | ArchDefinePpcsq)
131 .Cases("power6", "pwr6",
132 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
133 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
134 .Cases("power6x", "pwr6x",
135 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
136 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
138 .Cases("power7", "pwr7",
139 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
140 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
142 // powerpc64le automatically defaults to at least power8.
143 .Cases("power8", "pwr8", "ppc64le",
144 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
145 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
146 ArchDefinePpcgr | ArchDefinePpcsq)
147 .Cases("power9", "pwr9",
148 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
149 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
150 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
151 .Cases("power10", "pwr10",
152 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
153 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
154 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
157 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
158 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
159 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
160 ArchDefinePpcgr | ArchDefinePpcsq)
161 .Cases("8548", "e500", ArchDefineE500)
162 .Default(ArchDefineNone);
167 StringRef getABI() const override { return ABI; }
169 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
171 bool isCLZForZeroUndef() const override { return false; }
173 void getTargetDefines(const LangOptions &Opts,
174 MacroBuilder &Builder) const override;
177 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
179 const std::vector<std::string> &FeaturesVec) const override;
181 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
182 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
184 bool handleTargetFeatures(std::vector<std::string> &Features,
185 DiagnosticsEngine &Diags) override;
187 bool hasFeature(StringRef Feature) const override;
189 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
190 bool Enabled) const override;
192 ArrayRef<const char *> getGCCRegNames() const override;
194 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
196 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
198 bool validateAsmConstraint(const char *&Name,
199 TargetInfo::ConstraintInfo &Info) const override {
205 case 'f': // Floating point register
206 // Don't use floating point registers on soft float ABI.
207 if (FloatABI == SoftFloat)
210 case 'b': // Base register
211 Info.setAllowsRegister();
213 // FIXME: The following are added to allow parsing.
214 // I just took a guess at what the actions should be.
215 // Also, is more specific checking needed? I.e. specific registers?
216 case 'd': // Floating point register (containing 64-bit value)
217 case 'v': // Altivec vector register
218 // Don't use floating point and altivec vector registers
220 if (FloatABI == SoftFloat)
222 Info.setAllowsRegister();
226 case 'd': // VSX vector register to hold vector double data
227 case 'f': // VSX vector register to hold vector float data
228 case 's': // VSX vector register to hold scalar double data
229 case 'w': // VSX vector register to hold scalar double data
230 case 'a': // Any VSX register
231 case 'c': // An individual CR bit
232 case 'i': // FP or VSX register to hold 64-bit integers data
237 Info.setAllowsRegister();
238 Name++; // Skip over 'w'.
240 case 'h': // `MQ', `CTR', or `LINK' register
241 case 'q': // `MQ' register
242 case 'c': // `CTR' register
243 case 'l': // `LINK' register
244 case 'x': // `CR' register (condition register) number 0
245 case 'y': // `CR' register (condition register)
246 case 'z': // `XER[CA]' carry bit (part of the XER register)
247 Info.setAllowsRegister();
249 case 'I': // Signed 16-bit constant
250 case 'J': // Unsigned 16-bit constant shifted left 16 bits
251 // (use `L' instead for SImode constants)
252 case 'K': // Unsigned 16-bit constant
253 case 'L': // Signed 16-bit constant shifted left 16 bits
254 case 'M': // Constant larger than 31
255 case 'N': // Exact power of 2
256 case 'P': // Constant whose negation is a signed 16-bit constant
257 case 'G': // Floating point constant that can be loaded into a
258 // register with one instruction per word
259 case 'H': // Integer/Floating point constant that can be loaded
260 // into a register using three instructions
262 case 'm': // Memory operand. Note that on PowerPC targets, m can
263 // include addresses that update the base register. It
264 // is therefore only safe to use `m' in an asm statement
265 // if that asm statement accesses the operand exactly once.
266 // The asm statement must also use `%U<opno>' as a
267 // placeholder for the "update" flag in the corresponding
268 // load or store instruction. For example:
269 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
271 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
272 // is not. Use es rather than m if you don't want the base
273 // register to be updated.
277 // es: A "stable" memory operand; that is, one which does not
278 // include any automodification of the base register. Unlike
279 // `m', this constraint can be used in asm statements that
280 // might access the operand several times, or that might not
282 Info.setAllowsMemory();
283 Name++; // Skip over 'e'.
285 case 'Q': // Memory operand that is an offset from a register (it is
286 // usually better to use `m' or `es' in asm statements)
287 Info.setAllowsRegister();
289 case 'Z': // Memory operand that is an indexed or indirect from a
290 // register (it is usually better to use `m' or `es' in
292 Info.setAllowsMemory();
294 case 'R': // AIX TOC entry
295 case 'a': // Address operand that is an indexed or indirect from a
296 // register (`p' is preferable for asm statements)
297 case 'S': // Constant suitable as a 64-bit mask operand
298 case 'T': // Constant suitable as a 32-bit mask operand
299 case 'U': // System V Release 4 small data area reference
300 case 't': // AND masks that can be performed by two rldic{l, r}
302 case 'W': // Vector constant that does not require memory
303 case 'j': // Vector constant that is all zeros.
310 std::string convertConstraint(const char *&Constraint) const override {
312 switch (*Constraint) {
315 // Two-character constraint; add "^" hint for later parsing.
316 R = std::string("^") + std::string(Constraint, 2);
320 return TargetInfo::convertConstraint(Constraint);
325 const char *getClobbers() const override { return ""; }
326 int getEHDataRegisterNumber(unsigned RegNo) const override {
334 bool hasSjLjLowering() const override { return true; }
336 const char *getLongDoubleMangling() const override {
337 if (LongDoubleWidth == 64)
339 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
343 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
345 bool hasExtIntType() const override { return true; }
347 bool isSPRegName(StringRef RegName) const override {
348 return RegName.equals("r1") || RegName.equals("x1");
352 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
354 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
355 : PPCTargetInfo(Triple, Opts) {
356 if (Triple.isOSAIX())
357 resetDataLayout("E-m:a-p:32:32-i64:64-n32");
359 resetDataLayout("E-m:e-p:32:32-i64:64-n32");
361 switch (getTriple().getOS()) {
362 case llvm::Triple::Linux:
363 case llvm::Triple::FreeBSD:
364 case llvm::Triple::NetBSD:
365 SizeType = UnsignedInt;
366 PtrDiffType = SignedInt;
367 IntPtrType = SignedInt;
369 case llvm::Triple::AIX:
370 SizeType = UnsignedLong;
371 PtrDiffType = SignedLong;
372 IntPtrType = SignedLong;
379 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
380 Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
381 LongDoubleWidth = LongDoubleAlign = 64;
382 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
385 // PPC32 supports atomics up to 4 bytes.
386 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
389 BuiltinVaListKind getBuiltinVaListKind() const override {
390 // This is the ELF definition, and is overridden by the Darwin sub-target
391 return TargetInfo::PowerABIBuiltinVaList;
395 // Note: ABI differences may eventually require us to have a separate
396 // TargetInfo for little endian.
397 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
399 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
400 : PPCTargetInfo(Triple, Opts) {
401 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
402 IntMaxType = SignedLong;
403 Int64Type = SignedLong;
405 if (Triple.isOSAIX()) {
406 // TODO: Set appropriate ABI for AIX platform.
407 resetDataLayout("E-m:a-i64:64-n32:64");
409 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
410 resetDataLayout("e-m:e-i64:64-n32:64");
413 resetDataLayout("E-m:e-i64:64-n32:64");
417 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() ||
418 Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
419 LongDoubleWidth = LongDoubleAlign = 64;
420 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
423 // PPC64 supports atomics up to 8 bytes.
424 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
427 BuiltinVaListKind getBuiltinVaListKind() const override {
428 return TargetInfo::CharPtrBuiltinVaList;
431 // PPC64 Linux-specific ABI options.
432 bool setABI(const std::string &Name) override {
433 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
440 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
450 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
451 : public DarwinTargetInfo<PPC32TargetInfo> {
453 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
454 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
455 HasAlignMac68kSupport = true;
456 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
457 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
459 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
462 BuiltinVaListKind getBuiltinVaListKind() const override {
463 return TargetInfo::CharPtrBuiltinVaList;
467 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
468 : public DarwinTargetInfo<PPC64TargetInfo> {
470 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
471 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
472 HasAlignMac68kSupport = true;
473 resetDataLayout("E-m:o-i64:64-n32:64");
477 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
478 public AIXTargetInfo<PPC32TargetInfo> {
480 using AIXTargetInfo::AIXTargetInfo;
481 BuiltinVaListKind getBuiltinVaListKind() const override {
482 return TargetInfo::CharPtrBuiltinVaList;
486 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
487 public AIXTargetInfo<PPC64TargetInfo> {
489 using AIXTargetInfo::AIXTargetInfo;
492 } // namespace targets
494 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H