1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements X86 TargetInfo objects.
11 //===----------------------------------------------------------------------===//
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/TargetBuiltins.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/TargetParser/X86TargetParser.h"
26 static constexpr Builtin::Info BuiltinInfoX86[] = {
27 #define BUILTIN(ID, TYPE, ATTRS) \
28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
30 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
33 #include "clang/Basic/BuiltinsX86.def"
35 #define BUILTIN(ID, TYPE, ATTRS) \
36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
40 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS},
41 #include "clang/Basic/BuiltinsX86_64.def"
44 static const char *const GCCRegNames[] = {
45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
62 "k2", "k3", "k4", "k5", "k6", "k7",
63 "cr0", "cr2", "cr3", "cr4", "cr8",
64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
65 "bnd0", "bnd1", "bnd2", "bnd3",
66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
69 const TargetInfo::AddlRegName AddlRegNames[] = {
70 {{"al", "ah", "eax", "rax"}, 0},
71 {{"bl", "bh", "ebx", "rbx"}, 3},
72 {{"cl", "ch", "ecx", "rcx"}, 2},
73 {{"dl", "dh", "edx", "rdx"}, 1},
78 {{"r8d", "r8w", "r8b"}, 38},
79 {{"r9d", "r9w", "r9b"}, 39},
80 {{"r10d", "r10w", "r10b"}, 40},
81 {{"r11d", "r11w", "r11b"}, 41},
82 {{"r12d", "r12w", "r12b"}, 42},
83 {{"r13d", "r13w", "r13b"}, 43},
84 {{"r14d", "r14w", "r14b"}, 44},
85 {{"r15d", "r15w", "r15b"}, 45},
88 } // namespace targets
91 using namespace clang;
92 using namespace clang::targets;
94 bool X86TargetInfo::setFPMath(StringRef Name) {
106 bool X86TargetInfo::initFeatureMap(
107 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
108 const std::vector<std::string> &FeaturesVec) const {
109 // FIXME: This *really* should not be here.
110 // X86_64 always has SSE2.
111 if (getTriple().getArch() == llvm::Triple::x86_64)
112 setFeatureEnabled(Features, "sse2", true);
114 using namespace llvm::X86;
116 SmallVector<StringRef, 16> CPUFeatures;
117 getFeaturesForCPU(CPU, CPUFeatures);
118 for (auto &F : CPUFeatures)
119 setFeatureEnabled(Features, F, true);
121 std::vector<std::string> UpdatedFeaturesVec;
122 for (const auto &Feature : FeaturesVec) {
123 // Expand general-regs-only to -x86, -mmx and -sse
124 if (Feature == "+general-regs-only") {
125 UpdatedFeaturesVec.push_back("-x87");
126 UpdatedFeaturesVec.push_back("-mmx");
127 UpdatedFeaturesVec.push_back("-sse");
131 UpdatedFeaturesVec.push_back(Feature);
134 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
137 // Can't do this earlier because we need to be able to explicitly enable
138 // or disable these features and the things that they depend upon.
140 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
141 auto I = Features.find("sse4.2");
142 if (I != Features.end() && I->getValue() &&
143 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
144 Features["popcnt"] = true;
146 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
148 I = Features.find("sse");
149 if (I != Features.end() && I->getValue() &&
150 !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
151 Features["mmx"] = true;
153 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
154 I = Features.find("avx");
155 if (I != Features.end() && I->getValue() &&
156 !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
157 Features["xsave"] = true;
159 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
160 I = Features.find("sse4.2");
161 if (I != Features.end() && I->getValue() &&
162 !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
163 Features["crc32"] = true;
168 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
169 StringRef Name, bool Enabled) const {
170 if (Name == "sse4") {
171 // We can get here via the __target__ attribute since that's not controlled
172 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
173 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
181 Features[Name] = Enabled;
182 llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
185 /// handleTargetFeatures - Perform initialization based on the user
186 /// configured set of features.
187 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
188 DiagnosticsEngine &Diags) {
189 for (const auto &Feature : Features) {
190 if (Feature[0] != '+')
193 if (Feature == "+aes") {
195 } else if (Feature == "+vaes") {
197 } else if (Feature == "+pclmul") {
199 } else if (Feature == "+vpclmulqdq") {
200 HasVPCLMULQDQ = true;
201 } else if (Feature == "+lzcnt") {
203 } else if (Feature == "+rdrnd") {
205 } else if (Feature == "+fsgsbase") {
207 } else if (Feature == "+bmi") {
209 } else if (Feature == "+bmi2") {
211 } else if (Feature == "+popcnt") {
213 } else if (Feature == "+rtm") {
215 } else if (Feature == "+prfchw") {
217 } else if (Feature == "+rdseed") {
219 } else if (Feature == "+adx") {
221 } else if (Feature == "+tbm") {
223 } else if (Feature == "+lwp") {
225 } else if (Feature == "+fma") {
227 } else if (Feature == "+f16c") {
229 } else if (Feature == "+gfni") {
231 } else if (Feature == "+avx512cd") {
233 } else if (Feature == "+avx512vpopcntdq") {
234 HasAVX512VPOPCNTDQ = true;
235 } else if (Feature == "+avx512vnni") {
236 HasAVX512VNNI = true;
237 } else if (Feature == "+avx512bf16") {
238 HasAVX512BF16 = true;
239 } else if (Feature == "+avx512er") {
241 } else if (Feature == "+avx512fp16") {
242 HasAVX512FP16 = true;
243 HasLegalHalfType = true;
244 } else if (Feature == "+avx512pf") {
246 } else if (Feature == "+avx512dq") {
248 } else if (Feature == "+avx512bitalg") {
249 HasAVX512BITALG = true;
250 } else if (Feature == "+avx512bw") {
252 } else if (Feature == "+avx512vl") {
254 } else if (Feature == "+avx512vbmi") {
255 HasAVX512VBMI = true;
256 } else if (Feature == "+avx512vbmi2") {
257 HasAVX512VBMI2 = true;
258 } else if (Feature == "+avx512ifma") {
259 HasAVX512IFMA = true;
260 } else if (Feature == "+avx512vp2intersect") {
261 HasAVX512VP2INTERSECT = true;
262 } else if (Feature == "+sha") {
264 } else if (Feature == "+sha512") {
266 } else if (Feature == "+shstk") {
268 } else if (Feature == "+sm3") {
270 } else if (Feature == "+sm4") {
272 } else if (Feature == "+movbe") {
274 } else if (Feature == "+sgx") {
276 } else if (Feature == "+cx8") {
278 } else if (Feature == "+cx16") {
280 } else if (Feature == "+fxsr") {
282 } else if (Feature == "+xsave") {
284 } else if (Feature == "+xsaveopt") {
286 } else if (Feature == "+xsavec") {
288 } else if (Feature == "+xsaves") {
290 } else if (Feature == "+mwaitx") {
292 } else if (Feature == "+pku") {
294 } else if (Feature == "+clflushopt") {
295 HasCLFLUSHOPT = true;
296 } else if (Feature == "+clwb") {
298 } else if (Feature == "+wbnoinvd") {
300 } else if (Feature == "+prefetchi") {
302 } else if (Feature == "+prefetchwt1") {
303 HasPREFETCHWT1 = true;
304 } else if (Feature == "+clzero") {
306 } else if (Feature == "+cldemote") {
308 } else if (Feature == "+rdpid") {
310 } else if (Feature == "+rdpru") {
312 } else if (Feature == "+kl") {
314 } else if (Feature == "+widekl") {
316 } else if (Feature == "+retpoline-external-thunk") {
317 HasRetpolineExternalThunk = true;
318 } else if (Feature == "+sahf") {
320 } else if (Feature == "+waitpkg") {
322 } else if (Feature == "+movdiri") {
324 } else if (Feature == "+movdir64b") {
326 } else if (Feature == "+pconfig") {
328 } else if (Feature == "+ptwrite") {
330 } else if (Feature == "+invpcid") {
332 } else if (Feature == "+enqcmd") {
334 } else if (Feature == "+hreset") {
336 } else if (Feature == "+amx-bf16") {
338 } else if (Feature == "+amx-fp16") {
340 } else if (Feature == "+amx-int8") {
342 } else if (Feature == "+amx-tile") {
344 } else if (Feature == "+amx-complex") {
345 HasAMXCOMPLEX = true;
346 } else if (Feature == "+cmpccxadd") {
348 } else if (Feature == "+raoint") {
350 } else if (Feature == "+avxifma") {
352 } else if (Feature == "+avxneconvert") {
353 HasAVXNECONVERT= true;
354 } else if (Feature == "+avxvnni") {
356 } else if (Feature == "+avxvnniint16") {
357 HasAVXVNNIINT16 = true;
358 } else if (Feature == "+avxvnniint8") {
359 HasAVXVNNIINT8 = true;
360 } else if (Feature == "+serialize") {
362 } else if (Feature == "+tsxldtrk") {
364 } else if (Feature == "+uintr") {
366 } else if (Feature == "+crc32") {
368 } else if (Feature == "+x87") {
370 } else if (Feature == "+fullbf16") {
371 HasFullBFloat16 = true;
374 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
375 .Case("+avx512f", AVX512F)
378 .Case("+sse4.2", SSE42)
379 .Case("+sse4.1", SSE41)
380 .Case("+ssse3", SSSE3)
385 SSELevel = std::max(SSELevel, Level);
387 HasFloat16 = SSELevel >= SSE2;
389 // X86 target has bfloat16 emulation support in the backend, where
390 // bfloat16 is treated as a 32-bit float, arithmetic operations are
391 // performed in 32-bit, and the result is converted back to bfloat16.
392 // Truncation and extension between bfloat16 and 32-bit float are supported
393 // by the compiler-rt library. However, native bfloat16 support is currently
394 // not available in the X86 target. Hence, HasFullBFloat16 will be false
395 // until native bfloat16 support is available. HasFullBFloat16 is used to
396 // determine whether to automatically use excess floating point precision
397 // for bfloat16 arithmetic operations in the front-end.
398 HasBFloat16 = SSELevel >= SSE2;
400 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
401 .Case("+3dnowa", AMD3DNowAthlon)
402 .Case("+3dnow", AMD3DNow)
404 .Default(NoMMX3DNow);
405 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
407 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
410 .Case("+sse4a", SSE4A)
412 XOPLevel = std::max(XOPLevel, XLevel);
415 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
416 // matches the selected sse level.
417 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
418 (FPMath == FP_387 && SSELevel >= SSE1)) {
419 Diags.Report(diag::err_target_unsupported_fpmath)
420 << (FPMath == FP_SSE ? "sse" : "387");
424 // FIXME: We should allow long double type on 32-bits to match with GCC.
425 // This requires backend to be able to lower f80 without x87 first.
426 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
427 HasLongDouble = false;
432 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
433 /// definitions for this particular subtarget.
434 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
435 MacroBuilder &Builder) const {
436 // Inline assembly supports X86 flag outputs.
437 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
439 std::string CodeModel = getTargetOpts().CodeModel;
440 if (CodeModel == "default")
442 Builder.defineMacro("__code_model_" + CodeModel + "__");
444 // Target identification.
445 if (getTriple().getArch() == llvm::Triple::x86_64) {
446 Builder.defineMacro("__amd64__");
447 Builder.defineMacro("__amd64");
448 Builder.defineMacro("__x86_64");
449 Builder.defineMacro("__x86_64__");
450 if (getTriple().getArchName() == "x86_64h") {
451 Builder.defineMacro("__x86_64h");
452 Builder.defineMacro("__x86_64h__");
455 DefineStd(Builder, "i386", Opts);
458 Builder.defineMacro("__SEG_GS");
459 Builder.defineMacro("__SEG_FS");
460 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
461 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
463 // Subtarget options.
464 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
465 // truly should be based on -mtune options.
466 using namespace llvm::X86;
471 // The rest are coming from the i386 define above.
472 Builder.defineMacro("__tune_i386__");
478 defineCPUMacros(Builder, "i486");
481 Builder.defineMacro("__pentium_mmx__");
482 Builder.defineMacro("__tune_pentium_mmx__");
486 defineCPUMacros(Builder, "i586");
487 defineCPUMacros(Builder, "pentium");
491 Builder.defineMacro("__tune_pentium3__");
495 Builder.defineMacro("__tune_pentium2__");
499 defineCPUMacros(Builder, "i686");
500 defineCPUMacros(Builder, "pentiumpro");
503 defineCPUMacros(Builder, "pentium4");
508 defineCPUMacros(Builder, "nocona");
512 defineCPUMacros(Builder, "core2");
515 defineCPUMacros(Builder, "atom");
518 defineCPUMacros(Builder, "slm");
521 defineCPUMacros(Builder, "goldmont");
523 case CK_GoldmontPlus:
524 defineCPUMacros(Builder, "goldmont_plus");
527 defineCPUMacros(Builder, "tremont");
535 case CK_SkylakeClient:
536 case CK_SkylakeServer:
540 case CK_IcelakeClient:
542 case CK_IcelakeServer:
544 case CK_SapphireRapids:
548 case CK_Sierraforest:
550 case CK_Graniterapids:
551 case CK_GraniterapidsD:
552 case CK_Emeraldrapids:
553 // FIXME: Historically, we defined this legacy name, it would be nice to
554 // remove it at some point. We've never exposed fine-grained names for
555 // recent primary x86 CPUs, and we should keep it that way.
556 defineCPUMacros(Builder, "corei7");
559 defineCPUMacros(Builder, "knl");
564 defineCPUMacros(Builder, "i586", /*Tuning*/false);
565 defineCPUMacros(Builder, "pentium", /*Tuning*/false);
566 Builder.defineMacro("__tune_lakemont__");
569 Builder.defineMacro("__k6_2__");
570 Builder.defineMacro("__tune_k6_2__");
573 if (CPU != CK_K6_2) { // In case of fallthrough
574 // FIXME: GCC may be enabling these in cases where some other k6
575 // architecture is specified but -m3dnow is explicitly provided. The
576 // exact semantics need to be determined and emulated here.
577 Builder.defineMacro("__k6_3__");
578 Builder.defineMacro("__tune_k6_3__");
582 defineCPUMacros(Builder, "k6");
586 defineCPUMacros(Builder, "athlon");
587 if (SSELevel != NoSSE) {
588 Builder.defineMacro("__athlon_sse__");
589 Builder.defineMacro("__tune_athlon_sse__");
595 defineCPUMacros(Builder, "k8");
602 defineCPUMacros(Builder, "amdfam10");
605 defineCPUMacros(Builder, "btver1");
608 defineCPUMacros(Builder, "btver2");
611 defineCPUMacros(Builder, "bdver1");
614 defineCPUMacros(Builder, "bdver2");
617 defineCPUMacros(Builder, "bdver3");
620 defineCPUMacros(Builder, "bdver4");
623 defineCPUMacros(Builder, "znver1");
626 defineCPUMacros(Builder, "znver2");
629 defineCPUMacros(Builder, "znver3");
632 defineCPUMacros(Builder, "znver4");
635 defineCPUMacros(Builder, "geode");
639 // Target properties.
640 Builder.defineMacro("__REGISTER_PREFIX__", "");
642 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
643 // functions in glibc header files that use FP Stack inline asm which the
644 // backend can't deal with (PR879).
645 Builder.defineMacro("__NO_MATH_INLINES");
648 Builder.defineMacro("__AES__");
651 Builder.defineMacro("__VAES__");
654 Builder.defineMacro("__PCLMUL__");
657 Builder.defineMacro("__VPCLMULQDQ__");
659 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
660 // the feature flag only applies to 64-bit mode.
661 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
662 Builder.defineMacro("__LAHF_SAHF__");
665 Builder.defineMacro("__LZCNT__");
668 Builder.defineMacro("__RDRND__");
671 Builder.defineMacro("__FSGSBASE__");
674 Builder.defineMacro("__BMI__");
677 Builder.defineMacro("__BMI2__");
680 Builder.defineMacro("__POPCNT__");
683 Builder.defineMacro("__RTM__");
686 Builder.defineMacro("__PRFCHW__");
689 Builder.defineMacro("__RDSEED__");
692 Builder.defineMacro("__ADX__");
695 Builder.defineMacro("__TBM__");
698 Builder.defineMacro("__LWP__");
701 Builder.defineMacro("__MWAITX__");
704 Builder.defineMacro("__MOVBE__");
708 Builder.defineMacro("__XOP__");
711 Builder.defineMacro("__FMA4__");
714 Builder.defineMacro("__SSE4A__");
721 Builder.defineMacro("__FMA__");
724 Builder.defineMacro("__F16C__");
727 Builder.defineMacro("__GFNI__");
730 Builder.defineMacro("__AVX512CD__");
731 if (HasAVX512VPOPCNTDQ)
732 Builder.defineMacro("__AVX512VPOPCNTDQ__");
734 Builder.defineMacro("__AVX512VNNI__");
736 Builder.defineMacro("__AVX512BF16__");
738 Builder.defineMacro("__AVX512ER__");
740 Builder.defineMacro("__AVX512FP16__");
742 Builder.defineMacro("__AVX512PF__");
744 Builder.defineMacro("__AVX512DQ__");
746 Builder.defineMacro("__AVX512BITALG__");
748 Builder.defineMacro("__AVX512BW__");
750 Builder.defineMacro("__AVX512VL__");
752 Builder.defineMacro("__AVX512VBMI__");
754 Builder.defineMacro("__AVX512VBMI2__");
756 Builder.defineMacro("__AVX512IFMA__");
757 if (HasAVX512VP2INTERSECT)
758 Builder.defineMacro("__AVX512VP2INTERSECT__");
760 Builder.defineMacro("__SHA__");
762 Builder.defineMacro("__SHA512__");
765 Builder.defineMacro("__FXSR__");
767 Builder.defineMacro("__XSAVE__");
769 Builder.defineMacro("__XSAVEOPT__");
771 Builder.defineMacro("__XSAVEC__");
773 Builder.defineMacro("__XSAVES__");
775 Builder.defineMacro("__PKU__");
777 Builder.defineMacro("__CLFLUSHOPT__");
779 Builder.defineMacro("__CLWB__");
781 Builder.defineMacro("__WBNOINVD__");
783 Builder.defineMacro("__SHSTK__");
785 Builder.defineMacro("__SGX__");
787 Builder.defineMacro("__SM3__");
789 Builder.defineMacro("__SM4__");
791 Builder.defineMacro("__PREFETCHI__");
793 Builder.defineMacro("__PREFETCHWT1__");
795 Builder.defineMacro("__CLZERO__");
797 Builder.defineMacro("__KL__");
799 Builder.defineMacro("__WIDEKL__");
801 Builder.defineMacro("__RDPID__");
803 Builder.defineMacro("__RDPRU__");
805 Builder.defineMacro("__CLDEMOTE__");
807 Builder.defineMacro("__WAITPKG__");
809 Builder.defineMacro("__MOVDIRI__");
811 Builder.defineMacro("__MOVDIR64B__");
813 Builder.defineMacro("__PCONFIG__");
815 Builder.defineMacro("__PTWRITE__");
817 Builder.defineMacro("__INVPCID__");
819 Builder.defineMacro("__ENQCMD__");
821 Builder.defineMacro("__HRESET__");
823 Builder.defineMacro("__AMX_TILE__");
825 Builder.defineMacro("__AMX_INT8__");
827 Builder.defineMacro("__AMX_BF16__");
829 Builder.defineMacro("__AMX_FP16__");
831 Builder.defineMacro("__AMX_COMPLEX__");
833 Builder.defineMacro("__CMPCCXADD__");
835 Builder.defineMacro("__RAOINT__");
837 Builder.defineMacro("__AVXIFMA__");
839 Builder.defineMacro("__AVXNECONVERT__");
841 Builder.defineMacro("__AVXVNNI__");
843 Builder.defineMacro("__AVXVNNIINT16__");
845 Builder.defineMacro("__AVXVNNIINT8__");
847 Builder.defineMacro("__SERIALIZE__");
849 Builder.defineMacro("__TSXLDTRK__");
851 Builder.defineMacro("__UINTR__");
853 Builder.defineMacro("__CRC32__");
855 // Each case falls through to the previous one here.
858 Builder.defineMacro("__AVX512F__");
861 Builder.defineMacro("__AVX2__");
864 Builder.defineMacro("__AVX__");
867 Builder.defineMacro("__SSE4_2__");
870 Builder.defineMacro("__SSE4_1__");
873 Builder.defineMacro("__SSSE3__");
876 Builder.defineMacro("__SSE3__");
879 Builder.defineMacro("__SSE2__");
880 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
883 Builder.defineMacro("__SSE__");
884 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
890 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
900 Builder.defineMacro("_M_IX86_FP", Twine(2));
903 Builder.defineMacro("_M_IX86_FP", Twine(1));
906 Builder.defineMacro("_M_IX86_FP", Twine(0));
911 // Each case falls through to the previous one here.
912 switch (MMX3DNowLevel) {
914 Builder.defineMacro("__3dNOW_A__");
917 Builder.defineMacro("__3dNOW__");
920 Builder.defineMacro("__MMX__");
926 if (CPU >= CK_i486 || CPU == CK_None) {
927 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
928 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
929 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
932 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
933 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
934 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
937 Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
940 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
941 return llvm::StringSwitch<bool>(Name)
943 .Case("3dnowa", true)
946 .Case("amx-bf16", true)
947 .Case("amx-complex", true)
948 .Case("amx-fp16", true)
949 .Case("amx-int8", true)
950 .Case("amx-tile", true)
953 .Case("avx512f", true)
954 .Case("avx512cd", true)
955 .Case("avx512vpopcntdq", true)
956 .Case("avx512vnni", true)
957 .Case("avx512bf16", true)
958 .Case("avx512er", true)
959 .Case("avx512fp16", true)
960 .Case("avx512pf", true)
961 .Case("avx512dq", true)
962 .Case("avx512bitalg", true)
963 .Case("avx512bw", true)
964 .Case("avx512vl", true)
965 .Case("avx512vbmi", true)
966 .Case("avx512vbmi2", true)
967 .Case("avx512ifma", true)
968 .Case("avx512vp2intersect", true)
969 .Case("avxifma", true)
970 .Case("avxneconvert", true)
971 .Case("avxvnni", true)
972 .Case("avxvnniint16", true)
973 .Case("avxvnniint8", true)
976 .Case("cldemote", true)
977 .Case("clflushopt", true)
979 .Case("clzero", true)
980 .Case("cmpccxadd", true)
983 .Case("enqcmd", true)
987 .Case("fsgsbase", true)
989 .Case("general-regs-only", true)
991 .Case("hreset", true)
992 .Case("invpcid", true)
994 .Case("widekl", true)
999 .Case("movdiri", true)
1000 .Case("movdir64b", true)
1001 .Case("mwaitx", true)
1002 .Case("pclmul", true)
1003 .Case("pconfig", true)
1005 .Case("popcnt", true)
1006 .Case("prefetchi", true)
1007 .Case("prefetchwt1", true)
1008 .Case("prfchw", true)
1009 .Case("ptwrite", true)
1010 .Case("raoint", true)
1011 .Case("rdpid", true)
1012 .Case("rdpru", true)
1013 .Case("rdrnd", true)
1014 .Case("rdseed", true)
1017 .Case("serialize", true)
1020 .Case("sha512", true)
1021 .Case("shstk", true)
1027 .Case("ssse3", true)
1029 .Case("sse4.1", true)
1030 .Case("sse4.2", true)
1031 .Case("sse4a", true)
1033 .Case("tsxldtrk", true)
1034 .Case("uintr", true)
1036 .Case("vpclmulqdq", true)
1037 .Case("wbnoinvd", true)
1038 .Case("waitpkg", true)
1041 .Case("xsave", true)
1042 .Case("xsavec", true)
1043 .Case("xsaves", true)
1044 .Case("xsaveopt", true)
1048 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1049 return llvm::StringSwitch<bool>(Feature)
1050 .Case("adx", HasADX)
1051 .Case("aes", HasAES)
1052 .Case("amx-bf16", HasAMXBF16)
1053 .Case("amx-complex", HasAMXCOMPLEX)
1054 .Case("amx-fp16", HasAMXFP16)
1055 .Case("amx-int8", HasAMXINT8)
1056 .Case("amx-tile", HasAMXTILE)
1057 .Case("avx", SSELevel >= AVX)
1058 .Case("avx2", SSELevel >= AVX2)
1059 .Case("avx512f", SSELevel >= AVX512F)
1060 .Case("avx512cd", HasAVX512CD)
1061 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1062 .Case("avx512vnni", HasAVX512VNNI)
1063 .Case("avx512bf16", HasAVX512BF16)
1064 .Case("avx512er", HasAVX512ER)
1065 .Case("avx512fp16", HasAVX512FP16)
1066 .Case("avx512pf", HasAVX512PF)
1067 .Case("avx512dq", HasAVX512DQ)
1068 .Case("avx512bitalg", HasAVX512BITALG)
1069 .Case("avx512bw", HasAVX512BW)
1070 .Case("avx512vl", HasAVX512VL)
1071 .Case("avx512vbmi", HasAVX512VBMI)
1072 .Case("avx512vbmi2", HasAVX512VBMI2)
1073 .Case("avx512ifma", HasAVX512IFMA)
1074 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1075 .Case("avxifma", HasAVXIFMA)
1076 .Case("avxneconvert", HasAVXNECONVERT)
1077 .Case("avxvnni", HasAVXVNNI)
1078 .Case("avxvnniint16", HasAVXVNNIINT16)
1079 .Case("avxvnniint8", HasAVXVNNIINT8)
1080 .Case("bmi", HasBMI)
1081 .Case("bmi2", HasBMI2)
1082 .Case("cldemote", HasCLDEMOTE)
1083 .Case("clflushopt", HasCLFLUSHOPT)
1084 .Case("clwb", HasCLWB)
1085 .Case("clzero", HasCLZERO)
1086 .Case("cmpccxadd", HasCMPCCXADD)
1087 .Case("crc32", HasCRC32)
1088 .Case("cx8", HasCX8)
1089 .Case("cx16", HasCX16)
1090 .Case("enqcmd", HasENQCMD)
1091 .Case("f16c", HasF16C)
1092 .Case("fma", HasFMA)
1093 .Case("fma4", XOPLevel >= FMA4)
1094 .Case("fsgsbase", HasFSGSBASE)
1095 .Case("fxsr", HasFXSR)
1096 .Case("gfni", HasGFNI)
1097 .Case("hreset", HasHRESET)
1098 .Case("invpcid", HasINVPCID)
1100 .Case("widekl", HasWIDEKL)
1101 .Case("lwp", HasLWP)
1102 .Case("lzcnt", HasLZCNT)
1103 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1104 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1105 .Case("mmx", MMX3DNowLevel >= MMX)
1106 .Case("movbe", HasMOVBE)
1107 .Case("movdiri", HasMOVDIRI)
1108 .Case("movdir64b", HasMOVDIR64B)
1109 .Case("mwaitx", HasMWAITX)
1110 .Case("pclmul", HasPCLMUL)
1111 .Case("pconfig", HasPCONFIG)
1112 .Case("pku", HasPKU)
1113 .Case("popcnt", HasPOPCNT)
1114 .Case("prefetchi", HasPREFETCHI)
1115 .Case("prefetchwt1", HasPREFETCHWT1)
1116 .Case("prfchw", HasPRFCHW)
1117 .Case("ptwrite", HasPTWRITE)
1118 .Case("raoint", HasRAOINT)
1119 .Case("rdpid", HasRDPID)
1120 .Case("rdpru", HasRDPRU)
1121 .Case("rdrnd", HasRDRND)
1122 .Case("rdseed", HasRDSEED)
1123 .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1124 .Case("rtm", HasRTM)
1125 .Case("sahf", HasLAHFSAHF)
1126 .Case("serialize", HasSERIALIZE)
1127 .Case("sgx", HasSGX)
1128 .Case("sha", HasSHA)
1129 .Case("sha512", HasSHA512)
1130 .Case("shstk", HasSHSTK)
1131 .Case("sm3", HasSM3)
1132 .Case("sm4", HasSM4)
1133 .Case("sse", SSELevel >= SSE1)
1134 .Case("sse2", SSELevel >= SSE2)
1135 .Case("sse3", SSELevel >= SSE3)
1136 .Case("ssse3", SSELevel >= SSSE3)
1137 .Case("sse4.1", SSELevel >= SSE41)
1138 .Case("sse4.2", SSELevel >= SSE42)
1139 .Case("sse4a", XOPLevel >= SSE4A)
1140 .Case("tbm", HasTBM)
1141 .Case("tsxldtrk", HasTSXLDTRK)
1142 .Case("uintr", HasUINTR)
1143 .Case("vaes", HasVAES)
1144 .Case("vpclmulqdq", HasVPCLMULQDQ)
1145 .Case("wbnoinvd", HasWBNOINVD)
1146 .Case("waitpkg", HasWAITPKG)
1148 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1149 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1150 .Case("x87", HasX87)
1151 .Case("xop", XOPLevel >= XOP)
1152 .Case("xsave", HasXSAVE)
1153 .Case("xsavec", HasXSAVEC)
1154 .Case("xsaves", HasXSAVES)
1155 .Case("xsaveopt", HasXSAVEOPT)
1156 .Case("fullbf16", HasFullBFloat16)
1160 // We can't use a generic validation scheme for the features accepted here
1161 // versus subtarget features accepted in the target attribute because the
1162 // bitfield structure that's initialized in the runtime only supports the
1163 // below currently rather than the full range of subtarget features. (See
1164 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1165 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1166 return llvm::StringSwitch<bool>(FeatureStr)
1167 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1168 #include "llvm/TargetParser/X86TargetParser.def"
1172 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1173 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1174 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
1175 .Case(STR, llvm::X86::FEATURE_##ENUM)
1177 #include "llvm/TargetParser/X86TargetParser.def"
1179 // Note, this function should only be used after ensuring the value is
1180 // correct, so it asserts if the value is out of range.
1183 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1184 // Valid CPUs have a 'key feature' that compares just better than its key
1186 using namespace llvm::X86;
1187 CPUKind Kind = parseArchX86(Name);
1188 if (Kind != CK_None) {
1189 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1190 return (getFeaturePriority(KeyFeature) << 1) + 1;
1193 // Now we know we have a feature, so get its priority and shift it a few so
1194 // that we have sufficient room for the CPUs (above).
1195 return getFeaturePriority(getFeature(Name)) << 1;
1198 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1199 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1202 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1203 return llvm::X86::getCPUDispatchMangling(Name);
1206 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1207 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1208 SmallVector<StringRef, 32> TargetCPUFeatures;
1209 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true);
1210 for (auto &F : TargetCPUFeatures)
1211 Features.push_back(F);
1214 // We can't use a generic validation scheme for the cpus accepted here
1215 // versus subtarget cpus accepted in the target attribute because the
1216 // variables intitialized by the runtime only support the below currently
1217 // rather than the full range of cpus.
1218 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1219 return llvm::StringSwitch<bool>(FeatureStr)
1220 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1221 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1222 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1223 #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1224 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1225 #include "llvm/TargetParser/X86TargetParser.def"
1229 static unsigned matchAsmCCConstraint(const char *Name) {
1230 auto RV = llvm::StringSwitch<unsigned>(Name)
1263 bool X86TargetInfo::validateAsmConstraint(
1264 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1268 // Constant constraints.
1269 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1271 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1272 // x86_64 instructions.
1274 Info.setRequiresImmediate();
1277 Info.setRequiresImmediate(0, 31);
1280 Info.setRequiresImmediate(0, 63);
1283 Info.setRequiresImmediate(-128, 127);
1286 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1289 Info.setRequiresImmediate(0, 3);
1292 Info.setRequiresImmediate(0, 255);
1295 Info.setRequiresImmediate(0, 127);
1297 // Register constraints.
1298 case 'Y': // 'Y' is the first character for several 2-character constraints.
1299 // Shift the pointer to the second character of the constraint.
1304 case 'z': // First SSE register.
1306 case 't': // Any SSE register, when SSE2 is enabled.
1307 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1308 case 'm': // Any MMX register, when inter-unit moves enabled.
1309 case 'k': // AVX512 arch mask registers: k1-k7.
1310 Info.setAllowsRegister();
1313 case 'f': // Any x87 floating point stack register.
1314 // Constraint 'f' cannot be used for output operands.
1315 if (Info.ConstraintStr[0] == '=')
1317 Info.setAllowsRegister();
1325 case 'A': // edx:eax.
1326 case 't': // Top of floating point stack.
1327 case 'u': // Second from top of floating point stack.
1328 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1329 case 'y': // Any MMX register.
1330 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1331 case 'x': // Any SSE register.
1332 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1333 // for intermideate k reg operations).
1334 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1335 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1336 case 'l': // "Index" registers: any general register that can be used as an
1337 // index in a base+index memory access.
1338 Info.setAllowsRegister();
1340 // Floating point constant constraints.
1341 case 'C': // SSE floating point constant.
1342 case 'G': // x87 floating point constant.
1345 // CC condition changes.
1346 if (auto Len = matchAsmCCConstraint(Name)) {
1348 Info.setAllowsRegister();
1355 // Below is based on the following information:
1356 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1357 // | Processor Name | Cache Line Size (Bytes) | Source |
1358 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1359 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1360 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1361 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1362 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1363 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1364 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1365 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1366 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1367 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1368 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1369 // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1370 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1371 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1372 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1373 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1374 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1375 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1376 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1377 std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1378 using namespace llvm::X86;
1418 case CK_GoldmontPlus:
1422 case CK_SandyBridge:
1426 case CK_SkylakeClient:
1427 case CK_SkylakeServer:
1428 case CK_Cascadelake:
1433 case CK_SapphireRapids:
1434 case CK_IcelakeClient:
1436 case CK_IcelakeServer:
1440 case CK_Sierraforest:
1442 case CK_Graniterapids:
1443 case CK_GraniterapidsD:
1444 case CK_Emeraldrapids:
1477 // The following currently have unknown cache line sizes (but they are probably all 64):
1480 return std::nullopt;
1482 llvm_unreachable("Unknown CPU kind");
1485 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1486 StringRef Constraint,
1487 unsigned Size) const {
1488 // Strip off constraint modifiers.
1489 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1490 Constraint = Constraint.substr(1);
1492 return validateOperandSize(FeatureMap, Constraint, Size);
1495 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1496 StringRef Constraint,
1497 unsigned Size) const {
1498 return validateOperandSize(FeatureMap, Constraint, Size);
1501 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1502 StringRef Constraint,
1503 unsigned Size) const {
1504 switch (Constraint[0]) {
1508 // Registers k0-k7 (AVX512) size limit is 64 bit.
1516 // 'Y' is the first character for several 2-character constraints.
1517 switch (Constraint[1]) {
1521 // 'Ym' is synonymous with 'y'.
1526 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1527 // ZMM0 can be used if target supports AVX512F.
1528 return Size <= 512U;
1529 else if (hasFeatureEnabled(FeatureMap, "avx"))
1530 // YMM0 can be used if target supports AVX.
1531 return Size <= 256U;
1532 else if (hasFeatureEnabled(FeatureMap, "sse"))
1533 return Size <= 128U;
1538 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1539 if (SSELevel < SSE2)
1546 if (hasFeatureEnabled(FeatureMap, "avx512f"))
1547 // 512-bit zmm registers can be used if target supports AVX512F.
1548 return Size <= 512U;
1549 else if (hasFeatureEnabled(FeatureMap, "avx"))
1550 // 256-bit ymm registers can be used if target supports AVX.
1551 return Size <= 256U;
1552 return Size <= 128U;
1559 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1560 switch (*Constraint) {
1562 if (auto Len = matchAsmCCConstraint(Constraint)) {
1563 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1564 Constraint += Len - 1;
1567 return std::string(1, *Constraint);
1569 return std::string("{ax}");
1571 return std::string("{bx}");
1573 return std::string("{cx}");
1575 return std::string("{dx}");
1577 return std::string("{si}");
1579 return std::string("{di}");
1580 case 'p': // Keep 'p' constraint (address).
1581 return std::string("p");
1582 case 't': // top of floating point stack.
1583 return std::string("{st}");
1584 case 'u': // second from top of floating point stack.
1585 return std::string("{st(1)}"); // second from top of floating point stack.
1587 switch (Constraint[1]) {
1589 // Break from inner switch and fall through (copy single char),
1590 // continue parsing after copying the current constraint into
1591 // the return string.
1599 // "^" hints llvm that this is a 2 letter constraint.
1600 // "Constraint++" is used to promote the string iterator
1601 // to the next constraint.
1602 return std::string("^") + std::string(Constraint++, 2);
1606 return std::string(1, *Constraint);
1610 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1611 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1612 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1615 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1616 llvm::X86::fillValidTuneCPUList(Values);
1619 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1620 return llvm::ArrayRef(GCCRegNames);
1623 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1624 return llvm::ArrayRef(AddlRegNames);
1627 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1628 return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1629 Builtin::FirstTSBuiltin + 1);
1632 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1633 return llvm::ArrayRef(BuiltinInfoX86,
1634 X86::LastTSBuiltin - Builtin::FirstTSBuiltin);