1 //===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #include "clang/Driver/Driver.h"
11 #include "clang/Driver/DriverDiagnostic.h"
12 #include "clang/Driver/Options.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/Option/ArgList.h"
15 #include "llvm/Support/TargetParser.h"
17 using namespace clang::driver;
18 using namespace clang::driver::tools;
19 using namespace clang;
20 using namespace llvm::opt;
23 int arm::getARMSubArchVersionNumber(const llvm::Triple &Triple) {
24 llvm::StringRef Arch = Triple.getArchName();
25 return llvm::ARM::parseArchVersion(Arch);
29 bool arm::isARMMProfile(const llvm::Triple &Triple) {
30 llvm::StringRef Arch = Triple.getArchName();
31 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::M;
34 // Get Arch/CPU from args.
35 void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch,
36 llvm::StringRef &CPU, bool FromAs) {
37 if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ))
39 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
45 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
46 StringRef Value = A->getValue();
47 if (Value.startswith("-mcpu="))
48 CPU = Value.substr(6);
49 if (Value.startswith("-march="))
50 Arch = Value.substr(7);
55 // FIXME: Use ARMTargetParser.
56 static void getARMHWDivFeatures(const Driver &D, const Arg *A,
57 const ArgList &Args, StringRef HWDiv,
58 std::vector<StringRef> &Features) {
59 unsigned HWDivID = llvm::ARM::parseHWDiv(HWDiv);
60 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
61 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
65 static void getARMFPUFeatures(const Driver &D, const Arg *A,
66 const ArgList &Args, StringRef FPU,
67 std::vector<StringRef> &Features) {
68 unsigned FPUID = llvm::ARM::parseFPU(FPU);
69 if (!llvm::ARM::getFPUFeatures(FPUID, Features))
70 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
73 // Decode ARM features from string like +[no]featureA+[no]featureB+...
74 static bool DecodeARMFeatures(const Driver &D, StringRef text,
75 StringRef CPU, llvm::ARM::ArchKind ArchKind,
76 std::vector<StringRef> &Features) {
77 SmallVector<StringRef, 8> Split;
78 text.split(Split, StringRef("+"), -1, false);
80 for (StringRef Feature : Split) {
81 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features))
87 static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
88 std::vector<StringRef> &Features) {
89 CPU = CPU.split("+").first;
90 if (CPU != "generic") {
91 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
92 unsigned Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
93 llvm::ARM::getExtensionFeatures(Extension, Features);
97 // Check if -march is valid by checking if it can be canonicalised and parsed.
98 // getARMArch is used here instead of just checking the -march value in order
99 // to handle -march=native correctly.
100 static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
101 llvm::StringRef ArchName, llvm::StringRef CPUName,
102 std::vector<StringRef> &Features,
103 const llvm::Triple &Triple) {
104 std::pair<StringRef, StringRef> Split = ArchName.split("+");
106 std::string MArch = arm::getARMArch(ArchName, Triple);
107 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseArch(MArch);
108 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
109 (Split.second.size() && !DecodeARMFeatures(
110 D, Split.second, CPUName, ArchKind, Features)))
111 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
114 // Check -mcpu=. Needs ArchName to handle -mcpu=generic.
115 static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
116 llvm::StringRef CPUName, llvm::StringRef ArchName,
117 std::vector<StringRef> &Features,
118 const llvm::Triple &Triple) {
119 std::pair<StringRef, StringRef> Split = CPUName.split("+");
121 std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
122 llvm::ARM::ArchKind ArchKind =
123 arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
124 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
125 (Split.second.size() && !DecodeARMFeatures(
126 D, Split.second, CPU, ArchKind, Features)))
127 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
130 bool arm::useAAPCSForMachO(const llvm::Triple &T) {
131 // The backend is hardwired to assume AAPCS for M-class processors, ensure
132 // the frontend matches that.
133 return T.getEnvironment() == llvm::Triple::EABI ||
134 T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T);
137 // Select mode for reading thread pointer (-mtp=soft/cp15).
138 arm::ReadTPMode arm::getReadTPMode(const ToolChain &TC, const ArgList &Args) {
139 if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
140 const Driver &D = TC.getDriver();
141 arm::ReadTPMode ThreadPointer =
142 llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
143 .Case("cp15", ReadTPMode::Cp15)
144 .Case("soft", ReadTPMode::Soft)
145 .Default(ReadTPMode::Invalid);
146 if (ThreadPointer != ReadTPMode::Invalid)
147 return ThreadPointer;
148 if (StringRef(A->getValue()).empty())
149 D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
151 D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
152 return ReadTPMode::Invalid;
154 return ReadTPMode::Soft;
157 // Select the float ABI as determined by -msoft-float, -mhard-float, and
159 arm::FloatABI arm::getARMFloatABI(const ToolChain &TC, const ArgList &Args) {
160 const Driver &D = TC.getDriver();
161 const llvm::Triple &Triple = TC.getEffectiveTriple();
162 auto SubArch = getARMSubArchVersionNumber(Triple);
163 arm::FloatABI ABI = FloatABI::Invalid;
165 Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
166 options::OPT_mfloat_abi_EQ)) {
167 if (A->getOption().matches(options::OPT_msoft_float)) {
168 ABI = FloatABI::Soft;
169 } else if (A->getOption().matches(options::OPT_mhard_float)) {
170 ABI = FloatABI::Hard;
172 ABI = llvm::StringSwitch<arm::FloatABI>(A->getValue())
173 .Case("soft", FloatABI::Soft)
174 .Case("softfp", FloatABI::SoftFP)
175 .Case("hard", FloatABI::Hard)
176 .Default(FloatABI::Invalid);
177 if (ABI == FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
178 D.Diag(diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
179 ABI = FloatABI::Soft;
183 // It is incorrect to select hard float ABI on MachO platforms if the ABI is
185 if (Triple.isOSBinFormatMachO() && !useAAPCSForMachO(Triple) &&
186 ABI == FloatABI::Hard) {
187 D.Diag(diag::err_drv_unsupported_opt_for_target) << A->getAsString(Args)
188 << Triple.getArchName();
192 // If unspecified, choose the default based on the platform.
193 if (ABI == FloatABI::Invalid) {
194 switch (Triple.getOS()) {
195 case llvm::Triple::Darwin:
196 case llvm::Triple::MacOSX:
197 case llvm::Triple::IOS:
198 case llvm::Triple::TvOS: {
199 // Darwin defaults to "softfp" for v6 and v7.
200 ABI = (SubArch == 6 || SubArch == 7) ? FloatABI::SoftFP : FloatABI::Soft;
201 ABI = Triple.isWatchABI() ? FloatABI::Hard : ABI;
204 case llvm::Triple::WatchOS:
205 ABI = FloatABI::Hard;
208 // FIXME: this is invalid for WindowsCE
209 case llvm::Triple::Win32:
210 ABI = FloatABI::Hard;
213 case llvm::Triple::NetBSD:
214 switch (Triple.getEnvironment()) {
215 case llvm::Triple::EABIHF:
216 case llvm::Triple::GNUEABIHF:
217 ABI = FloatABI::Hard;
220 ABI = FloatABI::Soft;
225 case llvm::Triple::FreeBSD:
226 switch (Triple.getEnvironment()) {
227 case llvm::Triple::GNUEABIHF:
228 ABI = FloatABI::Hard;
231 // FreeBSD defaults to soft float
232 ABI = FloatABI::Soft;
237 case llvm::Triple::OpenBSD:
238 ABI = FloatABI::SoftFP;
242 switch (Triple.getEnvironment()) {
243 case llvm::Triple::GNUEABIHF:
244 case llvm::Triple::MuslEABIHF:
245 case llvm::Triple::EABIHF:
246 ABI = FloatABI::Hard;
248 case llvm::Triple::GNUEABI:
249 case llvm::Triple::MuslEABI:
250 case llvm::Triple::EABI:
251 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp
252 ABI = FloatABI::SoftFP;
254 case llvm::Triple::Android:
255 ABI = (SubArch >= 7) ? FloatABI::SoftFP : FloatABI::Soft;
258 // Assume "soft", but warn the user we are guessing.
259 if (Triple.isOSBinFormatMachO() &&
260 Triple.getSubArch() == llvm::Triple::ARMSubArch_v7em)
261 ABI = FloatABI::Hard;
263 ABI = FloatABI::Soft;
265 if (Triple.getOS() != llvm::Triple::UnknownOS ||
266 !Triple.isOSBinFormatMachO())
267 D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft";
273 assert(ABI != FloatABI::Invalid && "must select an ABI");
277 void arm::getARMTargetFeatures(const ToolChain &TC,
278 const llvm::Triple &Triple,
280 ArgStringList &CmdArgs,
281 std::vector<StringRef> &Features,
283 const Driver &D = TC.getDriver();
286 Args.hasArg(options::OPT_mkernel, options::OPT_fapple_kext);
287 arm::FloatABI ABI = arm::getARMFloatABI(TC, Args);
288 arm::ReadTPMode ThreadPointer = arm::getReadTPMode(TC, Args);
289 const Arg *WaCPU = nullptr, *WaFPU = nullptr;
290 const Arg *WaHDiv = nullptr, *WaArch = nullptr;
292 // This vector will accumulate features from the architecture
293 // extension suffixes on -mcpu and -march (e.g. the 'bar' in
294 // -mcpu=foo+bar). We want to apply those after the features derived
295 // from the FPU, in case -mfpu generates a negative feature which
296 // the +bar is supposed to override.
297 std::vector<StringRef> ExtensionFeatures;
300 // FIXME: Note, this is a hack, the LLVM backend doesn't actually use these
301 // yet (it uses the -mfloat-abi and -msoft-float options), and it is
302 // stripped out by the ARM target. We should probably pass this a new
303 // -target-option, which is handled by the -cc1/-cc1as invocation.
305 // FIXME2: For consistency, it would be ideal if we set up the target
306 // machine state the same when using the frontend or the assembler. We don't
307 // currently do that for the assembler, we pass the options directly to the
308 // backend and never even instantiate the frontend TargetInfo. If we did,
309 // and used its handleTargetFeatures hook, then we could ensure the
310 // assembler and the frontend behave the same.
312 // Use software floating point operations?
313 if (ABI == arm::FloatABI::Soft)
314 Features.push_back("+soft-float");
316 // Use software floating point argument passing?
317 if (ABI != arm::FloatABI::Hard)
318 Features.push_back("+soft-float-abi");
320 // Here, we make sure that -Wa,-mfpu/cpu/arch/hwdiv will be passed down
321 // to the assembler correctly.
323 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
324 StringRef Value = A->getValue();
325 if (Value.startswith("-mfpu=")) {
327 } else if (Value.startswith("-mcpu=")) {
329 } else if (Value.startswith("-mhwdiv=")) {
331 } else if (Value.startswith("-march=")) {
337 if (ThreadPointer == arm::ReadTPMode::Cp15)
338 Features.push_back("+read-tp-hard");
340 const Arg *ArchArg = Args.getLastArg(options::OPT_march_EQ);
341 const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
345 // Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
348 D.Diag(clang::diag::warn_drv_unused_argument)
349 << CPUArg->getAsString(Args);
350 CPUName = StringRef(WaCPU->getValue()).substr(6);
353 CPUName = CPUArg->getValue();
355 // Check -march. ClangAs gives preference to -Wa,-march=.
358 D.Diag(clang::diag::warn_drv_unused_argument)
359 << ArchArg->getAsString(Args);
360 ArchName = StringRef(WaArch->getValue()).substr(7);
361 checkARMArchName(D, WaArch, Args, ArchName, CPUName,
362 ExtensionFeatures, Triple);
364 D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
365 } else if (ArchArg) {
366 ArchName = ArchArg->getValue();
367 checkARMArchName(D, ArchArg, Args, ArchName, CPUName,
368 ExtensionFeatures, Triple);
371 // Add CPU features for generic CPUs
372 if (CPUName == "native") {
373 llvm::StringMap<bool> HostFeatures;
374 if (llvm::sys::getHostCPUFeatures(HostFeatures))
375 for (auto &F : HostFeatures)
377 Args.MakeArgString((F.second ? "+" : "-") + F.first()));
378 } else if (!CPUName.empty()) {
379 // This sets the default features for the specified CPU. We certainly don't
380 // want to override the features that have been explicitly specified on the
381 // command line. Therefore, process them directly instead of appending them
383 DecodeARMFeaturesFromCPU(D, CPUName, Features);
387 checkARMCPUName(D, CPUArg, Args, CPUName, ArchName,
388 ExtensionFeatures, Triple);
389 // Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
390 const Arg *FPUArg = Args.getLastArg(options::OPT_mfpu_EQ);
393 D.Diag(clang::diag::warn_drv_unused_argument)
394 << FPUArg->getAsString(Args);
395 getARMFPUFeatures(D, WaFPU, Args, StringRef(WaFPU->getValue()).substr(6),
398 getARMFPUFeatures(D, FPUArg, Args, FPUArg->getValue(), Features);
399 } else if (Triple.isAndroid() && getARMSubArchVersionNumber(Triple) >= 7) {
400 const char *AndroidFPU = "neon";
401 if (!llvm::ARM::getFPUFeatures(llvm::ARM::parseFPU(AndroidFPU), Features))
402 D.Diag(clang::diag::err_drv_clang_unsupported)
403 << std::string("-mfpu=") + AndroidFPU;
406 // Now we've finished accumulating features from arch, cpu and fpu,
407 // we can append the ones for architecture extensions that we
408 // collected separately.
409 Features.insert(std::end(Features),
410 std::begin(ExtensionFeatures), std::end(ExtensionFeatures));
412 // Honor -mhwdiv=. ClangAs gives preference to -Wa,-mhwdiv=.
413 const Arg *HDivArg = Args.getLastArg(options::OPT_mhwdiv_EQ);
416 D.Diag(clang::diag::warn_drv_unused_argument)
417 << HDivArg->getAsString(Args);
418 getARMHWDivFeatures(D, WaHDiv, Args,
419 StringRef(WaHDiv->getValue()).substr(8), Features);
421 getARMHWDivFeatures(D, HDivArg, Args, HDivArg->getValue(), Features);
423 // Handle (arch-dependent) fp16fml/fullfp16 relationship.
424 // Must happen before any features are disabled due to soft-float.
425 // FIXME: this fp16fml option handling will be reimplemented after the
426 // TargetParser rewrite.
427 const auto ItRNoFullFP16 = std::find(Features.rbegin(), Features.rend(), "-fullfp16");
428 const auto ItRFP16FML = std::find(Features.rbegin(), Features.rend(), "+fp16fml");
429 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_4a) {
430 const auto ItRFullFP16 = std::find(Features.rbegin(), Features.rend(), "+fullfp16");
431 if (ItRFullFP16 < ItRNoFullFP16 && ItRFullFP16 < ItRFP16FML) {
432 // Only entangled feature that can be to the right of this +fullfp16 is -fp16fml.
433 // Only append the +fp16fml if there is no -fp16fml after the +fullfp16.
434 if (std::find(Features.rbegin(), ItRFullFP16, "-fp16fml") == ItRFullFP16)
435 Features.push_back("+fp16fml");
438 goto fp16_fml_fallthrough;
441 fp16_fml_fallthrough:
442 // In both of these cases, putting the 'other' feature on the end of the vector will
443 // result in the same effect as placing it immediately after the current feature.
444 if (ItRNoFullFP16 < ItRFP16FML)
445 Features.push_back("-fp16fml");
446 else if (ItRNoFullFP16 > ItRFP16FML)
447 Features.push_back("+fullfp16");
450 // Setting -msoft-float/-mfloat-abi=soft effectively disables the FPU (GCC
451 // ignores the -mfpu options in this case).
452 // Note that the ABI can also be set implicitly by the target selected.
453 if (ABI == arm::FloatABI::Soft) {
454 llvm::ARM::getFPUFeatures(llvm::ARM::FK_NONE, Features);
456 // Disable all features relating to hardware FP.
457 // FIXME: Disabling fpregs should be enough all by itself, since all
458 // the other FP features are dependent on it. However
459 // there is currently no easy way to test this in clang, so for
460 // now just be explicit and disable all known dependent features
462 for (std::string Feature : {
463 "vfp2", "vfp2sp", "vfp2d16", "vfp2d16sp",
464 "vfp3", "vfp3sp", "vfp3d16", "vfp3d16sp",
465 "vfp4", "vfp4sp", "vfp4d16", "vfp4d16sp",
466 "fp-armv8", "fp-armv8sp", "fp-armv8d16", "fp-armv8d16sp",
467 "fullfp16", "neon", "crypto", "dotprod", "fp16fml",
468 "fp64", "d32", "fpregs"})
469 Features.push_back(Args.MakeArgString("-" + Feature));
472 // En/disable crc code generation.
473 if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
474 if (A->getOption().matches(options::OPT_mcrc))
475 Features.push_back("+crc");
477 Features.push_back("-crc");
480 // For Arch >= ARMv8.0: crypto = sha2 + aes
481 // FIXME: this needs reimplementation after the TargetParser rewrite
482 if (ArchName.find_lower("armv8a") != StringRef::npos ||
483 ArchName.find_lower("armv8.1a") != StringRef::npos ||
484 ArchName.find_lower("armv8.2a") != StringRef::npos ||
485 ArchName.find_lower("armv8.3a") != StringRef::npos ||
486 ArchName.find_lower("armv8.4a") != StringRef::npos) {
487 if (ArchName.find_lower("+crypto") != StringRef::npos) {
488 if (ArchName.find_lower("+nosha2") == StringRef::npos)
489 Features.push_back("+sha2");
490 if (ArchName.find_lower("+noaes") == StringRef::npos)
491 Features.push_back("+aes");
492 } else if (ArchName.find_lower("-crypto") != StringRef::npos) {
493 if (ArchName.find_lower("+sha2") == StringRef::npos)
494 Features.push_back("-sha2");
495 if (ArchName.find_lower("+aes") == StringRef::npos)
496 Features.push_back("-aes");
500 // CMSE: Check for target 8M (for -mcmse to be applicable) is performed later.
501 if (Args.getLastArg(options::OPT_mcmse))
502 Features.push_back("+8msecext");
504 // Look for the last occurrence of -mlong-calls or -mno-long-calls. If
505 // neither options are specified, see if we are compiling for kernel/kext and
506 // decide whether to pass "+long-calls" based on the OS and its version.
507 if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
508 options::OPT_mno_long_calls)) {
509 if (A->getOption().matches(options::OPT_mlong_calls))
510 Features.push_back("+long-calls");
511 } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
512 !Triple.isWatchOS()) {
513 Features.push_back("+long-calls");
516 // Generate execute-only output (no data access to code sections).
517 // This only makes sense for the compiler, not for the assembler.
519 // Supported only on ARMv6T2 and ARMv7 and above.
520 // Cannot be combined with -mno-movt or -mlong-calls
521 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
522 if (A->getOption().matches(options::OPT_mexecute_only)) {
523 if (getARMSubArchVersionNumber(Triple) < 7 &&
524 llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2)
525 D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
526 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
527 D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
528 // Long calls create constant pool entries and have not yet been fixed up
529 // to play nicely with execute-only. Hence, they cannot be used in
530 // execute-only code for now
531 else if (Arg *B = Args.getLastArg(options::OPT_mlong_calls, options::OPT_mno_long_calls)) {
532 if (B->getOption().matches(options::OPT_mlong_calls))
533 D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
535 Features.push_back("+execute-only");
540 // Kernel code has more strict alignment requirements.
542 Features.push_back("+strict-align");
543 else if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
544 options::OPT_munaligned_access)) {
545 if (A->getOption().matches(options::OPT_munaligned_access)) {
546 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
547 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
548 D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
549 // v8M Baseline follows on from v6M, so doesn't support unaligned memory
551 else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
552 D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
554 Features.push_back("+strict-align");
556 // Assume pre-ARMv6 doesn't support unaligned accesses.
558 // ARMv6 may or may not support unaligned accesses depending on the
559 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
560 // Darwin and NetBSD targets support unaligned accesses, and others don't.
562 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
563 // which raises an alignment fault on unaligned accesses. Linux
564 // defaults this bit to 0 and handles it as a system-wide (not
565 // per-process) setting. It is therefore safe to assume that ARMv7+
566 // Linux targets support unaligned accesses. The same goes for NaCl.
568 // The above behavior is consistent with GCC.
569 int VersionNum = getARMSubArchVersionNumber(Triple);
570 if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
571 if (VersionNum < 6 ||
572 Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
573 Features.push_back("+strict-align");
574 } else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
576 Features.push_back("+strict-align");
578 Features.push_back("+strict-align");
581 // llvm does not support reserving registers in general. There is support
582 // for reserving r9 on ARM though (defined as a platform-specific register
584 if (Args.hasArg(options::OPT_ffixed_r9))
585 Features.push_back("+reserve-r9");
587 // The kext linker doesn't know how to deal with movw/movt.
588 if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
589 Features.push_back("+no-movt");
591 if (Args.hasArg(options::OPT_mno_neg_immediates))
592 Features.push_back("+no-neg-immediates");
595 const std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
600 MArch = Triple.getArchName();
601 MArch = StringRef(MArch).split("+").first.lower();
603 // Handle -march=native.
604 if (MArch == "native") {
605 std::string CPU = llvm::sys::getHostCPUName();
606 if (CPU != "generic") {
607 // Translate the native cpu into the architecture suffix for that CPU.
608 StringRef Suffix = arm::getLLVMArchSuffixForARM(CPU, MArch, Triple);
609 // If there is no valid architecture suffix for this CPU we don't know how
610 // to handle it, so return no architecture.
614 MArch = std::string("arm") + Suffix.str();
621 /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
622 StringRef arm::getARMCPUForMArch(StringRef Arch, const llvm::Triple &Triple) {
623 std::string MArch = getARMArch(Arch, Triple);
624 // getARMCPUForArch defaults to the triple if MArch is empty, but empty MArch
625 // here means an -march=native that we can't handle, so instead return no CPU.
629 // We need to return an empty string here on invalid MArch values as the
630 // various places that call this function can't cope with a null result.
631 return Triple.getARMCPUForArch(MArch);
634 /// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
635 std::string arm::getARMTargetCPU(StringRef CPU, StringRef Arch,
636 const llvm::Triple &Triple) {
637 // FIXME: Warn on inconsistent use of -mcpu and -march.
638 // If we have -mcpu=, use that.
640 std::string MCPU = StringRef(CPU).split("+").first.lower();
641 // Handle -mcpu=native.
642 if (MCPU == "native")
643 return llvm::sys::getHostCPUName();
648 return getARMCPUForMArch(Arch, Triple);
651 /// getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a
652 /// particular CPU (or Arch, if CPU is generic). This is needed to
653 /// pass to functions like llvm::ARM::getDefaultFPU which need an
654 /// ArchKind as well as a CPU name.
655 llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef CPU, StringRef Arch,
656 const llvm::Triple &Triple) {
657 llvm::ARM::ArchKind ArchKind;
658 if (CPU == "generic") {
659 std::string ARMArch = tools::arm::getARMArch(Arch, Triple);
660 ArchKind = llvm::ARM::parseArch(ARMArch);
661 if (ArchKind == llvm::ARM::ArchKind::INVALID)
662 // In case of generic Arch, i.e. "arm",
663 // extract arch from default cpu of the Triple
664 ArchKind = llvm::ARM::parseCPUArch(Triple.getARMCPUForArch(ARMArch));
666 // FIXME: horrible hack to get around the fact that Cortex-A7 is only an
667 // armv7k triple if it's actually been specified via "-arch armv7k".
668 ArchKind = (Arch == "armv7k" || Arch == "thumbv7k")
669 ? llvm::ARM::ArchKind::ARMV7K
670 : llvm::ARM::parseCPUArch(CPU);
675 /// getLLVMArchSuffixForARM - Get the LLVM arch name to use for a particular
676 /// CPU (or Arch, if CPU is generic).
677 // FIXME: This is redundant with -mcpu, why does LLVM use this.
678 StringRef arm::getLLVMArchSuffixForARM(StringRef CPU, StringRef Arch,
679 const llvm::Triple &Triple) {
680 llvm::ARM::ArchKind ArchKind = getLLVMArchKindForARM(CPU, Arch, Triple);
681 if (ArchKind == llvm::ARM::ArchKind::INVALID)
683 return llvm::ARM::getSubArch(ArchKind);
686 void arm::appendBE8LinkFlag(const ArgList &Args, ArgStringList &CmdArgs,
687 const llvm::Triple &Triple) {
688 if (Args.hasArg(options::OPT_r))
691 // ARMv7 (and later) and ARMv6-M do not support BE-32, so instruct the linker
692 // to generate BE-8 executables.
693 if (arm::getARMSubArchVersionNumber(Triple) >= 7 || arm::isARMMProfile(Triple))
694 CmdArgs.push_back("--be8");