1 //===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #include "clang/Driver/Driver.h"
11 #include "clang/Driver/DriverDiagnostic.h"
12 #include "clang/Driver/Options.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/Option/ArgList.h"
15 #include "llvm/Support/TargetParser.h"
16 #include "llvm/Support/Host.h"
18 using namespace clang::driver;
19 using namespace clang::driver::tools;
20 using namespace clang;
21 using namespace llvm::opt;
24 int arm::getARMSubArchVersionNumber(const llvm::Triple &Triple) {
25 llvm::StringRef Arch = Triple.getArchName();
26 return llvm::ARM::parseArchVersion(Arch);
30 bool arm::isARMMProfile(const llvm::Triple &Triple) {
31 llvm::StringRef Arch = Triple.getArchName();
32 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::M;
35 // Get Arch/CPU from args.
36 void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch,
37 llvm::StringRef &CPU, bool FromAs) {
38 if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ))
40 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
46 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
47 StringRef Value = A->getValue();
48 if (Value.startswith("-mcpu="))
49 CPU = Value.substr(6);
50 if (Value.startswith("-march="))
51 Arch = Value.substr(7);
56 // FIXME: Use ARMTargetParser.
57 static void getARMHWDivFeatures(const Driver &D, const Arg *A,
58 const ArgList &Args, StringRef HWDiv,
59 std::vector<StringRef> &Features) {
60 uint64_t HWDivID = llvm::ARM::parseHWDiv(HWDiv);
61 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
62 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
66 static unsigned getARMFPUFeatures(const Driver &D, const Arg *A,
67 const ArgList &Args, StringRef FPU,
68 std::vector<StringRef> &Features) {
69 unsigned FPUID = llvm::ARM::parseFPU(FPU);
70 if (!llvm::ARM::getFPUFeatures(FPUID, Features))
71 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
75 // Decode ARM features from string like +[no]featureA+[no]featureB+...
76 static bool DecodeARMFeatures(const Driver &D, StringRef text,
77 StringRef CPU, llvm::ARM::ArchKind ArchKind,
78 std::vector<StringRef> &Features) {
79 SmallVector<StringRef, 8> Split;
80 text.split(Split, StringRef("+"), -1, false);
82 for (StringRef Feature : Split) {
83 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features))
89 static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
90 std::vector<StringRef> &Features) {
91 CPU = CPU.split("+").first;
92 if (CPU != "generic") {
93 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
94 uint64_t Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
95 llvm::ARM::getExtensionFeatures(Extension, Features);
99 // Check if -march is valid by checking if it can be canonicalised and parsed.
100 // getARMArch is used here instead of just checking the -march value in order
101 // to handle -march=native correctly.
102 static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
103 llvm::StringRef ArchName, llvm::StringRef CPUName,
104 std::vector<StringRef> &Features,
105 const llvm::Triple &Triple) {
106 std::pair<StringRef, StringRef> Split = ArchName.split("+");
108 std::string MArch = arm::getARMArch(ArchName, Triple);
109 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseArch(MArch);
110 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
111 (Split.second.size() && !DecodeARMFeatures(
112 D, Split.second, CPUName, ArchKind, Features)))
113 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
116 // Check -mcpu=. Needs ArchName to handle -mcpu=generic.
117 static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
118 llvm::StringRef CPUName, llvm::StringRef ArchName,
119 std::vector<StringRef> &Features,
120 const llvm::Triple &Triple) {
121 std::pair<StringRef, StringRef> Split = CPUName.split("+");
123 std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
124 llvm::ARM::ArchKind ArchKind =
125 arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
126 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
127 (Split.second.size() && !DecodeARMFeatures(
128 D, Split.second, CPU, ArchKind, Features)))
129 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
132 bool arm::useAAPCSForMachO(const llvm::Triple &T) {
133 // The backend is hardwired to assume AAPCS for M-class processors, ensure
134 // the frontend matches that.
135 return T.getEnvironment() == llvm::Triple::EABI ||
136 T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T);
139 // Select mode for reading thread pointer (-mtp=soft/cp15).
140 arm::ReadTPMode arm::getReadTPMode(const Driver &D, const ArgList &Args) {
141 if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
142 arm::ReadTPMode ThreadPointer =
143 llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
144 .Case("cp15", ReadTPMode::Cp15)
145 .Case("soft", ReadTPMode::Soft)
146 .Default(ReadTPMode::Invalid);
147 if (ThreadPointer != ReadTPMode::Invalid)
148 return ThreadPointer;
149 if (StringRef(A->getValue()).empty())
150 D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
152 D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
153 return ReadTPMode::Invalid;
155 return ReadTPMode::Soft;
158 arm::FloatABI arm::getARMFloatABI(const ToolChain &TC, const ArgList &Args) {
159 return arm::getARMFloatABI(TC.getDriver(), TC.getEffectiveTriple(), Args);
162 // Select the float ABI as determined by -msoft-float, -mhard-float, and
164 arm::FloatABI arm::getARMFloatABI(const Driver &D, const llvm::Triple &Triple,
165 const ArgList &Args) {
166 auto SubArch = getARMSubArchVersionNumber(Triple);
167 arm::FloatABI ABI = FloatABI::Invalid;
169 Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
170 options::OPT_mfloat_abi_EQ)) {
171 if (A->getOption().matches(options::OPT_msoft_float)) {
172 ABI = FloatABI::Soft;
173 } else if (A->getOption().matches(options::OPT_mhard_float)) {
174 ABI = FloatABI::Hard;
176 ABI = llvm::StringSwitch<arm::FloatABI>(A->getValue())
177 .Case("soft", FloatABI::Soft)
178 .Case("softfp", FloatABI::SoftFP)
179 .Case("hard", FloatABI::Hard)
180 .Default(FloatABI::Invalid);
181 if (ABI == FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
182 D.Diag(diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
183 ABI = FloatABI::Soft;
187 // It is incorrect to select hard float ABI on MachO platforms if the ABI is
189 if (Triple.isOSBinFormatMachO() && !useAAPCSForMachO(Triple) &&
190 ABI == FloatABI::Hard) {
191 D.Diag(diag::err_drv_unsupported_opt_for_target) << A->getAsString(Args)
192 << Triple.getArchName();
196 // If unspecified, choose the default based on the platform.
197 if (ABI == FloatABI::Invalid) {
198 switch (Triple.getOS()) {
199 case llvm::Triple::Darwin:
200 case llvm::Triple::MacOSX:
201 case llvm::Triple::IOS:
202 case llvm::Triple::TvOS: {
203 // Darwin defaults to "softfp" for v6 and v7.
204 ABI = (SubArch == 6 || SubArch == 7) ? FloatABI::SoftFP : FloatABI::Soft;
205 ABI = Triple.isWatchABI() ? FloatABI::Hard : ABI;
208 case llvm::Triple::WatchOS:
209 ABI = FloatABI::Hard;
212 // FIXME: this is invalid for WindowsCE
213 case llvm::Triple::Win32:
214 ABI = FloatABI::Hard;
217 case llvm::Triple::NetBSD:
218 switch (Triple.getEnvironment()) {
219 case llvm::Triple::EABIHF:
220 case llvm::Triple::GNUEABIHF:
221 ABI = FloatABI::Hard;
224 ABI = FloatABI::Soft;
229 case llvm::Triple::FreeBSD:
230 switch (Triple.getEnvironment()) {
231 case llvm::Triple::GNUEABIHF:
232 ABI = FloatABI::Hard;
235 // FreeBSD defaults to soft float
236 ABI = FloatABI::Soft;
241 case llvm::Triple::OpenBSD:
242 ABI = FloatABI::SoftFP;
246 switch (Triple.getEnvironment()) {
247 case llvm::Triple::GNUEABIHF:
248 case llvm::Triple::MuslEABIHF:
249 case llvm::Triple::EABIHF:
250 ABI = FloatABI::Hard;
252 case llvm::Triple::GNUEABI:
253 case llvm::Triple::MuslEABI:
254 case llvm::Triple::EABI:
255 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp
256 ABI = FloatABI::SoftFP;
258 case llvm::Triple::Android:
259 ABI = (SubArch >= 7) ? FloatABI::SoftFP : FloatABI::Soft;
262 // Assume "soft", but warn the user we are guessing.
263 if (Triple.isOSBinFormatMachO() &&
264 Triple.getSubArch() == llvm::Triple::ARMSubArch_v7em)
265 ABI = FloatABI::Hard;
267 ABI = FloatABI::Soft;
269 if (Triple.getOS() != llvm::Triple::UnknownOS ||
270 !Triple.isOSBinFormatMachO())
271 D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft";
277 assert(ABI != FloatABI::Invalid && "must select an ABI");
281 static bool hasIntegerMVE(const std::vector<StringRef> &F) {
282 auto MVE = llvm::find(llvm::reverse(F), "+mve");
283 auto NoMVE = llvm::find(llvm::reverse(F), "-mve");
284 return MVE != F.rend() &&
285 (NoMVE == F.rend() || std::distance(MVE, NoMVE) > 0);
288 void arm::getARMTargetFeatures(const Driver &D, const llvm::Triple &Triple,
289 const ArgList &Args, ArgStringList &CmdArgs,
290 std::vector<StringRef> &Features, bool ForAS) {
292 Args.hasArg(options::OPT_mkernel, options::OPT_fapple_kext);
293 arm::FloatABI ABI = arm::getARMFloatABI(D, Triple, Args);
294 arm::ReadTPMode ThreadPointer = arm::getReadTPMode(D, Args);
295 const Arg *WaCPU = nullptr, *WaFPU = nullptr;
296 const Arg *WaHDiv = nullptr, *WaArch = nullptr;
298 // This vector will accumulate features from the architecture
299 // extension suffixes on -mcpu and -march (e.g. the 'bar' in
300 // -mcpu=foo+bar). We want to apply those after the features derived
301 // from the FPU, in case -mfpu generates a negative feature which
302 // the +bar is supposed to override.
303 std::vector<StringRef> ExtensionFeatures;
306 // FIXME: Note, this is a hack, the LLVM backend doesn't actually use these
307 // yet (it uses the -mfloat-abi and -msoft-float options), and it is
308 // stripped out by the ARM target. We should probably pass this a new
309 // -target-option, which is handled by the -cc1/-cc1as invocation.
311 // FIXME2: For consistency, it would be ideal if we set up the target
312 // machine state the same when using the frontend or the assembler. We don't
313 // currently do that for the assembler, we pass the options directly to the
314 // backend and never even instantiate the frontend TargetInfo. If we did,
315 // and used its handleTargetFeatures hook, then we could ensure the
316 // assembler and the frontend behave the same.
318 // Use software floating point operations?
319 if (ABI == arm::FloatABI::Soft)
320 Features.push_back("+soft-float");
322 // Use software floating point argument passing?
323 if (ABI != arm::FloatABI::Hard)
324 Features.push_back("+soft-float-abi");
326 // Here, we make sure that -Wa,-mfpu/cpu/arch/hwdiv will be passed down
327 // to the assembler correctly.
329 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
330 StringRef Value = A->getValue();
331 if (Value.startswith("-mfpu=")) {
333 } else if (Value.startswith("-mcpu=")) {
335 } else if (Value.startswith("-mhwdiv=")) {
337 } else if (Value.startswith("-march=")) {
343 if (ThreadPointer == arm::ReadTPMode::Cp15)
344 Features.push_back("+read-tp-hard");
346 const Arg *ArchArg = Args.getLastArg(options::OPT_march_EQ);
347 const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
351 // Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
354 D.Diag(clang::diag::warn_drv_unused_argument)
355 << CPUArg->getAsString(Args);
356 CPUName = StringRef(WaCPU->getValue()).substr(6);
359 CPUName = CPUArg->getValue();
361 // Check -march. ClangAs gives preference to -Wa,-march=.
364 D.Diag(clang::diag::warn_drv_unused_argument)
365 << ArchArg->getAsString(Args);
366 ArchName = StringRef(WaArch->getValue()).substr(7);
367 checkARMArchName(D, WaArch, Args, ArchName, CPUName,
368 ExtensionFeatures, Triple);
370 D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
371 } else if (ArchArg) {
372 ArchName = ArchArg->getValue();
373 checkARMArchName(D, ArchArg, Args, ArchName, CPUName,
374 ExtensionFeatures, Triple);
377 // Add CPU features for generic CPUs
378 if (CPUName == "native") {
379 llvm::StringMap<bool> HostFeatures;
380 if (llvm::sys::getHostCPUFeatures(HostFeatures))
381 for (auto &F : HostFeatures)
383 Args.MakeArgString((F.second ? "+" : "-") + F.first()));
384 } else if (!CPUName.empty()) {
385 // This sets the default features for the specified CPU. We certainly don't
386 // want to override the features that have been explicitly specified on the
387 // command line. Therefore, process them directly instead of appending them
389 DecodeARMFeaturesFromCPU(D, CPUName, Features);
393 checkARMCPUName(D, CPUArg, Args, CPUName, ArchName,
394 ExtensionFeatures, Triple);
395 // Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
396 unsigned FPUID = llvm::ARM::FK_INVALID;
397 const Arg *FPUArg = Args.getLastArg(options::OPT_mfpu_EQ);
400 D.Diag(clang::diag::warn_drv_unused_argument)
401 << FPUArg->getAsString(Args);
402 (void)getARMFPUFeatures(D, WaFPU, Args, StringRef(WaFPU->getValue()).substr(6),
405 FPUID = getARMFPUFeatures(D, FPUArg, Args, FPUArg->getValue(), Features);
406 } else if (Triple.isAndroid() && getARMSubArchVersionNumber(Triple) >= 7) {
407 const char *AndroidFPU = "neon";
408 FPUID = llvm::ARM::parseFPU(AndroidFPU);
409 if (!llvm::ARM::getFPUFeatures(FPUID, Features))
410 D.Diag(clang::diag::err_drv_clang_unsupported)
411 << std::string("-mfpu=") + AndroidFPU;
414 // Now we've finished accumulating features from arch, cpu and fpu,
415 // we can append the ones for architecture extensions that we
416 // collected separately.
417 Features.insert(std::end(Features),
418 std::begin(ExtensionFeatures), std::end(ExtensionFeatures));
420 // Honor -mhwdiv=. ClangAs gives preference to -Wa,-mhwdiv=.
421 const Arg *HDivArg = Args.getLastArg(options::OPT_mhwdiv_EQ);
424 D.Diag(clang::diag::warn_drv_unused_argument)
425 << HDivArg->getAsString(Args);
426 getARMHWDivFeatures(D, WaHDiv, Args,
427 StringRef(WaHDiv->getValue()).substr(8), Features);
429 getARMHWDivFeatures(D, HDivArg, Args, HDivArg->getValue(), Features);
431 // Handle (arch-dependent) fp16fml/fullfp16 relationship.
432 // Must happen before any features are disabled due to soft-float.
433 // FIXME: this fp16fml option handling will be reimplemented after the
434 // TargetParser rewrite.
435 const auto ItRNoFullFP16 = std::find(Features.rbegin(), Features.rend(), "-fullfp16");
436 const auto ItRFP16FML = std::find(Features.rbegin(), Features.rend(), "+fp16fml");
437 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_4a) {
438 const auto ItRFullFP16 = std::find(Features.rbegin(), Features.rend(), "+fullfp16");
439 if (ItRFullFP16 < ItRNoFullFP16 && ItRFullFP16 < ItRFP16FML) {
440 // Only entangled feature that can be to the right of this +fullfp16 is -fp16fml.
441 // Only append the +fp16fml if there is no -fp16fml after the +fullfp16.
442 if (std::find(Features.rbegin(), ItRFullFP16, "-fp16fml") == ItRFullFP16)
443 Features.push_back("+fp16fml");
446 goto fp16_fml_fallthrough;
449 fp16_fml_fallthrough:
450 // In both of these cases, putting the 'other' feature on the end of the vector will
451 // result in the same effect as placing it immediately after the current feature.
452 if (ItRNoFullFP16 < ItRFP16FML)
453 Features.push_back("-fp16fml");
454 else if (ItRNoFullFP16 > ItRFP16FML)
455 Features.push_back("+fullfp16");
458 // Setting -msoft-float/-mfloat-abi=soft effectively disables the FPU (GCC
459 // ignores the -mfpu options in this case).
460 // Note that the ABI can also be set implicitly by the target selected.
461 if (ABI == arm::FloatABI::Soft) {
462 llvm::ARM::getFPUFeatures(llvm::ARM::FK_NONE, Features);
464 // Disable all features relating to hardware FP, not already disabled by the
466 Features.insert(Features.end(),
467 {"-dotprod", "-fp16fml", "-mve", "-mve.fp", "-fpregs"});
468 } else if (FPUID == llvm::ARM::FK_NONE) {
469 // -mfpu=none is *very* similar to -mfloat-abi=soft, only that it should not
471 Features.insert(Features.end(), {"-dotprod", "-fp16fml", "-mve.fp"});
472 if (!hasIntegerMVE(Features))
473 Features.emplace_back("-fpregs");
476 // En/disable crc code generation.
477 if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
478 if (A->getOption().matches(options::OPT_mcrc))
479 Features.push_back("+crc");
481 Features.push_back("-crc");
484 // For Arch >= ARMv8.0 && A profile: crypto = sha2 + aes
485 // FIXME: this needs reimplementation after the TargetParser rewrite
486 auto CryptoIt = llvm::find_if(llvm::reverse(Features), [](const StringRef F) {
487 return F.contains("crypto");
489 if (CryptoIt != Features.rend()) {
490 if (CryptoIt->take_front() == "+") {
491 StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
492 arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
493 if (llvm::ARM::parseArchVersion(ArchSuffix) >= 8 &&
494 llvm::ARM::parseArchProfile(ArchSuffix) ==
495 llvm::ARM::ProfileKind::A) {
496 if (ArchName.find_lower("+nosha2") == StringRef::npos &&
497 CPUName.find_lower("+nosha2") == StringRef::npos)
498 Features.push_back("+sha2");
499 if (ArchName.find_lower("+noaes") == StringRef::npos &&
500 CPUName.find_lower("+noaes") == StringRef::npos)
501 Features.push_back("+aes");
503 D.Diag(clang::diag::warn_target_unsupported_extension)
505 << llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
506 // With -fno-integrated-as -mfpu=crypto-neon-fp-armv8 some assemblers such as the GNU assembler
507 // will permit the use of crypto instructions as the fpu will override the architecture.
508 // We keep the crypto feature in this case to preserve compatibility.
509 // In all other cases we remove the crypto feature.
510 if (!Args.hasArg(options::OPT_fno_integrated_as))
511 Features.push_back("-crypto");
516 // CMSE: Check for target 8M (for -mcmse to be applicable) is performed later.
517 if (Args.getLastArg(options::OPT_mcmse))
518 Features.push_back("+8msecext");
520 // Look for the last occurrence of -mlong-calls or -mno-long-calls. If
521 // neither options are specified, see if we are compiling for kernel/kext and
522 // decide whether to pass "+long-calls" based on the OS and its version.
523 if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
524 options::OPT_mno_long_calls)) {
525 if (A->getOption().matches(options::OPT_mlong_calls))
526 Features.push_back("+long-calls");
527 } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
528 !Triple.isWatchOS()) {
529 Features.push_back("+long-calls");
532 // Generate execute-only output (no data access to code sections).
533 // This only makes sense for the compiler, not for the assembler.
535 // Supported only on ARMv6T2 and ARMv7 and above.
536 // Cannot be combined with -mno-movt or -mlong-calls
537 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
538 if (A->getOption().matches(options::OPT_mexecute_only)) {
539 if (getARMSubArchVersionNumber(Triple) < 7 &&
540 llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2)
541 D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
542 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
543 D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
544 // Long calls create constant pool entries and have not yet been fixed up
545 // to play nicely with execute-only. Hence, they cannot be used in
546 // execute-only code for now
547 else if (Arg *B = Args.getLastArg(options::OPT_mlong_calls, options::OPT_mno_long_calls)) {
548 if (B->getOption().matches(options::OPT_mlong_calls))
549 D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
551 Features.push_back("+execute-only");
556 // Kernel code has more strict alignment requirements.
558 Features.push_back("+strict-align");
559 else if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
560 options::OPT_munaligned_access)) {
561 if (A->getOption().matches(options::OPT_munaligned_access)) {
562 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
563 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
564 D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
565 // v8M Baseline follows on from v6M, so doesn't support unaligned memory
567 else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
568 D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
570 Features.push_back("+strict-align");
572 // Assume pre-ARMv6 doesn't support unaligned accesses.
574 // ARMv6 may or may not support unaligned accesses depending on the
575 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
576 // Darwin and NetBSD targets support unaligned accesses, and others don't.
578 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
579 // which raises an alignment fault on unaligned accesses. Linux
580 // defaults this bit to 0 and handles it as a system-wide (not
581 // per-process) setting. It is therefore safe to assume that ARMv7+
582 // Linux targets support unaligned accesses. The same goes for NaCl.
584 // The above behavior is consistent with GCC.
585 int VersionNum = getARMSubArchVersionNumber(Triple);
586 if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
587 if (VersionNum < 6 ||
588 Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
589 Features.push_back("+strict-align");
590 } else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
592 Features.push_back("+strict-align");
594 Features.push_back("+strict-align");
597 // llvm does not support reserving registers in general. There is support
598 // for reserving r9 on ARM though (defined as a platform-specific register
600 if (Args.hasArg(options::OPT_ffixed_r9))
601 Features.push_back("+reserve-r9");
603 // The kext linker doesn't know how to deal with movw/movt.
604 if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
605 Features.push_back("+no-movt");
607 if (Args.hasArg(options::OPT_mno_neg_immediates))
608 Features.push_back("+no-neg-immediates");
611 const std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
614 MArch = std::string(Arch);
616 MArch = std::string(Triple.getArchName());
617 MArch = StringRef(MArch).split("+").first.lower();
619 // Handle -march=native.
620 if (MArch == "native") {
621 std::string CPU = std::string(llvm::sys::getHostCPUName());
622 if (CPU != "generic") {
623 // Translate the native cpu into the architecture suffix for that CPU.
624 StringRef Suffix = arm::getLLVMArchSuffixForARM(CPU, MArch, Triple);
625 // If there is no valid architecture suffix for this CPU we don't know how
626 // to handle it, so return no architecture.
630 MArch = std::string("arm") + Suffix.str();
637 /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
638 StringRef arm::getARMCPUForMArch(StringRef Arch, const llvm::Triple &Triple) {
639 std::string MArch = getARMArch(Arch, Triple);
640 // getARMCPUForArch defaults to the triple if MArch is empty, but empty MArch
641 // here means an -march=native that we can't handle, so instead return no CPU.
645 // We need to return an empty string here on invalid MArch values as the
646 // various places that call this function can't cope with a null result.
647 return Triple.getARMCPUForArch(MArch);
650 /// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
651 std::string arm::getARMTargetCPU(StringRef CPU, StringRef Arch,
652 const llvm::Triple &Triple) {
653 // FIXME: Warn on inconsistent use of -mcpu and -march.
654 // If we have -mcpu=, use that.
656 std::string MCPU = StringRef(CPU).split("+").first.lower();
657 // Handle -mcpu=native.
658 if (MCPU == "native")
659 return std::string(llvm::sys::getHostCPUName());
664 return std::string(getARMCPUForMArch(Arch, Triple));
667 /// getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a
668 /// particular CPU (or Arch, if CPU is generic). This is needed to
669 /// pass to functions like llvm::ARM::getDefaultFPU which need an
670 /// ArchKind as well as a CPU name.
671 llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef CPU, StringRef Arch,
672 const llvm::Triple &Triple) {
673 llvm::ARM::ArchKind ArchKind;
674 if (CPU == "generic" || CPU.empty()) {
675 std::string ARMArch = tools::arm::getARMArch(Arch, Triple);
676 ArchKind = llvm::ARM::parseArch(ARMArch);
677 if (ArchKind == llvm::ARM::ArchKind::INVALID)
678 // In case of generic Arch, i.e. "arm",
679 // extract arch from default cpu of the Triple
680 ArchKind = llvm::ARM::parseCPUArch(Triple.getARMCPUForArch(ARMArch));
682 // FIXME: horrible hack to get around the fact that Cortex-A7 is only an
683 // armv7k triple if it's actually been specified via "-arch armv7k".
684 ArchKind = (Arch == "armv7k" || Arch == "thumbv7k")
685 ? llvm::ARM::ArchKind::ARMV7K
686 : llvm::ARM::parseCPUArch(CPU);
691 /// getLLVMArchSuffixForARM - Get the LLVM arch name to use for a particular
692 /// CPU (or Arch, if CPU is generic).
693 // FIXME: This is redundant with -mcpu, why does LLVM use this.
694 StringRef arm::getLLVMArchSuffixForARM(StringRef CPU, StringRef Arch,
695 const llvm::Triple &Triple) {
696 llvm::ARM::ArchKind ArchKind = getLLVMArchKindForARM(CPU, Arch, Triple);
697 if (ArchKind == llvm::ARM::ArchKind::INVALID)
699 return llvm::ARM::getSubArch(ArchKind);
702 void arm::appendBE8LinkFlag(const ArgList &Args, ArgStringList &CmdArgs,
703 const llvm::Triple &Triple) {
704 if (Args.hasArg(options::OPT_r))
707 // ARMv7 (and later) and ARMv6-M do not support BE-32, so instruct the linker
708 // to generate BE-8 executables.
709 if (arm::getARMSubArchVersionNumber(Triple) >= 7 || arm::isARMMProfile(Triple))
710 CmdArgs.push_back("--be8");