1 //===---------------------------- libunwind.h -----------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 // Compatible with libunwind API documented at:
9 // http://www.nongnu.org/libunwind/man/libunwind(3).html
11 //===----------------------------------------------------------------------===//
16 #include <__libunwind_config.h>
23 #if __has_include(<Availability.h>)
24 #include <Availability.h>
26 #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
27 #include <Availability.h>
31 #define LIBUNWIND_AVAIL __attribute__((unavailable))
32 #elif defined(__OSX_AVAILABLE_STARTING)
33 #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
35 #include <AvailabilityMacros.h>
36 #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
37 #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
39 #define LIBUNWIND_AVAIL __attribute__((unavailable))
43 #define LIBUNWIND_AVAIL
48 UNW_ESUCCESS = 0, /* no error */
49 UNW_EUNSPEC = -6540, /* unspecified (general) error */
50 UNW_ENOMEM = -6541, /* out of memory */
51 UNW_EBADREG = -6542, /* bad register number */
52 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */
53 UNW_ESTOPUNWIND = -6544, /* stop unwinding */
54 UNW_EINVALIDIP = -6545, /* invalid IP */
55 UNW_EBADFRAME = -6546, /* bad frame */
56 UNW_EINVAL = -6547, /* unsupported operation or bad value */
57 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */
58 UNW_ENOINFO = -6549 /* no unwind info found */
59 #if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
60 , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
64 struct unw_context_t {
65 uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
67 typedef struct unw_context_t unw_context_t;
70 uint64_t data[_LIBUNWIND_CURSOR_SIZE];
72 typedef struct unw_cursor_t unw_cursor_t;
74 typedef struct unw_addr_space *unw_addr_space_t;
76 typedef int unw_regnum_t;
77 typedef uintptr_t unw_word_t;
78 #if defined(__arm__) && !defined(__ARM_DWARF_EH__)
79 typedef uint64_t unw_fpreg_t;
81 typedef double unw_fpreg_t;
84 struct unw_proc_info_t {
85 unw_word_t start_ip; /* start address of function */
86 unw_word_t end_ip; /* address after end of function */
87 unw_word_t lsda; /* address of language specific data area, */
88 /* or zero if not used */
89 unw_word_t handler; /* personality routine, or zero if not used */
90 unw_word_t gp; /* not used */
91 unw_word_t flags; /* not used */
92 uint32_t format; /* compact unwind encoding, or zero if none */
93 uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */
94 unw_word_t unwind_info; /* address of DWARF unwind info, or zero */
95 unw_word_t extra; /* mach_header of mach-o image containing func */
97 typedef struct unw_proc_info_t unw_proc_info_t;
103 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
104 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
105 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
106 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
107 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
108 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
109 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL;
110 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
113 /* Save VFP registers in FSTMX format (instead of FSTMD). */
114 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
118 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
119 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
120 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
121 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
122 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
123 //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
125 extern unw_addr_space_t unw_local_addr_space;
131 // architecture independent register numbers
133 UNW_REG_IP = -1, // instruction pointer
134 UNW_REG_SP = -2, // stack pointer
137 // 32-bit x86 registers
149 // 64-bit x86_64 registers
168 UNW_X86_64_XMM0 = 17,
169 UNW_X86_64_XMM1 = 18,
170 UNW_X86_64_XMM2 = 19,
171 UNW_X86_64_XMM3 = 20,
172 UNW_X86_64_XMM4 = 21,
173 UNW_X86_64_XMM5 = 22,
174 UNW_X86_64_XMM6 = 23,
175 UNW_X86_64_XMM7 = 24,
176 UNW_X86_64_XMM8 = 25,
177 UNW_X86_64_XMM9 = 26,
178 UNW_X86_64_XMM10 = 27,
179 UNW_X86_64_XMM11 = 28,
180 UNW_X86_64_XMM12 = 29,
181 UNW_X86_64_XMM13 = 30,
182 UNW_X86_64_XMM14 = 31,
183 UNW_X86_64_XMM15 = 32,
187 // 32-bit ppc register numbers
298 UNW_PPC_VRSAVE = 109,
300 UNW_PPC_SPE_ACC = 111,
301 UNW_PPC_SPEFSCR = 112
304 // 64-bit ppc register numbers
415 // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
416 // Borrowing VRSAVE number from PPC32.
417 UNW_PPC64_VRSAVE = 109,
418 UNW_PPC64_VSCR = 110,
419 UNW_PPC64_TFHAR = 114,
420 UNW_PPC64_TFIAR = 115,
421 UNW_PPC64_TEXASR = 116,
422 UNW_PPC64_VS0 = UNW_PPC64_F0,
423 UNW_PPC64_VS1 = UNW_PPC64_F1,
424 UNW_PPC64_VS2 = UNW_PPC64_F2,
425 UNW_PPC64_VS3 = UNW_PPC64_F3,
426 UNW_PPC64_VS4 = UNW_PPC64_F4,
427 UNW_PPC64_VS5 = UNW_PPC64_F5,
428 UNW_PPC64_VS6 = UNW_PPC64_F6,
429 UNW_PPC64_VS7 = UNW_PPC64_F7,
430 UNW_PPC64_VS8 = UNW_PPC64_F8,
431 UNW_PPC64_VS9 = UNW_PPC64_F9,
432 UNW_PPC64_VS10 = UNW_PPC64_F10,
433 UNW_PPC64_VS11 = UNW_PPC64_F11,
434 UNW_PPC64_VS12 = UNW_PPC64_F12,
435 UNW_PPC64_VS13 = UNW_PPC64_F13,
436 UNW_PPC64_VS14 = UNW_PPC64_F14,
437 UNW_PPC64_VS15 = UNW_PPC64_F15,
438 UNW_PPC64_VS16 = UNW_PPC64_F16,
439 UNW_PPC64_VS17 = UNW_PPC64_F17,
440 UNW_PPC64_VS18 = UNW_PPC64_F18,
441 UNW_PPC64_VS19 = UNW_PPC64_F19,
442 UNW_PPC64_VS20 = UNW_PPC64_F20,
443 UNW_PPC64_VS21 = UNW_PPC64_F21,
444 UNW_PPC64_VS22 = UNW_PPC64_F22,
445 UNW_PPC64_VS23 = UNW_PPC64_F23,
446 UNW_PPC64_VS24 = UNW_PPC64_F24,
447 UNW_PPC64_VS25 = UNW_PPC64_F25,
448 UNW_PPC64_VS26 = UNW_PPC64_F26,
449 UNW_PPC64_VS27 = UNW_PPC64_F27,
450 UNW_PPC64_VS28 = UNW_PPC64_F28,
451 UNW_PPC64_VS29 = UNW_PPC64_F29,
452 UNW_PPC64_VS30 = UNW_PPC64_F30,
453 UNW_PPC64_VS31 = UNW_PPC64_F31,
454 UNW_PPC64_VS32 = UNW_PPC64_V0,
455 UNW_PPC64_VS33 = UNW_PPC64_V1,
456 UNW_PPC64_VS34 = UNW_PPC64_V2,
457 UNW_PPC64_VS35 = UNW_PPC64_V3,
458 UNW_PPC64_VS36 = UNW_PPC64_V4,
459 UNW_PPC64_VS37 = UNW_PPC64_V5,
460 UNW_PPC64_VS38 = UNW_PPC64_V6,
461 UNW_PPC64_VS39 = UNW_PPC64_V7,
462 UNW_PPC64_VS40 = UNW_PPC64_V8,
463 UNW_PPC64_VS41 = UNW_PPC64_V9,
464 UNW_PPC64_VS42 = UNW_PPC64_V10,
465 UNW_PPC64_VS43 = UNW_PPC64_V11,
466 UNW_PPC64_VS44 = UNW_PPC64_V12,
467 UNW_PPC64_VS45 = UNW_PPC64_V13,
468 UNW_PPC64_VS46 = UNW_PPC64_V14,
469 UNW_PPC64_VS47 = UNW_PPC64_V15,
470 UNW_PPC64_VS48 = UNW_PPC64_V16,
471 UNW_PPC64_VS49 = UNW_PPC64_V17,
472 UNW_PPC64_VS50 = UNW_PPC64_V18,
473 UNW_PPC64_VS51 = UNW_PPC64_V19,
474 UNW_PPC64_VS52 = UNW_PPC64_V20,
475 UNW_PPC64_VS53 = UNW_PPC64_V21,
476 UNW_PPC64_VS54 = UNW_PPC64_V22,
477 UNW_PPC64_VS55 = UNW_PPC64_V23,
478 UNW_PPC64_VS56 = UNW_PPC64_V24,
479 UNW_PPC64_VS57 = UNW_PPC64_V25,
480 UNW_PPC64_VS58 = UNW_PPC64_V26,
481 UNW_PPC64_VS59 = UNW_PPC64_V27,
482 UNW_PPC64_VS60 = UNW_PPC64_V28,
483 UNW_PPC64_VS61 = UNW_PPC64_V29,
484 UNW_PPC64_VS62 = UNW_PPC64_V30,
485 UNW_PPC64_VS63 = UNW_PPC64_V31
488 // 64-bit ARM64 registers
526 UNW_ARM64_RA_SIGN_STATE = 34,
562 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
563 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
564 // In this scheme, even though the 64-bit floating point registers D0-D31
565 // overlap physically with the 32-bit floating pointer registers S0-S31,
566 // they are given a non-overlapping range of register numbers.
568 // Commented out ranges are not preserved during unwinding.
583 UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP
587 UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP
589 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
622 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
623 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
640 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
641 // 134-143 -- Reserved
642 // 144-150 -- R8_USR-R14_USR
643 // 151-157 -- R8_FIQ-R14_FIQ
644 // 158-159 -- R13_IRQ-R14_IRQ
645 // 160-161 -- R13_ABT-R14_ABT
646 // 162-163 -- R13_UND-R14_UND
647 // 164-165 -- R13_SVC-R14_SVC
648 // 166-191 -- Reserved
653 // 196-199 -- wC4-wC7 (Intel wireless MMX control)
654 // 200-255 -- Reserved
687 // 288-319 -- Reserved for VFP/Neon
688 // 320-8191 -- Reserved
689 // 8192-16383 -- Unspecified vendor co-processor register.
692 // OpenRISC1000 register numbers
835 // RISC-V registers. These match the DWARF register numbers defined by section
836 // 4 of the RISC-V ELF psABI specification, which can be found at:
838 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md