1 //===- ARM.cpp ------------------------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "InputFiles.h"
11 #include "SyntheticSections.h"
14 #include "lld/Common/ErrorHandler.h"
15 #include "llvm/ADT/Bitfields.h"
16 #include "llvm/BinaryFormat/MachO.h"
17 #include "llvm/Support/Endian.h"
20 using namespace llvm::MachO;
21 using namespace llvm::support::endian;
23 using namespace lld::macho;
27 struct ARM : TargetInfo {
28 ARM(uint32_t cpuSubtype);
30 int64_t getEmbeddedAddend(MemoryBufferRef, uint64_t offset,
31 const relocation_info) const override;
32 void relocateOne(uint8_t *loc, const Reloc &, uint64_t va,
33 uint64_t pc) const override;
35 void writeStub(uint8_t *buf, const Symbol &) const override;
36 void writeStubHelperHeader(uint8_t *buf) const override;
37 void writeStubHelperEntry(uint8_t *buf, const Symbol &,
38 uint64_t entryAddr) const override;
40 void relaxGotLoad(uint8_t *loc, uint8_t type) const override;
41 const RelocAttrs &getRelocAttrs(uint8_t type) const override;
42 uint64_t getPageSize() const override { return 4 * 1024; }
47 const RelocAttrs &ARM::getRelocAttrs(uint8_t type) const {
48 static const std::array<RelocAttrs, 10> relocAttrsArray{{
49 #define B(x) RelocAttrBits::x
50 {"VANILLA", /* FIXME populate this */ B(_0)},
51 {"PAIR", /* FIXME populate this */ B(_0)},
52 {"SECTDIFF", /* FIXME populate this */ B(_0)},
53 {"LOCAL_SECTDIFF", /* FIXME populate this */ B(_0)},
54 {"PB_LA_PTR", /* FIXME populate this */ B(_0)},
55 {"BR24", B(PCREL) | B(LOCAL) | B(EXTERN) | B(BRANCH) | B(BYTE4)},
56 {"BR22", B(PCREL) | B(LOCAL) | B(EXTERN) | B(BRANCH) | B(BYTE4)},
57 {"32BIT_BRANCH", /* FIXME populate this */ B(_0)},
58 {"HALF", /* FIXME populate this */ B(_0)},
59 {"HALF_SECTDIFF", /* FIXME populate this */ B(_0)},
62 assert(type < relocAttrsArray.size() && "invalid relocation type");
63 if (type >= relocAttrsArray.size())
64 return invalidRelocAttrs;
65 return relocAttrsArray[type];
68 int64_t ARM::getEmbeddedAddend(MemoryBufferRef mb, uint64_t offset,
69 relocation_info rel) const {
70 // FIXME: implement this
74 template <int N> using BitfieldFlag = Bitfield::Element<bool, N, 1>;
79 // +---------+---------+----------------------------------------------+
80 // | cond | 1 0 1 1 | imm24 |
81 // +---------+---------+----------------------------------------------+
83 // `cond` here varies depending on whether we have bleq, blne, etc.
84 // `imm24` encodes a 26-bit pcrel offset -- last 2 bits are zero as ARM
85 // functions are 4-byte-aligned.
90 // +---------+---------+----------------------------------------------+
91 // | 1 1 1 1 | 1 0 1 H | imm24 |
92 // +---------+---------+----------------------------------------------+
94 // Since Thumb functions are 2-byte-aligned, we need one extra bit to encode
95 // the offset -- that is the H bit.
97 // BLX is always unconditional, so while we can convert directly from BLX to BL,
98 // we need to insert a shim if a BL's target is a Thumb function.
100 // Helper aliases for decoding BL / BLX:
101 using Cond = Bitfield::Element<uint32_t, 28, 4>;
102 using Imm24 = Bitfield::Element<int32_t, 0, 24>;
104 void ARM::relocateOne(uint8_t *loc, const Reloc &r, uint64_t value,
107 case ARM_RELOC_BR24: {
108 uint32_t base = read32le(loc);
109 bool isBlx = Bitfield::get<Cond>(base) == 0xf;
110 const Symbol *sym = r.referent.get<Symbol *>();
111 int32_t offset = value - (pc + 8);
113 if (auto *defined = dyn_cast<Defined>(sym)) {
114 if (!isBlx && defined->thumb) {
115 error("TODO: implement interworking shim");
117 } else if (isBlx && !defined->thumb) {
118 Bitfield::set<Cond>(base, 0xe); // unconditional BL
119 Bitfield::set<BitfieldFlag<24>>(base, true);
123 error("TODO: Implement ARM_RELOC_BR24 for dylib symbols");
128 assert((0x1 & value) == 0);
129 Bitfield::set<Imm24>(base, offset >> 2);
130 Bitfield::set<BitfieldFlag<24>>(base, (offset >> 1) & 1); // H bit
132 assert((0x3 & value) == 0);
133 Bitfield::set<Imm24>(base, offset >> 2);
135 write32le(loc, base);
139 fatal("unhandled relocation type");
143 void ARM::writeStub(uint8_t *buf, const Symbol &sym) const {
144 fatal("TODO: implement this");
147 void ARM::writeStubHelperHeader(uint8_t *buf) const {
148 fatal("TODO: implement this");
151 void ARM::writeStubHelperEntry(uint8_t *buf, const Symbol &sym,
152 uint64_t entryAddr) const {
153 fatal("TODO: implement this");
156 void ARM::relaxGotLoad(uint8_t *loc, uint8_t type) const {
157 fatal("TODO: implement this");
160 ARM::ARM(uint32_t cpuSubtype) : TargetInfo(ILP32()) {
161 cpuType = CPU_TYPE_ARM;
162 this->cpuSubtype = cpuSubtype;
164 stubSize = 0 /* FIXME */;
165 stubHelperHeaderSize = 0 /* FIXME */;
166 stubHelperEntrySize = 0 /* FIXME */;
169 TargetInfo *macho::createARMTargetInfo(uint32_t cpuSubtype) {
170 static ARM t(cpuSubtype);