1 //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "RegisterContextDarwin_arm.h"
10 #include "RegisterContextDarwinConstants.h"
12 #include "lldb/Utility/DataBufferHeap.h"
13 #include "lldb/Utility/DataExtractor.h"
14 #include "lldb/Utility/Endian.h"
15 #include "lldb/Utility/Log.h"
16 #include "lldb/Utility/RegisterValue.h"
17 #include "lldb/Utility/Scalar.h"
18 #include "llvm/Support/Compiler.h"
20 #include "Plugins/Process/Utility/InstructionUtils.h"
24 #include "Utility/ARM_DWARF_Registers.h"
25 #include "Utility/ARM_ehframe_Registers.h"
27 #include "llvm/ADT/STLExtras.h"
30 using namespace lldb_private;
163 #define GPR_OFFSET(idx) ((idx)*4)
164 #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR))
165 #define EXC_OFFSET(idx) \
166 ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \
167 sizeof(RegisterContextDarwin_arm::FPU))
168 #define DBG_OFFSET(reg) \
169 ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \
170 sizeof(RegisterContextDarwin_arm::GPR) + \
171 sizeof(RegisterContextDarwin_arm::FPU) + \
172 sizeof(RegisterContextDarwin_arm::EXC)))
174 #define DEFINE_DBG(reg, i) \
175 #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \
176 DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \
177 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
178 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
179 LLDB_INVALID_REGNUM }, \
180 nullptr, nullptr, nullptr, 0
181 #define REG_CONTEXT_SIZE \
182 (sizeof(RegisterContextDarwin_arm::GPR) + \
183 sizeof(RegisterContextDarwin_arm::FPU) + \
184 sizeof(RegisterContextDarwin_arm::EXC))
186 static RegisterInfo g_register_infos[] = {
187 // General purpose registers
188 // NAME ALT SZ OFFSET ENCODING FORMAT
189 // EH_FRAME DWARF GENERIC
190 // PROCESS PLUGIN LLDB NATIVE
191 // ====== ======= == ============= ============= ============
192 // =============== =============== =========================
193 // ===================== =============
200 {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0},
211 {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1},
222 {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2},
233 {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3},
244 {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4},
255 {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5},
266 {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6},
277 {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM,
289 {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8},
300 {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9},
311 {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
323 {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
335 {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
347 {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM,
359 {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM,
371 {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM,
383 {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM,
396 {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
408 {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
420 {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
432 {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
444 {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
456 {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
468 {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
480 {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
492 {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
504 {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
516 {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
528 {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
540 {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
552 {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
564 {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
576 {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
588 {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
600 {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
612 {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
624 {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
636 {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
648 {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
660 {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
672 {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
684 {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
696 {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
708 {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
720 {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
732 {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
744 {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
756 {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
768 {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
780 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
781 LLDB_INVALID_REGNUM, fpu_fpscr},
793 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
794 LLDB_INVALID_REGNUM, exc_exception},
805 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
806 LLDB_INVALID_REGNUM, exc_fsr},
817 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
818 LLDB_INVALID_REGNUM, exc_far},
824 {DEFINE_DBG(bvr, 0)},
825 {DEFINE_DBG(bvr, 1)},
826 {DEFINE_DBG(bvr, 2)},
827 {DEFINE_DBG(bvr, 3)},
828 {DEFINE_DBG(bvr, 4)},
829 {DEFINE_DBG(bvr, 5)},
830 {DEFINE_DBG(bvr, 6)},
831 {DEFINE_DBG(bvr, 7)},
832 {DEFINE_DBG(bvr, 8)},
833 {DEFINE_DBG(bvr, 9)},
834 {DEFINE_DBG(bvr, 10)},
835 {DEFINE_DBG(bvr, 11)},
836 {DEFINE_DBG(bvr, 12)},
837 {DEFINE_DBG(bvr, 13)},
838 {DEFINE_DBG(bvr, 14)},
839 {DEFINE_DBG(bvr, 15)},
841 {DEFINE_DBG(bcr, 0)},
842 {DEFINE_DBG(bcr, 1)},
843 {DEFINE_DBG(bcr, 2)},
844 {DEFINE_DBG(bcr, 3)},
845 {DEFINE_DBG(bcr, 4)},
846 {DEFINE_DBG(bcr, 5)},
847 {DEFINE_DBG(bcr, 6)},
848 {DEFINE_DBG(bcr, 7)},
849 {DEFINE_DBG(bcr, 8)},
850 {DEFINE_DBG(bcr, 9)},
851 {DEFINE_DBG(bcr, 10)},
852 {DEFINE_DBG(bcr, 11)},
853 {DEFINE_DBG(bcr, 12)},
854 {DEFINE_DBG(bcr, 13)},
855 {DEFINE_DBG(bcr, 14)},
856 {DEFINE_DBG(bcr, 15)},
858 {DEFINE_DBG(wvr, 0)},
859 {DEFINE_DBG(wvr, 1)},
860 {DEFINE_DBG(wvr, 2)},
861 {DEFINE_DBG(wvr, 3)},
862 {DEFINE_DBG(wvr, 4)},
863 {DEFINE_DBG(wvr, 5)},
864 {DEFINE_DBG(wvr, 6)},
865 {DEFINE_DBG(wvr, 7)},
866 {DEFINE_DBG(wvr, 8)},
867 {DEFINE_DBG(wvr, 9)},
868 {DEFINE_DBG(wvr, 10)},
869 {DEFINE_DBG(wvr, 11)},
870 {DEFINE_DBG(wvr, 12)},
871 {DEFINE_DBG(wvr, 13)},
872 {DEFINE_DBG(wvr, 14)},
873 {DEFINE_DBG(wvr, 15)},
875 {DEFINE_DBG(wcr, 0)},
876 {DEFINE_DBG(wcr, 1)},
877 {DEFINE_DBG(wcr, 2)},
878 {DEFINE_DBG(wcr, 3)},
879 {DEFINE_DBG(wcr, 4)},
880 {DEFINE_DBG(wcr, 5)},
881 {DEFINE_DBG(wcr, 6)},
882 {DEFINE_DBG(wcr, 7)},
883 {DEFINE_DBG(wcr, 8)},
884 {DEFINE_DBG(wcr, 9)},
885 {DEFINE_DBG(wcr, 10)},
886 {DEFINE_DBG(wcr, 11)},
887 {DEFINE_DBG(wcr, 12)},
888 {DEFINE_DBG(wcr, 13)},
889 {DEFINE_DBG(wcr, 14)},
890 {DEFINE_DBG(wcr, 15)}};
892 // General purpose registers
893 static uint32_t g_gpr_regnums[] = {
894 gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8,
895 gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr};
897 // Floating point registers
898 static uint32_t g_fpu_regnums[] = {
899 fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6,
900 fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13,
901 fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20,
902 fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27,
903 fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr,
906 // Exception registers
908 static uint32_t g_exc_regnums[] = {
909 exc_exception, exc_fsr, exc_far,
912 static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos);
914 RegisterContextDarwin_arm::RegisterContextDarwin_arm(
915 Thread &thread, uint32_t concrete_frame_idx)
916 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
918 for (i = 0; i < kNumErrors; i++) {
925 RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {}
927 void RegisterContextDarwin_arm::InvalidateAllRegisters() {
928 InvalidateAllRegisterStates();
931 size_t RegisterContextDarwin_arm::GetRegisterCount() {
932 assert(k_num_register_infos == k_num_registers);
933 return k_num_registers;
937 RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) {
938 assert(k_num_register_infos == k_num_registers);
939 if (reg < k_num_registers)
940 return &g_register_infos[reg];
944 size_t RegisterContextDarwin_arm::GetRegisterInfosCount() {
945 return k_num_register_infos;
948 const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() {
949 return g_register_infos;
952 // Number of registers in each register set
953 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
954 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
955 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
957 // Register set definitions. The first definitions at register set index of
958 // zero is for all registers, followed by other registers sets. The register
959 // information for the all register set need not be filled in.
960 static const RegisterSet g_reg_sets[] = {
962 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
964 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
965 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
967 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
969 size_t RegisterContextDarwin_arm::GetRegisterSetCount() {
970 return k_num_regsets;
973 const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) {
974 if (reg_set < k_num_regsets)
975 return &g_reg_sets[reg_set];
979 // Register information definitions for 32 bit i386.
980 int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) {
983 else if (reg < exc_exception)
985 else if (reg < k_num_registers)
990 int RegisterContextDarwin_arm::ReadGPR(bool force) {
992 if (force || !RegisterSetIsCached(set)) {
993 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
995 return GetError(GPRRegSet, Read);
998 int RegisterContextDarwin_arm::ReadFPU(bool force) {
1000 if (force || !RegisterSetIsCached(set)) {
1001 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
1003 return GetError(FPURegSet, Read);
1006 int RegisterContextDarwin_arm::ReadEXC(bool force) {
1007 int set = EXCRegSet;
1008 if (force || !RegisterSetIsCached(set)) {
1009 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
1011 return GetError(EXCRegSet, Read);
1014 int RegisterContextDarwin_arm::ReadDBG(bool force) {
1015 int set = DBGRegSet;
1016 if (force || !RegisterSetIsCached(set)) {
1017 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
1019 return GetError(DBGRegSet, Read);
1022 int RegisterContextDarwin_arm::WriteGPR() {
1023 int set = GPRRegSet;
1024 if (!RegisterSetIsCached(set)) {
1025 SetError(set, Write, -1);
1026 return KERN_INVALID_ARGUMENT;
1028 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
1029 SetError(set, Read, -1);
1030 return GetError(GPRRegSet, Write);
1033 int RegisterContextDarwin_arm::WriteFPU() {
1034 int set = FPURegSet;
1035 if (!RegisterSetIsCached(set)) {
1036 SetError(set, Write, -1);
1037 return KERN_INVALID_ARGUMENT;
1039 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
1040 SetError(set, Read, -1);
1041 return GetError(FPURegSet, Write);
1044 int RegisterContextDarwin_arm::WriteEXC() {
1045 int set = EXCRegSet;
1046 if (!RegisterSetIsCached(set)) {
1047 SetError(set, Write, -1);
1048 return KERN_INVALID_ARGUMENT;
1050 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
1051 SetError(set, Read, -1);
1052 return GetError(EXCRegSet, Write);
1055 int RegisterContextDarwin_arm::WriteDBG() {
1056 int set = DBGRegSet;
1057 if (!RegisterSetIsCached(set)) {
1058 SetError(set, Write, -1);
1059 return KERN_INVALID_ARGUMENT;
1061 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
1062 SetError(set, Read, -1);
1063 return GetError(DBGRegSet, Write);
1066 int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) {
1069 return ReadGPR(force);
1071 return ReadGPR(force);
1073 return ReadFPU(force);
1075 return ReadEXC(force);
1077 return ReadDBG(force);
1081 return KERN_INVALID_ARGUMENT;
1084 int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) {
1085 // Make sure we have a valid context to set.
1086 if (RegisterSetIsCached(set)) {
1102 return KERN_INVALID_ARGUMENT;
1105 void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) {
1107 for (uint32_t i = 0; i < 16; i++)
1109 "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { "
1110 "0x%8.8x, 0x%8.8x }",
1111 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
1115 bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info,
1116 RegisterValue &value) {
1117 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
1118 int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg);
1123 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
1143 value.SetUInt32(gpr.r[reg - gpr_r0]);
1146 value.SetUInt32(gpr.cpsr);
1180 value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat);
1184 value.SetUInt32(fpu.fpscr);
1188 value.SetUInt32(exc.exception);
1191 value.SetUInt32(exc.fsr);
1194 value.SetUInt32(exc.far);
1198 value.SetValueToInvalid();
1204 bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info,
1205 const RegisterValue &value) {
1206 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
1207 int set = GetSetForNativeRegNum(reg);
1212 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
1233 gpr.r[reg - gpr_r0] = value.GetAsUInt32();
1268 fpu.floats.s[reg] = value.GetAsUInt32();
1272 fpu.fpscr = value.GetAsUInt32();
1276 exc.exception = value.GetAsUInt32();
1279 exc.fsr = value.GetAsUInt32();
1282 exc.far = value.GetAsUInt32();
1288 return WriteRegisterSet(set) == KERN_SUCCESS;
1291 bool RegisterContextDarwin_arm::ReadAllRegisterValues(
1292 lldb::DataBufferSP &data_sp) {
1293 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
1294 if (data_sp && ReadGPR(false) == KERN_SUCCESS &&
1295 ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) {
1296 uint8_t *dst = data_sp->GetBytes();
1297 ::memcpy(dst, &gpr, sizeof(gpr));
1300 ::memcpy(dst, &fpu, sizeof(fpu));
1303 ::memcpy(dst, &exc, sizeof(exc));
1309 bool RegisterContextDarwin_arm::WriteAllRegisterValues(
1310 const lldb::DataBufferSP &data_sp) {
1311 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
1312 const uint8_t *src = data_sp->GetBytes();
1313 ::memcpy(&gpr, src, sizeof(gpr));
1316 ::memcpy(&fpu, src, sizeof(fpu));
1319 ::memcpy(&exc, src, sizeof(exc));
1320 uint32_t success_count = 0;
1321 if (WriteGPR() == KERN_SUCCESS)
1323 if (WriteFPU() == KERN_SUCCESS)
1325 if (WriteEXC() == KERN_SUCCESS)
1327 return success_count == 3;
1332 uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber(
1333 lldb::RegisterKind kind, uint32_t reg) {
1334 if (kind == eRegisterKindGeneric) {
1336 case LLDB_REGNUM_GENERIC_PC:
1338 case LLDB_REGNUM_GENERIC_SP:
1340 case LLDB_REGNUM_GENERIC_FP:
1342 case LLDB_REGNUM_GENERIC_RA:
1344 case LLDB_REGNUM_GENERIC_FLAGS:
1349 } else if (kind == eRegisterKindDWARF) {
1454 } else if (kind == eRegisterKindEHFrame) {
1491 } else if (kind == eRegisterKindLLDB) {
1494 return LLDB_INVALID_REGNUM;
1497 uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() {
1498 #if defined(__APPLE__) && defined(__arm__)
1499 // Set the init value to something that will let us know that we need to
1500 // autodetect how many breakpoints are supported dynamically...
1501 static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX;
1502 if (g_num_supported_hw_breakpoints == UINT32_MAX) {
1503 // Set this to zero in case we can't tell if there are any HW breakpoints
1504 g_num_supported_hw_breakpoints = 0;
1506 uint32_t register_DBGDIDR;
1508 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
1509 g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24);
1510 // Zero is reserved for the BRP count, so don't increment it if it is zero
1511 if (g_num_supported_hw_breakpoints > 0)
1512 g_num_supported_hw_breakpoints++;
1514 return g_num_supported_hw_breakpoints;
1516 // TODO: figure out remote case here!
1521 uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr,
1523 // Make sure our address isn't bogus
1525 return LLDB_INVALID_INDEX32;
1527 int kret = ReadDBG(false);
1529 if (kret == KERN_SUCCESS) {
1530 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
1532 for (i = 0; i < num_hw_breakpoints; ++i) {
1533 if ((dbg.bcr[i] & BCR_ENABLE) == 0)
1534 break; // We found an available hw breakpoint slot (in i)
1537 // See if we found an available hw breakpoint slot above
1538 if (i < num_hw_breakpoints) {
1539 // Make sure bits 1:0 are clear in our address
1540 dbg.bvr[i] = addr & ~((lldb::addr_t)3);
1542 if (size == 2 || addr & 2) {
1543 uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
1545 // We have a thumb breakpoint
1546 // We have an ARM breakpoint
1547 dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
1548 byte_addr_select | // Set the correct byte address select
1549 // so we only trigger on the correct
1551 S_USER | // Which modes should this breakpoint stop in?
1552 BCR_ENABLE; // Enable this hardware breakpoint
1553 // if (log) log->Printf
1554 // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(
1555 // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x /
1556 // 0x%8.8x (Thumb)",
1563 } else if (size == 4) {
1564 // We have an ARM breakpoint
1566 BCR_M_IMVA_MATCH | // Stop on address mismatch
1567 BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
1568 S_USER | // Which modes should this breakpoint stop in?
1569 BCR_ENABLE; // Enable this hardware breakpoint
1570 // if (log) log->Printf
1571 // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(
1572 // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x /
1583 // if (log) log->Printf
1584 // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint()
1585 // WriteDBG() => 0x%8.8x.", kret);
1587 if (kret == KERN_SUCCESS)
1592 // if (log) log->Printf
1593 // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr =
1594 // %8.8p, size = %u) => all hardware breakpoint resources are
1595 // being used.", addr, size);
1599 return LLDB_INVALID_INDEX32;
1602 bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) {
1603 int kret = ReadDBG(false);
1605 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
1606 if (kret == KERN_SUCCESS) {
1607 if (hw_index < num_hw_points) {
1608 dbg.bcr[hw_index] = 0;
1609 // if (log) log->Printf
1610 // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) -
1611 // BVR%u = 0x%8.8x BCR%u = 0x%8.8x",
1614 // dbg.bvr[hw_index],
1616 // dbg.bcr[hw_index]);
1620 if (kret == KERN_SUCCESS)
1627 uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() {
1628 #if defined(__APPLE__) && defined(__arm__)
1629 // Set the init value to something that will let us know that we need to
1630 // autodetect how many watchpoints are supported dynamically...
1631 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
1632 if (g_num_supported_hw_watchpoints == UINT32_MAX) {
1633 // Set this to zero in case we can't tell if there are any HW breakpoints
1634 g_num_supported_hw_watchpoints = 0;
1636 uint32_t register_DBGDIDR;
1637 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
1638 g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1;
1640 return g_num_supported_hw_watchpoints;
1642 // TODO: figure out remote case here!
1647 uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr,
1651 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
1653 // Can't watch zero bytes
1655 return LLDB_INVALID_INDEX32;
1657 // We must watch for either read or write
1658 if (!read && !write)
1659 return LLDB_INVALID_INDEX32;
1661 // Can't watch more than 4 bytes per WVR/WCR pair
1663 return LLDB_INVALID_INDEX32;
1665 // We can only watch up to four bytes that follow a 4 byte aligned address
1666 // per watchpoint register pair. Since we have at most so we can only watch
1667 // until the next 4 byte boundary and we need to make sure we can properly
1669 uint32_t addr_word_offset = addr % 4;
1670 // if (log) log->Printf
1671 // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() -
1672 // addr_word_offset = 0x%8.8x", addr_word_offset);
1674 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
1675 // if (log) log->Printf
1676 // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask =
1677 // 0x%8.8x", byte_mask);
1678 if (byte_mask > 0xfu)
1679 return LLDB_INVALID_INDEX32;
1681 // Read the debug state
1682 int kret = ReadDBG(false);
1684 if (kret == KERN_SUCCESS) {
1685 // Check to make sure we have the needed hardware support
1688 for (i = 0; i < num_hw_watchpoints; ++i) {
1689 if ((dbg.wcr[i] & WCR_ENABLE) == 0)
1690 break; // We found an available hw breakpoint slot (in i)
1693 // See if we found an available hw breakpoint slot above
1694 if (i < num_hw_watchpoints) {
1695 // Make the byte_mask into a valid Byte Address Select mask
1696 uint32_t byte_address_select = byte_mask << 5;
1697 // Make sure bits 1:0 are clear in our address
1698 dbg.wvr[i] = addr & ~((lldb::addr_t)3);
1699 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA
1700 // that we will watch
1701 S_USER | // Stop only in user mode
1702 (read ? WCR_LOAD : 0) | // Stop on read access?
1703 (write ? WCR_STORE : 0) | // Stop on write access?
1704 WCR_ENABLE; // Enable this watchpoint;
1707 // if (log) log->Printf
1708 // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint()
1709 // WriteDBG() => 0x%8.8x.", kret);
1711 if (kret == KERN_SUCCESS)
1714 // if (log) log->Printf
1715 // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All
1716 // hardware resources (%u) are in use.", num_hw_watchpoints);
1719 return LLDB_INVALID_INDEX32;
1722 bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) {
1723 int kret = ReadDBG(false);
1725 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1726 if (kret == KERN_SUCCESS) {
1727 if (hw_index < num_hw_points) {
1728 dbg.wcr[hw_index] = 0;
1729 // if (log) log->Printf
1730 // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) -
1731 // WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1734 // dbg.wvr[hw_index],
1736 // dbg.wcr[hw_index]);
1740 if (kret == KERN_SUCCESS)