contrib/llvm-project/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp

   1 //===-- RegisterContextPOSIX_arm.cpp --------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include <cstring>
  10 #include <errno.h>
  11 #include <stdint.h>
  12
  13 #include "lldb/Target/Process.h"
  14 #include "lldb/Target/Target.h"
  15 #include "lldb/Target/Thread.h"
  16 #include "lldb/Utility/DataBufferHeap.h"
  17 #include "lldb/Utility/DataExtractor.h"
  18 #include "lldb/Utility/Endian.h"
  19 #include "lldb/Utility/RegisterValue.h"
  20 #include "lldb/Utility/Scalar.h"
  21 #include "llvm/Support/Compiler.h"
  22
  23 #include "RegisterContextPOSIX_arm.h"
  24
  25 using namespace lldb;
  26 using namespace lldb_private;
  27
  28 // arm general purpose registers.
  29 const uint32_t g_gpr_regnums_arm[] = {
  30     gpr_r0_arm,         gpr_r1_arm,   gpr_r2_arm,  gpr_r3_arm, gpr_r4_arm,
  31     gpr_r5_arm,         gpr_r6_arm,   gpr_r7_arm,  gpr_r8_arm, gpr_r9_arm,
  32     gpr_r10_arm,        gpr_r11_arm,  gpr_r12_arm, gpr_sp_arm, gpr_lr_arm,
  33     gpr_pc_arm,         gpr_cpsr_arm,
  34     LLDB_INVALID_REGNUM // register sets need to end with this flag
  35
  36 };
  37 static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
  38                   k_num_gpr_registers_arm,
  39               "g_gpr_regnums_arm has wrong number of register infos");
  40
  41 // arm floating point registers.
  42 static const uint32_t g_fpu_regnums_arm[] = {
  43     fpu_s0_arm,         fpu_s1_arm,  fpu_s2_arm,    fpu_s3_arm,  fpu_s4_arm,
  44     fpu_s5_arm,         fpu_s6_arm,  fpu_s7_arm,    fpu_s8_arm,  fpu_s9_arm,
  45     fpu_s10_arm,        fpu_s11_arm, fpu_s12_arm,   fpu_s13_arm, fpu_s14_arm,
  46     fpu_s15_arm,        fpu_s16_arm, fpu_s17_arm,   fpu_s18_arm, fpu_s19_arm,
  47     fpu_s20_arm,        fpu_s21_arm, fpu_s22_arm,   fpu_s23_arm, fpu_s24_arm,
  48     fpu_s25_arm,        fpu_s26_arm, fpu_s27_arm,   fpu_s28_arm, fpu_s29_arm,
  49     fpu_s30_arm,        fpu_s31_arm, fpu_fpscr_arm, fpu_d0_arm,  fpu_d1_arm,
  50     fpu_d2_arm,         fpu_d3_arm,  fpu_d4_arm,    fpu_d5_arm,  fpu_d6_arm,
  51     fpu_d7_arm,         fpu_d8_arm,  fpu_d9_arm,    fpu_d10_arm, fpu_d11_arm,
  52     fpu_d12_arm,        fpu_d13_arm, fpu_d14_arm,   fpu_d15_arm, fpu_d16_arm,
  53     fpu_d17_arm,        fpu_d18_arm, fpu_d19_arm,   fpu_d20_arm, fpu_d21_arm,
  54     fpu_d22_arm,        fpu_d23_arm, fpu_d24_arm,   fpu_d25_arm, fpu_d26_arm,
  55     fpu_d27_arm,        fpu_d28_arm, fpu_d29_arm,   fpu_d30_arm, fpu_d31_arm,
  56     fpu_q0_arm,         fpu_q1_arm,  fpu_q2_arm,    fpu_q3_arm,  fpu_q4_arm,
  57     fpu_q5_arm,         fpu_q6_arm,  fpu_q7_arm,    fpu_q8_arm,  fpu_q9_arm,
  58     fpu_q10_arm,        fpu_q11_arm, fpu_q12_arm,   fpu_q13_arm, fpu_q14_arm,
  59     fpu_q15_arm,
  60     LLDB_INVALID_REGNUM // register sets need to end with this flag
  61
  62 };
  63 static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
  64                   k_num_fpr_registers_arm,
  65               "g_fpu_regnums_arm has wrong number of register infos");
  66
  67 // Number of register sets provided by this context.
  68 enum { k_num_register_sets = 2 };
  69
  70 // Register sets for arm.
  71 static const lldb_private::RegisterSet g_reg_sets_arm[k_num_register_sets] = {
  72     {"General Purpose Registers", "gpr", k_num_gpr_registers_arm,
  73      g_gpr_regnums_arm},
  74     {"Floating Point Registers", "fpu", k_num_fpr_registers_arm,
  75      g_fpu_regnums_arm}};
  76
  77 bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) {
  78   return reg <= m_reg_info.last_gpr; // GPR's come first.
  79 }
  80
  81 bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) {
  82   return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
  83 }
  84
  85 RegisterContextPOSIX_arm::RegisterContextPOSIX_arm(
  86     lldb_private::Thread &thread, uint32_t concrete_frame_idx,
  87     lldb_private::RegisterInfoInterface *register_info)
  88     : lldb_private::RegisterContext(thread, concrete_frame_idx) {
  89   m_register_info_up.reset(register_info);
  90
  91   switch (register_info->m_target_arch.GetMachine()) {
  92   case llvm::Triple::arm:
  93     m_reg_info.num_registers = k_num_registers_arm;
  94     m_reg_info.num_gpr_registers = k_num_gpr_registers_arm;
  95     m_reg_info.num_fpr_registers = k_num_fpr_registers_arm;
  96     m_reg_info.last_gpr = k_last_gpr_arm;
  97     m_reg_info.first_fpr = k_first_fpr_arm;
  98     m_reg_info.last_fpr = k_last_fpr_arm;
  99     m_reg_info.first_fpr_v = fpu_s0_arm;
 100     m_reg_info.last_fpr_v = fpu_s31_arm;
 101     m_reg_info.gpr_flags = gpr_cpsr_arm;
 102     break;
 103   default:
 104     assert(false && "Unhandled target architecture.");
 105     break;
 106   }
 107
 108   ::memset(&m_fpr, 0, sizeof m_fpr);
 109 }
 110
 111 RegisterContextPOSIX_arm::~RegisterContextPOSIX_arm() {}
 112
 113 void RegisterContextPOSIX_arm::Invalidate() {}
 114
 115 void RegisterContextPOSIX_arm::InvalidateAllRegisters() {}
 116
 117 unsigned RegisterContextPOSIX_arm::GetRegisterOffset(unsigned reg) {
 118   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 119   return GetRegisterInfo()[reg].byte_offset;
 120 }
 121
 122 unsigned RegisterContextPOSIX_arm::GetRegisterSize(unsigned reg) {
 123   assert(reg < m_reg_info.num_registers && "Invalid register number.");
 124   return GetRegisterInfo()[reg].byte_size;
 125 }
 126
 127 size_t RegisterContextPOSIX_arm::GetRegisterCount() {
 128   size_t num_registers =
 129       m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers;
 130   return num_registers;
 131 }
 132
 133 size_t RegisterContextPOSIX_arm::GetGPRSize() {
 134   return m_register_info_up->GetGPRSize();
 135 }
 136
 137 const lldb_private::RegisterInfo *RegisterContextPOSIX_arm::GetRegisterInfo() {
 138   // Commonly, this method is overridden and g_register_infos is copied and
 139   // specialized. So, use GetRegisterInfo() rather than g_register_infos in
 140   // this scope.
 141   return m_register_info_up->GetRegisterInfo();
 142 }
 143
 144 const lldb_private::RegisterInfo *
 145 RegisterContextPOSIX_arm::GetRegisterInfoAtIndex(size_t reg) {
 146   if (reg < m_reg_info.num_registers)
 147     return &GetRegisterInfo()[reg];
 148   else
 149     return nullptr;
 150 }
 151
 152 size_t RegisterContextPOSIX_arm::GetRegisterSetCount() {
 153   size_t sets = 0;
 154   for (size_t set = 0; set < k_num_register_sets; ++set) {
 155     if (IsRegisterSetAvailable(set))
 156       ++sets;
 157   }
 158
 159   return sets;
 160 }
 161
 162 const lldb_private::RegisterSet *
 163 RegisterContextPOSIX_arm::GetRegisterSet(size_t set) {
 164   if (IsRegisterSetAvailable(set)) {
 165     switch (m_register_info_up->m_target_arch.GetMachine()) {
 166     case llvm::Triple::arm:
 167       return &g_reg_sets_arm[set];
 168     default:
 169       assert(false && "Unhandled target architecture.");
 170       return nullptr;
 171     }
 172   }
 173   return nullptr;
 174 }
 175
 176 const char *RegisterContextPOSIX_arm::GetRegisterName(unsigned reg) {
 177   assert(reg < m_reg_info.num_registers && "Invalid register offset.");
 178   return GetRegisterInfo()[reg].name;
 179 }
 180
 181 lldb::ByteOrder RegisterContextPOSIX_arm::GetByteOrder() {
 182   // Get the target process whose privileged thread was used for the register
 183   // read.
 184   lldb::ByteOrder byte_order = lldb::eByteOrderInvalid;
 185   lldb_private::Process *process = CalculateProcess().get();
 186
 187   if (process)
 188     byte_order = process->GetByteOrder();
 189   return byte_order;
 190 }
 191
 192 bool RegisterContextPOSIX_arm::IsRegisterSetAvailable(size_t set_index) {
 193   return set_index < k_num_register_sets;
 194 }
 195
 196 // Used when parsing DWARF and EH frame information and any other object file
 197 // sections that contain register numbers in them.
 198 uint32_t RegisterContextPOSIX_arm::ConvertRegisterKindToRegisterNumber(
 199     lldb::RegisterKind kind, uint32_t num) {
 200   const uint32_t num_regs = GetRegisterCount();
 201
 202   assert(kind < lldb::kNumRegisterKinds);
 203   for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) {
 204     const lldb_private::RegisterInfo *reg_info =
 205         GetRegisterInfoAtIndex(reg_idx);
 206
 207     if (reg_info->kinds[kind] == num)
 208       return reg_idx;
 209   }
 210
 211   return LLDB_INVALID_REGNUM;
 212 }