1 //===-- RegisterInfoPOSIX_arm64.cpp ----------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===---------------------------------------------------------------------===//
13 #include "lldb/lldb-defines.h"
14 #include "llvm/Support/Compiler.h"
16 #include "RegisterInfoPOSIX_arm64.h"
18 // Based on RegisterContextDarwin_arm64.cpp
19 #define GPR_OFFSET(idx) ((idx)*8)
20 #define GPR_OFFSET_NAME(reg) \
21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
24 #define FPU_OFFSET_NAME(reg) \
25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
26 sizeof(RegisterInfoPOSIX_arm64::GPR))
28 #define EXC_OFFSET_NAME(reg) \
29 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
30 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
31 sizeof(RegisterInfoPOSIX_arm64::FPU))
32 #define DBG_OFFSET_NAME(reg) \
33 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
34 sizeof(RegisterInfoPOSIX_arm64::GPR) + \
35 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
36 sizeof(RegisterInfoPOSIX_arm64::EXC))
38 #define DEFINE_DBG(reg, i) \
40 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
41 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
42 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
43 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
46 #define REG_CONTEXT_SIZE \
47 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
48 sizeof(RegisterInfoPOSIX_arm64::FPU) + \
49 sizeof(RegisterInfoPOSIX_arm64::EXC))
51 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
52 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
53 #include "RegisterInfos_arm64.h"
54 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
56 static const lldb_private::RegisterInfo *
57 GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
58 switch (target_arch.GetMachine()) {
59 case llvm::Triple::aarch64:
60 case llvm::Triple::aarch64_32:
61 return g_register_infos_arm64_le;
63 assert(false && "Unhandled target architecture.");
69 GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
70 switch (target_arch.GetMachine()) {
71 case llvm::Triple::aarch64:
72 case llvm::Triple::aarch64_32:
73 return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
74 sizeof(g_register_infos_arm64_le[0]));
76 assert(false && "Unhandled target architecture.");
81 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
82 const lldb_private::ArchSpec &target_arch)
83 : lldb_private::RegisterInfoInterface(target_arch),
84 m_register_info_p(GetRegisterInfoPtr(target_arch)),
85 m_register_info_count(GetRegisterInfoCount(target_arch)) {}
87 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const {
88 return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
91 const lldb_private::RegisterInfo *
92 RegisterInfoPOSIX_arm64::GetRegisterInfo() const {
93 return m_register_info_p;
96 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const {
97 return m_register_info_count;