1 //===-- RegisterInfos_arm64.h -----------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
13 #include "lldb/lldb-defines.h"
14 #include "lldb/lldb-enumerations.h"
15 #include "lldb/lldb-private.h"
17 #include "Utility/ARM64_DWARF_Registers.h"
18 #include "Utility/ARM64_ehframe_Registers.h"
21 #error GPR_OFFSET must be defined before including this header file
24 #ifndef GPR_OFFSET_NAME
25 #error GPR_OFFSET_NAME must be defined before including this header file
29 #error FPU_OFFSET must be defined before including this header file
32 #ifndef FPU_OFFSET_NAME
33 #error FPU_OFFSET_NAME must be defined before including this header file
36 #ifndef EXC_OFFSET_NAME
37 #error EXC_OFFSET_NAME must be defined before including this header file
40 #ifndef DBG_OFFSET_NAME
41 #error DBG_OFFSET_NAME must be defined before including this header file
45 #error DEFINE_DBG must be defined before including this header file
48 // Offsets for a little-endian layout of the register context
49 #define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0
50 #define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0
51 #define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0
300 static uint32_t g_contained_x0[] = {gpr_x0, LLDB_INVALID_REGNUM};
301 static uint32_t g_contained_x1[] = {gpr_x1, LLDB_INVALID_REGNUM};
302 static uint32_t g_contained_x2[] = {gpr_x2, LLDB_INVALID_REGNUM};
303 static uint32_t g_contained_x3[] = {gpr_x3, LLDB_INVALID_REGNUM};
304 static uint32_t g_contained_x4[] = {gpr_x4, LLDB_INVALID_REGNUM};
305 static uint32_t g_contained_x5[] = {gpr_x5, LLDB_INVALID_REGNUM};
306 static uint32_t g_contained_x6[] = {gpr_x6, LLDB_INVALID_REGNUM};
307 static uint32_t g_contained_x7[] = {gpr_x7, LLDB_INVALID_REGNUM};
308 static uint32_t g_contained_x8[] = {gpr_x8, LLDB_INVALID_REGNUM};
309 static uint32_t g_contained_x9[] = {gpr_x9, LLDB_INVALID_REGNUM};
310 static uint32_t g_contained_x10[] = {gpr_x10, LLDB_INVALID_REGNUM};
311 static uint32_t g_contained_x11[] = {gpr_x11, LLDB_INVALID_REGNUM};
312 static uint32_t g_contained_x12[] = {gpr_x12, LLDB_INVALID_REGNUM};
313 static uint32_t g_contained_x13[] = {gpr_x13, LLDB_INVALID_REGNUM};
314 static uint32_t g_contained_x14[] = {gpr_x14, LLDB_INVALID_REGNUM};
315 static uint32_t g_contained_x15[] = {gpr_x15, LLDB_INVALID_REGNUM};
316 static uint32_t g_contained_x16[] = {gpr_x16, LLDB_INVALID_REGNUM};
317 static uint32_t g_contained_x17[] = {gpr_x17, LLDB_INVALID_REGNUM};
318 static uint32_t g_contained_x18[] = {gpr_x18, LLDB_INVALID_REGNUM};
319 static uint32_t g_contained_x19[] = {gpr_x19, LLDB_INVALID_REGNUM};
320 static uint32_t g_contained_x20[] = {gpr_x20, LLDB_INVALID_REGNUM};
321 static uint32_t g_contained_x21[] = {gpr_x21, LLDB_INVALID_REGNUM};
322 static uint32_t g_contained_x22[] = {gpr_x22, LLDB_INVALID_REGNUM};
323 static uint32_t g_contained_x23[] = {gpr_x23, LLDB_INVALID_REGNUM};
324 static uint32_t g_contained_x24[] = {gpr_x24, LLDB_INVALID_REGNUM};
325 static uint32_t g_contained_x25[] = {gpr_x25, LLDB_INVALID_REGNUM};
326 static uint32_t g_contained_x26[] = {gpr_x26, LLDB_INVALID_REGNUM};
327 static uint32_t g_contained_x27[] = {gpr_x27, LLDB_INVALID_REGNUM};
328 static uint32_t g_contained_x28[] = {gpr_x28, LLDB_INVALID_REGNUM};
330 static uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM};
331 static uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM};
332 static uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM};
333 static uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM};
334 static uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM};
335 static uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM};
336 static uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM};
337 static uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM};
338 static uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM};
339 static uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM};
340 static uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM};
341 static uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM};
342 static uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM};
343 static uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM};
344 static uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM};
345 static uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM};
346 static uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM};
347 static uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM};
348 static uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM};
349 static uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM};
350 static uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM};
351 static uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM};
352 static uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM};
353 static uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM};
354 static uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM};
355 static uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM};
356 static uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM};
357 static uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM};
358 static uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM};
360 static uint32_t g_contained_v0[] = {fpu_v0, LLDB_INVALID_REGNUM};
361 static uint32_t g_contained_v1[] = {fpu_v1, LLDB_INVALID_REGNUM};
362 static uint32_t g_contained_v2[] = {fpu_v2, LLDB_INVALID_REGNUM};
363 static uint32_t g_contained_v3[] = {fpu_v3, LLDB_INVALID_REGNUM};
364 static uint32_t g_contained_v4[] = {fpu_v4, LLDB_INVALID_REGNUM};
365 static uint32_t g_contained_v5[] = {fpu_v5, LLDB_INVALID_REGNUM};
366 static uint32_t g_contained_v6[] = {fpu_v6, LLDB_INVALID_REGNUM};
367 static uint32_t g_contained_v7[] = {fpu_v7, LLDB_INVALID_REGNUM};
368 static uint32_t g_contained_v8[] = {fpu_v8, LLDB_INVALID_REGNUM};
369 static uint32_t g_contained_v9[] = {fpu_v9, LLDB_INVALID_REGNUM};
370 static uint32_t g_contained_v10[] = {fpu_v10, LLDB_INVALID_REGNUM};
371 static uint32_t g_contained_v11[] = {fpu_v11, LLDB_INVALID_REGNUM};
372 static uint32_t g_contained_v12[] = {fpu_v12, LLDB_INVALID_REGNUM};
373 static uint32_t g_contained_v13[] = {fpu_v13, LLDB_INVALID_REGNUM};
374 static uint32_t g_contained_v14[] = {fpu_v14, LLDB_INVALID_REGNUM};
375 static uint32_t g_contained_v15[] = {fpu_v15, LLDB_INVALID_REGNUM};
376 static uint32_t g_contained_v16[] = {fpu_v16, LLDB_INVALID_REGNUM};
377 static uint32_t g_contained_v17[] = {fpu_v17, LLDB_INVALID_REGNUM};
378 static uint32_t g_contained_v18[] = {fpu_v18, LLDB_INVALID_REGNUM};
379 static uint32_t g_contained_v19[] = {fpu_v19, LLDB_INVALID_REGNUM};
380 static uint32_t g_contained_v20[] = {fpu_v20, LLDB_INVALID_REGNUM};
381 static uint32_t g_contained_v21[] = {fpu_v21, LLDB_INVALID_REGNUM};
382 static uint32_t g_contained_v22[] = {fpu_v22, LLDB_INVALID_REGNUM};
383 static uint32_t g_contained_v23[] = {fpu_v23, LLDB_INVALID_REGNUM};
384 static uint32_t g_contained_v24[] = {fpu_v24, LLDB_INVALID_REGNUM};
385 static uint32_t g_contained_v25[] = {fpu_v25, LLDB_INVALID_REGNUM};
386 static uint32_t g_contained_v26[] = {fpu_v26, LLDB_INVALID_REGNUM};
387 static uint32_t g_contained_v27[] = {fpu_v27, LLDB_INVALID_REGNUM};
388 static uint32_t g_contained_v28[] = {fpu_v28, LLDB_INVALID_REGNUM};
389 static uint32_t g_contained_v29[] = {fpu_v29, LLDB_INVALID_REGNUM};
390 static uint32_t g_contained_v30[] = {fpu_v30, LLDB_INVALID_REGNUM};
391 static uint32_t g_contained_v31[] = {fpu_v31, LLDB_INVALID_REGNUM};
393 static uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM};
394 static uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM};
395 static uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM};
396 static uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM};
397 static uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM};
398 static uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM};
399 static uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM};
400 static uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM};
401 static uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM};
402 static uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM};
403 static uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM};
404 static uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM};
405 static uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM};
406 static uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM};
407 static uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM};
408 static uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM};
409 static uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM};
410 static uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM};
411 static uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM};
412 static uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM};
413 static uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM};
414 static uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM};
415 static uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM};
416 static uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM};
417 static uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM};
418 static uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM};
419 static uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM};
420 static uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM};
421 static uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM};
422 static uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM};
423 static uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM};
424 static uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM};
426 static uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM};
427 static uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM};
428 static uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM};
429 static uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM};
430 static uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM};
431 static uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM};
432 static uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM};
433 static uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM};
434 static uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM};
435 static uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM};
436 static uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM};
437 static uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM};
438 static uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM};
439 static uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM};
440 static uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM};
441 static uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM};
442 static uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM};
443 static uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM};
444 static uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM};
445 static uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM};
446 static uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM};
447 static uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM};
448 static uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM};
449 static uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM};
450 static uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM};
451 static uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM};
452 static uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM};
453 static uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM};
454 static uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM};
455 static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM};
456 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
457 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
459 // Generates register kinds array with DWARF, EH frame and generic kind
460 #define MISC_KIND(reg, type, generic_kind) \
462 arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM, \
466 // Generates register kinds array for registers with only lldb kind
467 #define LLDB_KIND(lldb_kind) \
469 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
470 LLDB_INVALID_REGNUM, lldb_kind \
473 // Generates register kinds array for vector registers
474 #define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
475 #define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
476 #define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
477 #define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
478 #define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
480 // Defines a 64-bit general purpose register
481 #define DEFINE_GPR64(reg, generic_kind) \
483 #reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
484 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
488 // Defines a 64-bit general purpose register
489 #define DEFINE_GPR64_ALT(reg, alt, generic_kind) \
491 #reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint, \
492 lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr, \
496 // Defines a 32-bit general purpose pseudo register
497 #define DEFINE_GPR32(wreg, xreg) \
500 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, \
501 lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg), \
502 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 \
505 // Defines a vector register with 16-byte size
506 #define DEFINE_VREG(reg) \
508 #reg, nullptr, 16, FPU_OFFSET(fpu_##reg - fpu_v0), lldb::eEncodingVector, \
509 lldb::eFormatVectorOfUInt8, VREG_KIND(reg), nullptr, nullptr, nullptr, \
513 // Defines S and D pseudo registers mapping over corresponding vector register
514 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg) \
516 #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset, \
517 lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg), \
518 g_contained_##vreg, g_##reg##_invalidates, nullptr, 0 \
521 // Defines miscellaneous status and control registers like cpsr, fpsr etc
522 #define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind) \
524 #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
525 lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr, \
529 static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
530 // DEFINE_GPR64(name, GENERIC KIND)
531 DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
532 DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
533 DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
534 DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
535 DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
536 DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
537 DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
538 DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
539 DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
540 DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
541 DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
542 DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
543 DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
544 DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
545 DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
546 DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
547 DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
548 DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
549 DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
550 DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
551 DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
552 DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
553 DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
554 DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
555 DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
556 DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
557 DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
558 DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
559 DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
560 // DEFINE_GPR64(name, GENERIC KIND)
561 DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
562 DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
563 DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
564 DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
566 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
567 DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
569 // DEFINE_GPR32(name, parent name)
570 DEFINE_GPR32(w0, x0),
571 DEFINE_GPR32(w1, x1),
572 DEFINE_GPR32(w2, x2),
573 DEFINE_GPR32(w3, x3),
574 DEFINE_GPR32(w4, x4),
575 DEFINE_GPR32(w5, x5),
576 DEFINE_GPR32(w6, x6),
577 DEFINE_GPR32(w7, x7),
578 DEFINE_GPR32(w8, x8),
579 DEFINE_GPR32(w9, x9),
580 DEFINE_GPR32(w10, x10),
581 DEFINE_GPR32(w11, x11),
582 DEFINE_GPR32(w12, x12),
583 DEFINE_GPR32(w13, x13),
584 DEFINE_GPR32(w14, x14),
585 DEFINE_GPR32(w15, x15),
586 DEFINE_GPR32(w16, x16),
587 DEFINE_GPR32(w17, x17),
588 DEFINE_GPR32(w18, x18),
589 DEFINE_GPR32(w19, x19),
590 DEFINE_GPR32(w20, x20),
591 DEFINE_GPR32(w21, x21),
592 DEFINE_GPR32(w22, x22),
593 DEFINE_GPR32(w23, x23),
594 DEFINE_GPR32(w24, x24),
595 DEFINE_GPR32(w25, x25),
596 DEFINE_GPR32(w26, x26),
597 DEFINE_GPR32(w27, x27),
598 DEFINE_GPR32(w28, x28),
634 // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
635 DEFINE_FPU_PSEUDO(s0, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v0),
636 DEFINE_FPU_PSEUDO(s1, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v1),
637 DEFINE_FPU_PSEUDO(s2, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v2),
638 DEFINE_FPU_PSEUDO(s3, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v3),
639 DEFINE_FPU_PSEUDO(s4, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v4),
640 DEFINE_FPU_PSEUDO(s5, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v5),
641 DEFINE_FPU_PSEUDO(s6, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v6),
642 DEFINE_FPU_PSEUDO(s7, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v7),
643 DEFINE_FPU_PSEUDO(s8, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v8),
644 DEFINE_FPU_PSEUDO(s9, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v9),
645 DEFINE_FPU_PSEUDO(s10, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v10),
646 DEFINE_FPU_PSEUDO(s11, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v11),
647 DEFINE_FPU_PSEUDO(s12, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v12),
648 DEFINE_FPU_PSEUDO(s13, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v13),
649 DEFINE_FPU_PSEUDO(s14, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v14),
650 DEFINE_FPU_PSEUDO(s15, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v15),
651 DEFINE_FPU_PSEUDO(s16, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v16),
652 DEFINE_FPU_PSEUDO(s17, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v17),
653 DEFINE_FPU_PSEUDO(s18, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v18),
654 DEFINE_FPU_PSEUDO(s19, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v19),
655 DEFINE_FPU_PSEUDO(s20, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v20),
656 DEFINE_FPU_PSEUDO(s21, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v21),
657 DEFINE_FPU_PSEUDO(s22, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v22),
658 DEFINE_FPU_PSEUDO(s23, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v23),
659 DEFINE_FPU_PSEUDO(s24, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v24),
660 DEFINE_FPU_PSEUDO(s25, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v25),
661 DEFINE_FPU_PSEUDO(s26, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v26),
662 DEFINE_FPU_PSEUDO(s27, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v27),
663 DEFINE_FPU_PSEUDO(s28, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v28),
664 DEFINE_FPU_PSEUDO(s29, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v29),
665 DEFINE_FPU_PSEUDO(s30, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v30),
666 DEFINE_FPU_PSEUDO(s31, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v31),
668 DEFINE_FPU_PSEUDO(d0, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v0),
669 DEFINE_FPU_PSEUDO(d1, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v1),
670 DEFINE_FPU_PSEUDO(d2, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v2),
671 DEFINE_FPU_PSEUDO(d3, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v3),
672 DEFINE_FPU_PSEUDO(d4, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v4),
673 DEFINE_FPU_PSEUDO(d5, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v5),
674 DEFINE_FPU_PSEUDO(d6, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v6),
675 DEFINE_FPU_PSEUDO(d7, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v7),
676 DEFINE_FPU_PSEUDO(d8, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v8),
677 DEFINE_FPU_PSEUDO(d9, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v9),
678 DEFINE_FPU_PSEUDO(d10, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v10),
679 DEFINE_FPU_PSEUDO(d11, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v11),
680 DEFINE_FPU_PSEUDO(d12, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v12),
681 DEFINE_FPU_PSEUDO(d13, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v13),
682 DEFINE_FPU_PSEUDO(d14, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v14),
683 DEFINE_FPU_PSEUDO(d15, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v15),
684 DEFINE_FPU_PSEUDO(d16, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v16),
685 DEFINE_FPU_PSEUDO(d17, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v17),
686 DEFINE_FPU_PSEUDO(d18, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v18),
687 DEFINE_FPU_PSEUDO(d19, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v19),
688 DEFINE_FPU_PSEUDO(d20, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v20),
689 DEFINE_FPU_PSEUDO(d21, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v21),
690 DEFINE_FPU_PSEUDO(d22, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v22),
691 DEFINE_FPU_PSEUDO(d23, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v23),
692 DEFINE_FPU_PSEUDO(d24, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v24),
693 DEFINE_FPU_PSEUDO(d25, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v25),
694 DEFINE_FPU_PSEUDO(d26, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v26),
695 DEFINE_FPU_PSEUDO(d27, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v27),
696 DEFINE_FPU_PSEUDO(d28, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v28),
697 DEFINE_FPU_PSEUDO(d29, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v29),
698 DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
699 DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
701 // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
702 DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
703 DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
704 DEFINE_MISC_REGS(far, 8, EXC, exc_far),
705 DEFINE_MISC_REGS(esr, 4, EXC, exc_esr),
706 DEFINE_MISC_REGS(exception, 4, EXC, exc_exception),
708 {DEFINE_DBG(bvr, 0)},
709 {DEFINE_DBG(bvr, 1)},
710 {DEFINE_DBG(bvr, 2)},
711 {DEFINE_DBG(bvr, 3)},
712 {DEFINE_DBG(bvr, 4)},
713 {DEFINE_DBG(bvr, 5)},
714 {DEFINE_DBG(bvr, 6)},
715 {DEFINE_DBG(bvr, 7)},
716 {DEFINE_DBG(bvr, 8)},
717 {DEFINE_DBG(bvr, 9)},
718 {DEFINE_DBG(bvr, 10)},
719 {DEFINE_DBG(bvr, 11)},
720 {DEFINE_DBG(bvr, 12)},
721 {DEFINE_DBG(bvr, 13)},
722 {DEFINE_DBG(bvr, 14)},
723 {DEFINE_DBG(bvr, 15)},
725 {DEFINE_DBG(bcr, 0)},
726 {DEFINE_DBG(bcr, 1)},
727 {DEFINE_DBG(bcr, 2)},
728 {DEFINE_DBG(bcr, 3)},
729 {DEFINE_DBG(bcr, 4)},
730 {DEFINE_DBG(bcr, 5)},
731 {DEFINE_DBG(bcr, 6)},
732 {DEFINE_DBG(bcr, 7)},
733 {DEFINE_DBG(bcr, 8)},
734 {DEFINE_DBG(bcr, 9)},
735 {DEFINE_DBG(bcr, 10)},
736 {DEFINE_DBG(bcr, 11)},
737 {DEFINE_DBG(bcr, 12)},
738 {DEFINE_DBG(bcr, 13)},
739 {DEFINE_DBG(bcr, 14)},
740 {DEFINE_DBG(bcr, 15)},
742 {DEFINE_DBG(wvr, 0)},
743 {DEFINE_DBG(wvr, 1)},
744 {DEFINE_DBG(wvr, 2)},
745 {DEFINE_DBG(wvr, 3)},
746 {DEFINE_DBG(wvr, 4)},
747 {DEFINE_DBG(wvr, 5)},
748 {DEFINE_DBG(wvr, 6)},
749 {DEFINE_DBG(wvr, 7)},
750 {DEFINE_DBG(wvr, 8)},
751 {DEFINE_DBG(wvr, 9)},
752 {DEFINE_DBG(wvr, 10)},
753 {DEFINE_DBG(wvr, 11)},
754 {DEFINE_DBG(wvr, 12)},
755 {DEFINE_DBG(wvr, 13)},
756 {DEFINE_DBG(wvr, 14)},
757 {DEFINE_DBG(wvr, 15)},
759 {DEFINE_DBG(wcr, 0)},
760 {DEFINE_DBG(wcr, 1)},
761 {DEFINE_DBG(wcr, 2)},
762 {DEFINE_DBG(wcr, 3)},
763 {DEFINE_DBG(wcr, 4)},
764 {DEFINE_DBG(wcr, 5)},
765 {DEFINE_DBG(wcr, 6)},
766 {DEFINE_DBG(wcr, 7)},
767 {DEFINE_DBG(wcr, 8)},
768 {DEFINE_DBG(wcr, 9)},
769 {DEFINE_DBG(wcr, 10)},
770 {DEFINE_DBG(wcr, 11)},
771 {DEFINE_DBG(wcr, 12)},
772 {DEFINE_DBG(wcr, 13)},
773 {DEFINE_DBG(wcr, 14)},
774 {DEFINE_DBG(wcr, 15)}
778 #endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT