1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This implements routines for translating functions from LLVM IR into
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/ISDOpcodes.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/IR/Value.h"
29 #include "llvm/Support/KnownBits.h"
38 class BranchProbabilityInfo;
39 class LegacyDivergenceAnalysis;
42 class MachineFunction;
44 class MachineRegisterInfo;
49 //===--------------------------------------------------------------------===//
50 /// FunctionLoweringInfo - This contains information that is global to a
51 /// function that is used when lowering a region of the function.
53 class FunctionLoweringInfo {
57 const TargetLowering *TLI;
58 MachineRegisterInfo *RegInfo;
59 BranchProbabilityInfo *BPI;
60 const LegacyDivergenceAnalysis *DA;
61 /// CanLowerReturn - true iff the function's return value can be lowered to
65 /// True if part of the CSRs will be handled via explicit copies.
68 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
69 /// allocated to hold a pointer to the hidden sret parameter.
70 Register DemoteRegister;
72 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
73 DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
75 /// ValueMap - Since we emit code for the function a basic block at a time,
76 /// we must remember which virtual registers hold the values for
77 /// cross-basic-block values.
78 DenseMap<const Value *, Register> ValueMap;
80 /// VirtReg2Value map is needed by the Divergence Analysis driven
81 /// instruction selection. It is reverted ValueMap. It is computed
82 /// in lazy style - on demand. It is used to get the Value corresponding
83 /// to the live in virtual register and is called from the
84 /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
85 DenseMap<Register, const Value*> VirtReg2Value;
87 /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
88 /// to get the Value corresponding to the live-in virtual register.
89 const Value *getValueFromVirtualReg(Register Vreg);
91 /// Track virtual registers created for exception pointers.
92 DenseMap<const Value *, Register> CatchPadExceptionPointers;
94 /// Keep track of frame indices allocated for statepoints as they could be
95 /// used across basic block boundaries (e.g. for an invoke). For each
96 /// gc.statepoint instruction, maps uniqued llvm IR values to the slots they
97 /// were spilled in. If a value is mapped to None it means we visited the
98 /// value but didn't spill it (because it was a constant, for instance).
99 using StatepointSpillMapTy = DenseMap<const Value *, Optional<int>>;
100 DenseMap<const Instruction *, StatepointSpillMapTy> StatepointSpillMaps;
102 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
103 /// the entry block. This allows the allocas to be efficiently referenced
104 /// anywhere in the function.
105 DenseMap<const AllocaInst*, int> StaticAllocaMap;
107 /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
108 DenseMap<const Argument*, int> ByValArgFrameIndexMap;
110 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
111 /// function arguments that are inserted after scheduling is completed.
112 SmallVector<MachineInstr*, 8> ArgDbgValues;
114 /// Bitvector with a bit set if corresponding argument is described in
115 /// ArgDbgValues. Using arg numbers according to Argument numbering.
116 BitVector DescribedArgs;
118 /// RegFixups - Registers which need to be replaced after isel is done.
119 DenseMap<Register, Register> RegFixups;
121 DenseSet<Register> RegsWithFixups;
123 /// StatepointStackSlots - A list of temporary stack slots (frame indices)
124 /// used to spill values at a statepoint. We store them here to enable
125 /// reuse of the same stack slots across different statepoints in different
127 SmallVector<unsigned, 50> StatepointStackSlots;
129 /// MBB - The current block.
130 MachineBasicBlock *MBB;
132 /// MBB - The current insert position inside the current block.
133 MachineBasicBlock::iterator InsertPt;
136 unsigned NumSignBits : 31;
137 unsigned IsValid : 1;
140 LiveOutInfo() : NumSignBits(0), IsValid(true) {}
143 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
145 DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
147 /// VisitedBBs - The set of basic blocks visited thus far by instruction
149 SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
151 /// PHINodesToUpdate - A list of phi instructions whose operand list will
152 /// be updated after processing the current basic block.
153 /// TODO: This isn't per-function state, it's per-basic-block state. But
154 /// there's no other convenient place for it to live right now.
155 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
156 unsigned OrigNumPHINodesToUpdate;
158 /// If the current MBB is a landing pad, the exception pointer and exception
159 /// selector registers are copied into these virtual registers by
160 /// SelectionDAGISel::PrepareEHLandingPad().
161 unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
163 /// set - Initialize this FunctionLoweringInfo with the given Function
164 /// and its associated MachineFunction.
166 void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
168 /// clear - Clear out all the function-specific state. This returns this
169 /// FunctionLoweringInfo to an empty state, ready to be used for a
170 /// different function.
173 /// isExportedInst - Return true if the specified value is an instruction
174 /// exported from its block.
175 bool isExportedInst(const Value *V) const {
176 return ValueMap.count(V);
179 Register CreateReg(MVT VT, bool isDivergent = false);
181 Register CreateRegs(const Value *V);
183 Register CreateRegs(Type *Ty, bool isDivergent = false);
185 Register InitializeRegForValue(const Value *V) {
186 // Tokens never live in vregs.
187 if (V->getType()->isTokenTy())
189 Register &R = ValueMap[V];
190 assert(R == 0 && "Already initialized this value register!");
191 assert(VirtReg2Value.empty());
192 return R = CreateRegs(V);
195 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
196 /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
197 const LiveOutInfo *GetLiveOutRegInfo(Register Reg) {
198 if (!LiveOutRegInfo.inBounds(Reg))
201 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
208 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
209 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
210 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
211 /// the larger bit width by zero extension. The bit width must be no smaller
212 /// than the LiveOutInfo's existing bit width.
213 const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
215 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
216 void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
217 const KnownBits &Known) {
218 // Only install this information if it tells us something.
219 if (NumSignBits == 1 && Known.isUnknown())
222 LiveOutRegInfo.grow(Reg);
223 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
224 LOI.NumSignBits = NumSignBits;
225 LOI.Known.One = Known.One;
226 LOI.Known.Zero = Known.Zero;
229 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
230 /// register based on the LiveOutInfo of its operands.
231 void ComputePHILiveOutRegInfo(const PHINode*);
233 /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
234 /// called when a block is visited before all of its predecessors.
235 void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
236 // PHIs with no uses have no ValueMap entry.
237 DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(PN);
238 if (It == ValueMap.end())
241 Register Reg = It->second;
245 LiveOutRegInfo.grow(Reg);
246 LiveOutRegInfo[Reg].IsValid = false;
249 /// setArgumentFrameIndex - Record frame index for the byval
251 void setArgumentFrameIndex(const Argument *A, int FI);
253 /// getArgumentFrameIndex - Get frame index for the byval argument.
254 int getArgumentFrameIndex(const Argument *A);
256 Register getCatchPadExceptionPointerVReg(const Value *CPI,
257 const TargetRegisterClass *RC);
260 /// LiveOutRegInfo - Information about live out vregs.
261 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
264 } // end namespace llvm
266 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H