1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
16 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
17 #include "llvm/CodeGen/LowLevelType.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/DebugLoc.h"
27 // Forward declarations.
28 class MachineFunction;
30 class TargetInstrInfo;
31 class GISelChangeObserver;
33 /// Class which stores all the state required in a MachineIRBuilder.
34 /// Since MachineIRBuilders will only store state in this object, it allows
35 /// to transfer BuilderState between different kinds of MachineIRBuilders.
36 struct MachineIRBuilderState {
37 /// MachineFunction under construction.
38 MachineFunction *MF = nullptr;
39 /// Information used to access the description of the opcodes.
40 const TargetInstrInfo *TII = nullptr;
41 /// Information used to verify types are consistent and to create virtual registers.
42 MachineRegisterInfo *MRI = nullptr;
43 /// Debug location to be set to any instruction we create.
46 /// \name Fields describing the insertion point.
48 MachineBasicBlock *MBB = nullptr;
49 MachineBasicBlock::iterator II;
52 GISelChangeObserver *Observer = nullptr;
54 GISelCSEInfo *CSEInfo = nullptr;
61 const TargetRegisterClass *RC;
65 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
66 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
67 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
68 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
69 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
70 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
78 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
81 MIB.addDef(MRI.createVirtualRegister(RC));
86 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
93 return MRI.getType(Reg);
95 llvm_unreachable("Unrecognised DstOp::DstType enum");
98 Register getReg() const {
99 assert(Ty == DstType::Ty_Reg && "Not a register");
103 const TargetRegisterClass *getRegClass() const {
108 llvm_unreachable("Not a RC Operand");
112 DstType getDstOpKind() const { return Ty; }
120 MachineInstrBuilder SrcMIB;
122 CmpInst::Predicate Pred;
127 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
128 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
130 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
131 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 /// Use of registers held in unsigned integer variables (or more rarely signed
133 /// integers) is no longer permitted to avoid ambiguity with upcoming support
135 SrcOp(unsigned) = delete;
137 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
138 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140 void addSrcToMIB(MachineInstrBuilder &MIB) const {
142 case SrcType::Ty_Predicate:
143 MIB.addPredicate(Pred);
145 case SrcType::Ty_Reg:
148 case SrcType::Ty_MIB:
149 MIB.addUse(SrcMIB->getOperand(0).getReg());
151 case SrcType::Ty_Imm:
157 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
159 case SrcType::Ty_Predicate:
160 case SrcType::Ty_Imm:
161 llvm_unreachable("Not a register operand");
162 case SrcType::Ty_Reg:
163 return MRI.getType(Reg);
164 case SrcType::Ty_MIB:
165 return MRI.getType(SrcMIB->getOperand(0).getReg());
167 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
170 Register getReg() const {
172 case SrcType::Ty_Predicate:
173 case SrcType::Ty_Imm:
174 llvm_unreachable("Not a register operand");
175 case SrcType::Ty_Reg:
177 case SrcType::Ty_MIB:
178 return SrcMIB->getOperand(0).getReg();
180 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
183 CmpInst::Predicate getPredicate() const {
185 case SrcType::Ty_Predicate:
188 llvm_unreachable("Not a register operand");
192 int64_t getImm() const {
194 case SrcType::Ty_Imm:
197 llvm_unreachable("Not an immediate");
201 SrcType getSrcOpKind() const { return Ty; }
208 Optional<unsigned> Flags;
211 explicit FlagsOp(unsigned F) : Flags(F) {}
212 FlagsOp() : Flags(None) {}
213 Optional<unsigned> getFlags() const { return Flags; }
215 /// Helper class to build MachineInstr.
216 /// It keeps internally the insertion point and debug location for all
217 /// the new instructions we want to create.
218 /// This information can be modify via the related setters.
219 class MachineIRBuilder {
221 MachineIRBuilderState State;
224 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
226 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
227 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
229 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
232 void recordInsertion(MachineInstr *InsertedInstr) const {
234 State.Observer->createdInstr(*InsertedInstr);
238 /// Some constructors for easy use.
239 MachineIRBuilder() = default;
240 MachineIRBuilder(MachineFunction &MF) { setMF(MF); }
242 MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) {
243 setMF(*MBB.getParent());
244 setInsertPt(MBB, InsPt);
247 MachineIRBuilder(MachineInstr &MI) :
248 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
250 setDebugLoc(MI.getDebugLoc());
253 virtual ~MachineIRBuilder() = default;
255 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
257 const TargetInstrInfo &getTII() {
258 assert(State.TII && "TargetInstrInfo is not set");
262 /// Getter for the function we currently build.
263 MachineFunction &getMF() {
264 assert(State.MF && "MachineFunction is not set");
268 const MachineFunction &getMF() const {
269 assert(State.MF && "MachineFunction is not set");
273 const DataLayout &getDataLayout() const {
274 return getMF().getFunction().getParent()->getDataLayout();
277 /// Getter for DebugLoc
278 const DebugLoc &getDL() { return State.DL; }
281 MachineRegisterInfo *getMRI() { return State.MRI; }
282 const MachineRegisterInfo *getMRI() const { return State.MRI; }
284 /// Getter for the State
285 MachineIRBuilderState &getState() { return State; }
287 /// Getter for the basic block we currently build.
288 const MachineBasicBlock &getMBB() const {
289 assert(State.MBB && "MachineBasicBlock is not set");
293 MachineBasicBlock &getMBB() {
294 return const_cast<MachineBasicBlock &>(
295 const_cast<const MachineIRBuilder *>(this)->getMBB());
298 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
299 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
301 /// Current insertion point for new instructions.
302 MachineBasicBlock::iterator getInsertPt() { return State.II; }
304 /// Set the insertion point before the specified position.
305 /// \pre MBB must be in getMF().
306 /// \pre II must be a valid iterator in MBB.
307 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) {
308 assert(MBB.getParent() == &getMF() &&
309 "Basic block is in a different function");
316 void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
318 /// \name Setters for the insertion point.
320 /// Set the MachineFunction where to build instructions.
321 void setMF(MachineFunction &MF);
323 /// Set the insertion point to the end of \p MBB.
324 /// \pre \p MBB must be contained by getMF().
325 void setMBB(MachineBasicBlock &MBB) {
327 State.II = MBB.end();
328 assert(&getMF() == MBB.getParent() &&
329 "Basic block is in a different function");
332 /// Set the insertion point to before MI.
333 /// \pre MI must be in getMF().
334 void setInstr(MachineInstr &MI) {
335 assert(MI.getParent() && "Instruction is not part of a basic block");
336 setMBB(*MI.getParent());
337 State.II = MI.getIterator();
341 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
342 /// \pre MI must be in getMF().
343 void setInstrAndDebugLoc(MachineInstr &MI) {
345 setDebugLoc(MI.getDebugLoc());
348 void setChangeObserver(GISelChangeObserver &Observer) {
349 State.Observer = &Observer;
352 void stopObservingChanges() { State.Observer = nullptr; }
355 /// Set the debug location to \p DL for all the next build instructions.
356 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
358 /// Get the current instruction's debug location.
359 DebugLoc getDebugLoc() { return State.DL; }
361 /// Build and insert <empty> = \p Opcode <empty>.
362 /// The insertion point is the one set by the last call of either
363 /// setBasicBlock or setMI.
365 /// \pre setBasicBlock or setMI must have been called.
367 /// \return a MachineInstrBuilder for the newly created instruction.
368 MachineInstrBuilder buildInstr(unsigned Opcode) {
369 return insertInstr(buildInstrNoInsert(Opcode));
372 /// Build but don't insert <empty> = \p Opcode <empty>.
374 /// \pre setMF, setBasicBlock or setMI must have been called.
376 /// \return a MachineInstrBuilder for the newly created instruction.
377 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
379 /// Insert an existing instruction at the insertion point.
380 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
382 /// Build and insert a DBG_VALUE instruction expressing the fact that the
383 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
384 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
387 /// Build and insert a DBG_VALUE instruction expressing the fact that the
388 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
390 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
391 const MDNode *Variable,
394 /// Build and insert a DBG_VALUE instruction expressing the fact that the
395 /// associated \p Variable lives in the stack slot specified by \p FI
396 /// (suitably modified by \p Expr).
397 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
400 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
401 /// given by \p C (suitably modified by \p Expr).
402 MachineInstrBuilder buildConstDbgValue(const Constant &C,
403 const MDNode *Variable,
406 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
407 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
408 MachineInstrBuilder buildDbgLabel(const MDNode *Label);
410 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
412 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
413 /// the allocated memory into \p Res.
414 /// \pre setBasicBlock or setMI must have been called.
415 /// \pre \p Res must be a generic virtual register with pointer type.
417 /// \return a MachineInstrBuilder for the newly created instruction.
418 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
421 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
423 /// G_FRAME_INDEX materializes the address of an alloca value or other
424 /// stack-based object.
426 /// \pre setBasicBlock or setMI must have been called.
427 /// \pre \p Res must be a generic virtual register with pointer type.
429 /// \return a MachineInstrBuilder for the newly created instruction.
430 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
432 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
434 /// G_GLOBAL_VALUE materializes the address of the specified global
437 /// \pre setBasicBlock or setMI must have been called.
438 /// \pre \p Res must be a generic virtual register with pointer type
439 /// in the same address space as \p GV.
441 /// \return a MachineInstrBuilder for the newly created instruction.
442 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
444 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
446 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
447 /// storing the resulting pointer in \p Res. Addressible units are typically
448 /// bytes but this can vary between targets.
450 /// \pre setBasicBlock or setMI must have been called.
451 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
453 /// \pre \p Op1 must be a generic virtual register with scalar type.
455 /// \return a MachineInstrBuilder for the newly created instruction.
456 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
459 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
461 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
462 /// storing the resulting pointer in \p Res. If \p Value is zero then no
463 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
466 /// \pre setBasicBlock or setMI must have been called.
467 /// \pre \p Op0 must be a generic virtual register with pointer type.
468 /// \pre \p ValueTy must be a scalar type.
469 /// \pre \p Res must be 0. This is to detect confusion between
470 /// materializePtrAdd() and buildPtrAdd().
471 /// \post \p Res will either be a new generic virtual register of the same
472 /// type as \p Op0 or \p Op0 itself.
474 /// \return a MachineInstrBuilder for the newly created instruction.
475 Optional<MachineInstrBuilder> materializePtrAdd(Register &Res, Register Op0,
479 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
480 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
482 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
485 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
487 /// This clears the low bits of a pointer operand without destroying its
488 /// pointer properties. This has the effect of rounding the address *down* to
489 /// a specified alignment in bits.
491 /// \pre setBasicBlock or setMI must have been called.
492 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
494 /// \pre \p NumBits must be an integer representing the number of low bits to
495 /// be cleared in \p Op0.
497 /// \return a MachineInstrBuilder for the newly created instruction.
498 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
501 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
503 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
504 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
506 /// \pre setBasicBlock or setMI must have been called.
507 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
508 /// same scalar type.
509 ////\pre \p CarryOut must be generic virtual register with scalar type
512 /// \return The newly created instruction.
513 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
514 const SrcOp &Op0, const SrcOp &Op1) {
515 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
518 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
519 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
520 const SrcOp &Op0, const SrcOp &Op1) {
521 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
524 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
525 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
526 const SrcOp &Op0, const SrcOp &Op1) {
527 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
530 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
531 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
532 const SrcOp &Op0, const SrcOp &Op1) {
533 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
536 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
537 /// \p Op1, \p CarryIn
539 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
540 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
543 /// \pre setBasicBlock or setMI must have been called.
544 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
545 /// with the same scalar type.
546 /// \pre \p CarryOut and \p CarryIn must be generic virtual
547 /// registers with the same scalar type (typically s1)
549 /// \return The newly created instruction.
550 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
551 const SrcOp &Op0, const SrcOp &Op1,
552 const SrcOp &CarryIn) {
553 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
554 {Op0, Op1, CarryIn});
557 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
558 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
559 const SrcOp &Op0, const SrcOp &Op1,
560 const SrcOp &CarryIn) {
561 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
562 {Op0, Op1, CarryIn});
565 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
566 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
567 const SrcOp &Op0, const SrcOp &Op1,
568 const SrcOp &CarryIn) {
569 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
570 {Op0, Op1, CarryIn});
573 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
574 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
575 const SrcOp &Op0, const SrcOp &Op1,
576 const SrcOp &CarryIn) {
577 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
578 {Op0, Op1, CarryIn});
581 /// Build and insert \p Res = G_ANYEXT \p Op0
583 /// G_ANYEXT produces a register of the specified width, with bits 0 to
584 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
585 /// (i.e. this is neither zero nor sign-extension). For a vector register,
586 /// each element is extended individually.
588 /// \pre setBasicBlock or setMI must have been called.
589 /// \pre \p Res must be a generic virtual register with scalar or vector type.
590 /// \pre \p Op must be a generic virtual register with scalar or vector type.
591 /// \pre \p Op must be smaller than \p Res
593 /// \return The newly created instruction.
595 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
597 /// Build and insert \p Res = G_SEXT \p Op
599 /// G_SEXT produces a register of the specified width, with bits 0 to
600 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
601 /// high bit of \p Op (i.e. 2s-complement sign extended).
603 /// \pre setBasicBlock or setMI must have been called.
604 /// \pre \p Res must be a generic virtual register with scalar or vector type.
605 /// \pre \p Op must be a generic virtual register with scalar or vector type.
606 /// \pre \p Op must be smaller than \p Res
608 /// \return The newly created instruction.
609 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
611 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
612 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
613 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
616 /// Build and insert \p Res = G_FPEXT \p Op
617 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op,
618 Optional<unsigned> Flags = None) {
619 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
623 /// Build and insert a G_PTRTOINT instruction.
624 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
625 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
628 /// Build and insert a G_INTTOPTR instruction.
629 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
630 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
633 /// Build and insert \p Dst = G_BITCAST \p Src
634 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
635 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
638 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
639 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {
640 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
643 /// \return The opcode of the extension the target wants to use for boolean
645 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
647 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
648 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
649 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
652 /// Build and insert \p Res = G_ZEXT \p Op
654 /// G_ZEXT produces a register of the specified width, with bits 0 to
655 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
656 /// register, each element is extended individually.
658 /// \pre setBasicBlock or setMI must have been called.
659 /// \pre \p Res must be a generic virtual register with scalar or vector type.
660 /// \pre \p Op must be a generic virtual register with scalar or vector type.
661 /// \pre \p Op must be smaller than \p Res
663 /// \return The newly created instruction.
664 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
666 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
667 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
669 /// \pre setBasicBlock or setMI must have been called.
670 /// \pre \p Res must be a generic virtual register with scalar or vector type.
671 /// \pre \p Op must be a generic virtual register with scalar or vector type.
673 /// \return The newly created instruction.
674 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
676 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
677 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
679 /// \pre setBasicBlock or setMI must have been called.
680 /// \pre \p Res must be a generic virtual register with scalar or vector type.
681 /// \pre \p Op must be a generic virtual register with scalar or vector type.
683 /// \return The newly created instruction.
684 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
686 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
687 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
689 /// \pre setBasicBlock or setMI must have been called.
690 /// \pre \p Res must be a generic virtual register with scalar or vector type.
691 /// \pre \p Op must be a generic virtual register with scalar or vector type.
693 /// \return The newly created instruction.
694 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
696 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
697 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
700 /// \pre setBasicBlock or setMI must have been called.
701 /// \pre \p Res must be a generic virtual register with scalar or vector type.
702 /// \pre \p Op must be a generic virtual register with scalar or vector type.
704 /// \return The newly created instruction.
705 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
708 /// Build and insert an appropriate cast between two registers of equal size.
709 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
711 /// Build and insert G_BR \p Dest
713 /// G_BR is an unconditional branch to \p Dest.
715 /// \pre setBasicBlock or setMI must have been called.
717 /// \return a MachineInstrBuilder for the newly created instruction.
718 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
720 /// Build and insert G_BRCOND \p Tst, \p Dest
722 /// G_BRCOND is a conditional branch to \p Dest.
724 /// \pre setBasicBlock or setMI must have been called.
725 /// \pre \p Tst must be a generic virtual register with scalar
726 /// type. At the beginning of legalization, this will be a single
727 /// bit (s1). Targets with interesting flags registers may change
728 /// this. For a wider type, whether the branch is taken must only
729 /// depend on bit 0 (for now).
731 /// \return The newly created instruction.
732 MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
734 /// Build and insert G_BRINDIRECT \p Tgt
736 /// G_BRINDIRECT is an indirect branch to \p Tgt.
738 /// \pre setBasicBlock or setMI must have been called.
739 /// \pre \p Tgt must be a generic virtual register with pointer type.
741 /// \return a MachineInstrBuilder for the newly created instruction.
742 MachineInstrBuilder buildBrIndirect(Register Tgt);
744 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
746 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
747 /// jump table index \p JTI and index \p IndexReg
749 /// \pre setBasicBlock or setMI must have been called.
750 /// \pre \p TablePtr must be a generic virtual register with pointer type.
751 /// \pre \p JTI must be be a jump table index.
752 /// \pre \p IndexReg must be a generic virtual register with pointer type.
754 /// \return a MachineInstrBuilder for the newly created instruction.
755 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
758 /// Build and insert \p Res = G_CONSTANT \p Val
760 /// G_CONSTANT is an integer constant with the specified size and value. \p
761 /// Val will be extended or truncated to the size of \p Reg.
763 /// \pre setBasicBlock or setMI must have been called.
764 /// \pre \p Res must be a generic virtual register with scalar or pointer
767 /// \return The newly created instruction.
768 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
769 const ConstantInt &Val);
771 /// Build and insert \p Res = G_CONSTANT \p Val
773 /// G_CONSTANT is an integer constant with the specified size and value.
775 /// \pre setBasicBlock or setMI must have been called.
776 /// \pre \p Res must be a generic virtual register with scalar type.
778 /// \return The newly created instruction.
779 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
780 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
782 /// Build and insert \p Res = G_FCONSTANT \p Val
784 /// G_FCONSTANT is a floating-point constant with the specified size and
787 /// \pre setBasicBlock or setMI must have been called.
788 /// \pre \p Res must be a generic virtual register with scalar type.
790 /// \return The newly created instruction.
791 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
792 const ConstantFP &Val);
794 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
795 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
797 /// Build and insert \p Res = COPY Op
799 /// Register-to-register COPY sets \p Res to \p Op.
801 /// \pre setBasicBlock or setMI must have been called.
803 /// \return a MachineInstrBuilder for the newly created instruction.
804 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
806 /// Build and insert `Res = G_LOAD Addr, MMO`.
808 /// Loads the value stored at \p Addr. Puts the result in \p Res.
810 /// \pre setBasicBlock or setMI must have been called.
811 /// \pre \p Res must be a generic virtual register.
812 /// \pre \p Addr must be a generic virtual register with pointer type.
814 /// \return a MachineInstrBuilder for the newly created instruction.
815 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
816 MachineMemOperand &MMO);
818 /// Build and insert `Res = <opcode> Addr, MMO`.
820 /// Loads the value stored at \p Addr. Puts the result in \p Res.
822 /// \pre setBasicBlock or setMI must have been called.
823 /// \pre \p Res must be a generic virtual register.
824 /// \pre \p Addr must be a generic virtual register with pointer type.
826 /// \return a MachineInstrBuilder for the newly created instruction.
827 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
828 const SrcOp &Addr, MachineMemOperand &MMO);
830 /// Helper to create a load from a constant offset given a base address. Load
831 /// the type of \p Dst from \p Offset from the given base address and memory
833 MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst,
834 const SrcOp &BasePtr,
835 MachineMemOperand &BaseMMO,
838 /// Build and insert `G_STORE Val, Addr, MMO`.
840 /// Stores the value \p Val to \p Addr.
842 /// \pre setBasicBlock or setMI must have been called.
843 /// \pre \p Val must be a generic virtual register.
844 /// \pre \p Addr must be a generic virtual register with pointer type.
846 /// \return a MachineInstrBuilder for the newly created instruction.
847 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
848 MachineMemOperand &MMO);
850 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
852 /// \pre setBasicBlock or setMI must have been called.
853 /// \pre \p Res and \p Src must be generic virtual registers.
855 /// \return a MachineInstrBuilder for the newly created instruction.
856 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
858 /// Build and insert \p Res = IMPLICIT_DEF.
859 MachineInstrBuilder buildUndef(const DstOp &Res);
861 /// Build and insert instructions to put \p Ops together at the specified p
862 /// Indices to form a larger register.
864 /// If the types of the input registers are uniform and cover the entirity of
865 /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
866 /// followed by a sequence of G_INSERT instructions.
868 /// \pre setBasicBlock or setMI must have been called.
869 /// \pre The final element of the sequence must not extend past the end of the
870 /// destination register.
871 /// \pre The bits defined by each Op (derived from index and scalar size) must
873 /// \pre \p Indices must be in ascending order of bit position.
874 void buildSequence(Register Res, ArrayRef<Register> Ops,
875 ArrayRef<uint64_t> Indices);
877 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
879 /// G_MERGE_VALUES combines the input elements contiguously into a larger
882 /// \pre setBasicBlock or setMI must have been called.
883 /// \pre The entire register \p Res (and no more) must be covered by the input
885 /// \pre The type of all \p Ops registers must be identical.
887 /// \return a MachineInstrBuilder for the newly created instruction.
888 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
889 MachineInstrBuilder buildMerge(const DstOp &Res,
890 std::initializer_list<SrcOp> Ops);
892 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
894 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
896 /// \pre setBasicBlock or setMI must have been called.
897 /// \pre The entire register \p Res (and no more) must be covered by the input
899 /// \pre The type of all \p Res registers must be identical.
901 /// \return a MachineInstrBuilder for the newly created instruction.
902 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
903 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
905 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
906 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
908 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
910 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
911 /// \pre setBasicBlock or setMI must have been called.
912 /// \pre The entire register \p Res (and no more) must be covered by the
913 /// input scalar registers.
914 /// \pre The type of all \p Ops registers must be identical.
916 /// \return a MachineInstrBuilder for the newly created instruction.
917 MachineInstrBuilder buildBuildVector(const DstOp &Res,
918 ArrayRef<Register> Ops);
920 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
921 /// the number of elements
922 MachineInstrBuilder buildSplatVector(const DstOp &Res,
925 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
927 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
928 /// which have types larger than the destination vector element type, and
929 /// truncates the values to fit.
931 /// If the operands given are already the same size as the vector elt type,
932 /// then this method will instead create a G_BUILD_VECTOR instruction.
934 /// \pre setBasicBlock or setMI must have been called.
935 /// \pre The type of all \p Ops registers must be identical.
937 /// \return a MachineInstrBuilder for the newly created instruction.
938 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
939 ArrayRef<Register> Ops);
941 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
943 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
946 /// \pre setBasicBlock or setMI must have been called.
947 /// \pre The entire register \p Res (and no more) must be covered by the input
949 /// \pre The type of all source operands must be identical.
951 /// \return a MachineInstrBuilder for the newly created instruction.
952 MachineInstrBuilder buildConcatVectors(const DstOp &Res,
953 ArrayRef<Register> Ops);
955 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
956 const SrcOp &Op, unsigned Index);
958 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
959 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
960 /// result register definition unless \p Reg is NoReg (== 0). The second
961 /// operand will be the intrinsic's ID.
963 /// Callers are expected to add the required definitions and uses afterwards.
965 /// \pre setBasicBlock or setMI must have been called.
967 /// \return a MachineInstrBuilder for the newly created instruction.
968 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res,
969 bool HasSideEffects);
970 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
971 bool HasSideEffects);
973 /// Build and insert \p Res = G_FPTRUNC \p Op
975 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
977 /// \pre setBasicBlock or setMI must have been called.
978 /// \pre \p Res must be a generic virtual register with scalar or vector type.
979 /// \pre \p Op must be a generic virtual register with scalar or vector type.
980 /// \pre \p Res must be smaller than \p Op
982 /// \return The newly created instruction.
983 MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
984 Optional<unsigned> Flags = None);
986 /// Build and insert \p Res = G_TRUNC \p Op
988 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
989 /// truncated independently before being packed into the destination.
991 /// \pre setBasicBlock or setMI must have been called.
992 /// \pre \p Res must be a generic virtual register with scalar or vector type.
993 /// \pre \p Op must be a generic virtual register with scalar or vector type.
994 /// \pre \p Res must be smaller than \p Op
996 /// \return The newly created instruction.
997 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
999 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1001 /// \pre setBasicBlock or setMI must have been called.
1003 /// \pre \p Res must be a generic virtual register with scalar or
1004 /// vector type. Typically this starts as s1 or <N x s1>.
1005 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1006 /// same number of elements as \p Res. If \p Res is a scalar,
1007 /// \p Op0 must be either a scalar or pointer.
1008 /// \pre \p Pred must be an integer predicate.
1010 /// \return a MachineInstrBuilder for the newly created instruction.
1011 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
1012 const SrcOp &Op0, const SrcOp &Op1);
1014 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1016 /// \pre setBasicBlock or setMI must have been called.
1018 /// \pre \p Res must be a generic virtual register with scalar or
1019 /// vector type. Typically this starts as s1 or <N x s1>.
1020 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1021 /// same number of elements as \p Res (or scalar, if \p Res is
1023 /// \pre \p Pred must be a floating-point predicate.
1025 /// \return a MachineInstrBuilder for the newly created instruction.
1026 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
1027 const SrcOp &Op0, const SrcOp &Op1,
1028 Optional<unsigned> Flags = None);
1030 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1032 /// \pre setBasicBlock or setMI must have been called.
1033 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1034 /// with the same type.
1035 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1036 /// vector type. If vector then it must have the same number of
1037 /// elements as the other parameters.
1039 /// \return a MachineInstrBuilder for the newly created instruction.
1040 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1041 const SrcOp &Op0, const SrcOp &Op1,
1042 Optional<unsigned> Flags = None);
1044 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1047 /// \pre setBasicBlock or setMI must have been called.
1048 /// \pre \p Res and \p Val must be a generic virtual register
1049 // with the same vector type.
1050 /// \pre \p Elt and \p Idx must be a generic virtual register
1051 /// with scalar type.
1053 /// \return The newly created instruction.
1054 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
1059 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1061 /// \pre setBasicBlock or setMI must have been called.
1062 /// \pre \p Res must be a generic virtual register with scalar type.
1063 /// \pre \p Val must be a generic virtual register with vector type.
1064 /// \pre \p Idx must be a generic virtual register with scalar type.
1066 /// \return The newly created instruction.
1067 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
1071 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1072 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1074 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1075 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1076 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1078 /// \pre setBasicBlock or setMI must have been called.
1079 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1080 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1081 /// will be assigned 0 on failure and 1 on success.
1082 /// \pre \p Addr must be a generic virtual register with pointer type.
1083 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1084 /// registers of the same type.
1086 /// \return a MachineInstrBuilder for the newly created instruction.
1088 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1089 Register Addr, Register CmpVal, Register NewVal,
1090 MachineMemOperand &MMO);
1092 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1095 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1096 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1099 /// \pre setBasicBlock or setMI must have been called.
1100 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1101 /// \pre \p Addr must be a generic virtual register with pointer type.
1102 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1103 /// registers of the same type.
1105 /// \return a MachineInstrBuilder for the newly created instruction.
1106 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
1107 Register CmpVal, Register NewVal,
1108 MachineMemOperand &MMO);
1110 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1112 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1113 /// original value from \p Addr in \p OldValRes. The modification is
1114 /// determined by the opcode.
1116 /// \pre setBasicBlock or setMI must have been called.
1117 /// \pre \p OldValRes must be a generic virtual register.
1118 /// \pre \p Addr must be a generic virtual register with pointer type.
1119 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1122 /// \return a MachineInstrBuilder for the newly created instruction.
1123 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1124 const SrcOp &Addr, const SrcOp &Val,
1125 MachineMemOperand &MMO);
1127 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1129 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1130 /// value from \p Addr in \p OldValRes.
1132 /// \pre setBasicBlock or setMI must have been called.
1133 /// \pre \p OldValRes must be a generic virtual register.
1134 /// \pre \p Addr must be a generic virtual register with pointer type.
1135 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1138 /// \return a MachineInstrBuilder for the newly created instruction.
1139 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1140 Register Val, MachineMemOperand &MMO);
1142 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1144 /// Atomically replace the value at \p Addr with the addition of \p Val and
1145 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1147 /// \pre setBasicBlock or setMI must have been called.
1148 /// \pre \p OldValRes must be a generic virtual register.
1149 /// \pre \p Addr must be a generic virtual register with pointer type.
1150 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1153 /// \return a MachineInstrBuilder for the newly created instruction.
1154 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1155 Register Val, MachineMemOperand &MMO);
1157 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1159 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1160 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1162 /// \pre setBasicBlock or setMI must have been called.
1163 /// \pre \p OldValRes must be a generic virtual register.
1164 /// \pre \p Addr must be a generic virtual register with pointer type.
1165 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1168 /// \return a MachineInstrBuilder for the newly created instruction.
1169 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1170 Register Val, MachineMemOperand &MMO);
1172 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1174 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1175 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1177 /// \pre setBasicBlock or setMI must have been called.
1178 /// \pre \p OldValRes must be a generic virtual register.
1179 /// \pre \p Addr must be a generic virtual register with pointer type.
1180 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1183 /// \return a MachineInstrBuilder for the newly created instruction.
1184 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1185 Register Val, MachineMemOperand &MMO);
1187 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1189 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1190 /// and the original value. Puts the original value from \p Addr in \p
1193 /// \pre setBasicBlock or setMI must have been called.
1194 /// \pre \p OldValRes must be a generic virtual register.
1195 /// \pre \p Addr must be a generic virtual register with pointer type.
1196 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1199 /// \return a MachineInstrBuilder for the newly created instruction.
1200 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1201 Register Val, MachineMemOperand &MMO);
1203 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1205 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1206 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1208 /// \pre setBasicBlock or setMI must have been called.
1209 /// \pre \p OldValRes must be a generic virtual register.
1210 /// \pre \p Addr must be a generic virtual register with pointer type.
1211 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1214 /// \return a MachineInstrBuilder for the newly created instruction.
1215 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1216 Register Val, MachineMemOperand &MMO);
1218 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1220 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1221 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1223 /// \pre setBasicBlock or setMI must have been called.
1224 /// \pre \p OldValRes must be a generic virtual register.
1225 /// \pre \p Addr must be a generic virtual register with pointer type.
1226 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1229 /// \return a MachineInstrBuilder for the newly created instruction.
1230 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1231 Register Val, MachineMemOperand &MMO);
1233 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1235 /// Atomically replace the value at \p Addr with the signed maximum of \p
1236 /// Val and the original value. Puts the original value from \p Addr in \p
1239 /// \pre setBasicBlock or setMI must have been called.
1240 /// \pre \p OldValRes must be a generic virtual register.
1241 /// \pre \p Addr must be a generic virtual register with pointer type.
1242 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1245 /// \return a MachineInstrBuilder for the newly created instruction.
1246 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1247 Register Val, MachineMemOperand &MMO);
1249 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1251 /// Atomically replace the value at \p Addr with the signed minimum of \p
1252 /// Val and the original value. Puts the original value from \p Addr in \p
1255 /// \pre setBasicBlock or setMI must have been called.
1256 /// \pre \p OldValRes must be a generic virtual register.
1257 /// \pre \p Addr must be a generic virtual register with pointer type.
1258 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1261 /// \return a MachineInstrBuilder for the newly created instruction.
1262 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1263 Register Val, MachineMemOperand &MMO);
1265 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1267 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1268 /// Val and the original value. Puts the original value from \p Addr in \p
1271 /// \pre setBasicBlock or setMI must have been called.
1272 /// \pre \p OldValRes must be a generic virtual register.
1273 /// \pre \p Addr must be a generic virtual register with pointer type.
1274 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1277 /// \return a MachineInstrBuilder for the newly created instruction.
1278 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1279 Register Val, MachineMemOperand &MMO);
1281 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1283 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1284 /// Val and the original value. Puts the original value from \p Addr in \p
1287 /// \pre setBasicBlock or setMI must have been called.
1288 /// \pre \p OldValRes must be a generic virtual register.
1289 /// \pre \p Addr must be a generic virtual register with pointer type.
1290 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1293 /// \return a MachineInstrBuilder for the newly created instruction.
1294 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1295 Register Val, MachineMemOperand &MMO);
1297 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1298 MachineInstrBuilder buildAtomicRMWFAdd(
1299 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1300 MachineMemOperand &MMO);
1302 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1303 MachineInstrBuilder buildAtomicRMWFSub(
1304 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1305 MachineMemOperand &MMO);
1307 /// Build and insert `G_FENCE Ordering, Scope`.
1308 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1310 /// Build and insert \p Dst = G_FREEZE \p Src
1311 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1312 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1315 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1317 /// G_BLOCK_ADDR computes the address of a basic block.
1319 /// \pre setBasicBlock or setMI must have been called.
1320 /// \pre \p Res must be a generic virtual register of a pointer type.
1322 /// \return The newly created instruction.
1323 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1325 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1327 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1328 /// truncated to their width.
1330 /// \pre setBasicBlock or setMI must have been called.
1331 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1332 /// with the same (scalar or vector) type).
1334 /// \return a MachineInstrBuilder for the newly created instruction.
1336 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1338 Optional<unsigned> Flags = None) {
1339 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1342 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1344 /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1345 /// truncated to their width.
1347 /// \pre setBasicBlock or setMI must have been called.
1348 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1349 /// with the same (scalar or vector) type).
1351 /// \return a MachineInstrBuilder for the newly created instruction.
1353 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1355 Optional<unsigned> Flags = None) {
1356 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1359 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1361 /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1362 /// truncated to their width.
1364 /// \pre setBasicBlock or setMI must have been called.
1365 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1366 /// with the same (scalar or vector) type).
1368 /// \return a MachineInstrBuilder for the newly created instruction.
1369 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1371 Optional<unsigned> Flags = None) {
1372 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1375 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1377 Optional<unsigned> Flags = None) {
1378 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1381 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1383 Optional<unsigned> Flags = None) {
1384 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1387 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1389 Optional<unsigned> Flags = None) {
1390 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1393 MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0,
1395 Optional<unsigned> Flags = None) {
1396 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1399 MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0,
1401 Optional<unsigned> Flags = None) {
1402 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1405 MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0,
1407 Optional<unsigned> Flags = None) {
1408 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1411 MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0,
1413 Optional<unsigned> Flags = None) {
1414 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1417 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1419 Optional<unsigned> Flags = None) {
1420 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1423 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1425 Optional<unsigned> Flags = None) {
1426 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1429 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1431 Optional<unsigned> Flags = None) {
1432 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1435 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1437 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1440 /// \pre setBasicBlock or setMI must have been called.
1441 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1442 /// with the same (scalar or vector) type).
1444 /// \return a MachineInstrBuilder for the newly created instruction.
1446 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1447 const SrcOp &Src1) {
1448 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1451 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1453 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1456 /// \pre setBasicBlock or setMI must have been called.
1457 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1458 /// with the same (scalar or vector) type).
1460 /// \return a MachineInstrBuilder for the newly created instruction.
1461 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1462 const SrcOp &Src1) {
1463 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1466 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1467 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1468 const SrcOp &Src1) {
1469 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1472 /// Build and insert a bitwise not,
1473 /// \p NegOne = G_CONSTANT -1
1474 /// \p Res = G_OR \p Op0, NegOne
1475 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1476 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1477 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1480 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1481 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1482 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1485 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1486 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1487 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1490 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1491 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1492 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1495 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1496 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1497 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1500 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1501 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1502 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1505 /// Build and insert \p Dst = G_BSWAP \p Src0
1506 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1507 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1510 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1511 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1513 Optional<unsigned> Flags = None) {
1514 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1517 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1518 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1520 Optional<unsigned> Flags = None) {
1521 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1524 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1525 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1526 const SrcOp &Src1, const SrcOp &Src2,
1527 Optional<unsigned> Flags = None) {
1528 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1531 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1532 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1533 const SrcOp &Src1, const SrcOp &Src2,
1534 Optional<unsigned> Flags = None) {
1535 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1538 /// Build and insert \p Res = G_FNEG \p Op0
1539 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1540 Optional<unsigned> Flags = None) {
1541 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1544 /// Build and insert \p Res = G_FABS \p Op0
1545 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1546 Optional<unsigned> Flags = None) {
1547 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1550 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1551 MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1552 Optional<unsigned> Flags = None) {
1553 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1556 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1557 MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1558 Optional<unsigned> Flags = None) {
1559 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1562 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1563 MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1564 Optional<unsigned> Flags = None) {
1565 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1568 /// Build and insert \p Dst = G_FLOG \p Src
1569 MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1570 Optional<unsigned> Flags = None) {
1571 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1574 /// Build and insert \p Dst = G_FLOG2 \p Src
1575 MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1576 Optional<unsigned> Flags = None) {
1577 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1580 /// Build and insert \p Dst = G_FEXP2 \p Src
1581 MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1582 Optional<unsigned> Flags = None) {
1583 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1586 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1587 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0,
1588 const SrcOp &Src1) {
1589 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1592 /// Build and insert \p Res = G_UITOFP \p Src0
1593 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1594 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1597 /// Build and insert \p Res = G_SITOFP \p Src0
1598 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1599 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1602 /// Build and insert \p Res = G_FPTOUI \p Src0
1603 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1604 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1607 /// Build and insert \p Res = G_FPTOSI \p Src0
1608 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1609 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1612 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1613 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1614 const SrcOp &Src1) {
1615 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1618 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1619 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1620 const SrcOp &Src1) {
1621 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1624 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1625 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1626 const SrcOp &Src1) {
1627 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1630 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1631 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1632 const SrcOp &Src1) {
1633 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1636 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1638 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1639 /// the jump table index \p JTI.
1641 /// \return a MachineInstrBuilder for the newly created instruction.
1642 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1644 virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1645 ArrayRef<SrcOp> SrcOps,
1646 Optional<unsigned> Flags = None);
1649 } // End namespace llvm.
1650 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H