1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares codegen opcodes and related utilities.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_CODEGEN_ISDOPCODES_H
14 #define LLVM_CODEGEN_ISDOPCODES_H
16 #include "llvm/CodeGen/ValueTypes.h"
20 /// ISD namespace - This namespace contains an enum which represents all of the
21 /// SelectionDAG node types and value types.
25 //===--------------------------------------------------------------------===//
26 /// ISD::NodeType enum - This enum defines the target-independent operators
27 /// for a SelectionDAG.
29 /// Targets may also define target-dependent operator codes for SDNodes. For
30 /// example, on x86, these are the enum values in the X86ISD namespace.
31 /// Targets should aim to use target-independent operators to model their
32 /// instruction sets as much as possible, and only use target-dependent
33 /// operators when they have special requirements.
35 /// Finally, during and after selection proper, SNodes may use special
36 /// operator codes that correspond directly with MachineInstr opcodes. These
37 /// are used to represent selected instructions. See the isMachineOpcode()
38 /// and getMachineOpcode() member functions of SDNode.
41 /// DELETED_NODE - This is an illegal value that is used to catch
42 /// errors. This opcode is not a legal opcode for any node.
45 /// EntryToken - This is the marker used to indicate the start of a region.
48 /// TokenFactor - This node takes multiple tokens as input and produces a
49 /// single token result. This is used to represent the fact that the operand
50 /// operators are independent of each other.
53 /// AssertSext, AssertZext - These nodes record if a register contains a
54 /// value that has already been zero or sign extended from a narrower type.
55 /// These nodes take two operands. The first is the node that has already
56 /// been extended, and the second is a value type node indicating the width
58 AssertSext, AssertZext,
60 /// Various leaf nodes.
61 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
63 GlobalAddress, GlobalTLSAddress, FrameIndex,
64 JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
66 /// The address of the GOT
69 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
70 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
71 /// of the frame or return address to return. An index of zero corresponds
72 /// to the current function's frame or return address, an index of one to
73 /// the parent's frame or return address, and so on.
74 FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY,
76 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
77 /// Materializes the offset from the local object pointer of another
78 /// function to a particular local object passed to llvm.localescape. The
79 /// operand is the MCSymbol label used to represent this offset, since
80 /// typically the offset is not known until after code generation of the
84 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
85 /// the DAG, which implements the named register global variables extension.
89 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
90 /// first (possible) on-stack argument. This is needed for correct stack
91 /// adjustment during unwind.
94 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
95 /// Frame Address (CFA), generally the value of the stack pointer at the
96 /// call site in the previous frame.
99 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
100 /// 'eh_return' gcc dwarf builtin, which is used to return from
101 /// exception. The general meaning is: adjust stack by OFFSET and pass
102 /// execution to HANDLER. Many platform-related details also :)
105 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
106 /// This corresponds to the eh.sjlj.setjmp intrinsic.
107 /// It takes an input chain and a pointer to the jump buffer as inputs
108 /// and returns an outchain.
111 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
112 /// This corresponds to the eh.sjlj.longjmp intrinsic.
113 /// It takes an input chain and a pointer to the jump buffer as inputs
114 /// and returns an outchain.
117 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
118 /// The target initializes the dispatch table here.
119 EH_SJLJ_SETUP_DISPATCH,
121 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
122 /// simplification, or lowering of the constant. They are used for constants
123 /// which are known to fit in the immediate fields of their users, or for
124 /// carrying magic numbers which are not values which need to be
125 /// materialized in registers.
129 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
130 /// anything else with this node, and this is valid in the target-specific
131 /// dag, turning into a GlobalAddress operand.
133 TargetGlobalTLSAddress,
137 TargetExternalSymbol,
142 /// TargetIndex - Like a constant pool entry, but with completely
143 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
144 /// 64-bit index. Targets can use this however they like.
147 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
148 /// This node represents a target intrinsic function with no side effects.
149 /// The first operand is the ID number of the intrinsic from the
150 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
151 /// node returns the result of the intrinsic.
154 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
155 /// This node represents a target intrinsic function with side effects that
156 /// returns a result. The first operand is a chain pointer. The second is
157 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
158 /// operands to the intrinsic follow. The node has two results, the result
159 /// of the intrinsic and an output chain.
162 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
163 /// This node represents a target intrinsic function with side effects that
164 /// does not return a result. The first operand is a chain pointer. The
165 /// second is the ID number of the intrinsic from the llvm::Intrinsic
166 /// namespace. The operands to the intrinsic follow.
169 /// CopyToReg - This node has three operands: a chain, a register number to
170 /// set to this value, and a value.
173 /// CopyFromReg - This node indicates that the input value is a virtual or
174 /// physical register that is defined outside of the scope of this
175 /// SelectionDAG. The register is available from the RegisterSDNode object.
178 /// UNDEF - An undefined node.
181 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
182 /// a Constant, which is required to be operand #1) half of the integer or
183 /// float value specified as operand #0. This is only for use before
184 /// legalization, for values that will be broken into multiple registers.
187 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
188 /// Given two values of the same integer value type, this produces a value
189 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
190 /// legalization. The lower part of the composite value should be in
191 /// element 0 and the upper part should be in element 1.
194 /// MERGE_VALUES - This node takes multiple discrete operands and returns
195 /// them all as its individual results. This nodes has exactly the same
196 /// number of inputs and outputs. This node is useful for some pieces of the
197 /// code generator that want to think about a single node with multiple
198 /// results, not multiple nodes.
201 /// Simple integer binary arithmetic operators.
202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
204 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
205 /// a signed/unsigned value of type i[2*N], and return the full value as
206 /// two results, each of type iN.
207 SMUL_LOHI, UMUL_LOHI,
209 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
210 /// remainder result.
213 /// CARRY_FALSE - This node is used when folding other nodes,
214 /// like ADDC/SUBC, which indicate the carry result is always false.
217 /// Carry-setting nodes for multiple precision addition and subtraction.
218 /// These nodes take two operands of the same value type, and produce two
219 /// results. The first result is the normal add or sub result, the second
220 /// result is the carry flag result.
221 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
222 /// They are kept around for now to provide a smooth transition path
223 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
226 /// Carry-using nodes for multiple precision addition and subtraction. These
227 /// nodes take three operands: The first two are the normal lhs and rhs to
228 /// the add or sub, and the third is the input carry flag. These nodes
229 /// produce two results; the normal result of the add or sub, and the output
230 /// carry flag. These nodes both read and write a carry flag to allow them
231 /// to them to be chained together for add and sub of arbitrarily large
235 /// Carry-using nodes for multiple precision addition and subtraction.
236 /// These nodes take three operands: The first two are the normal lhs and
237 /// rhs to the add or sub, and the third is a boolean indicating if there
238 /// is an incoming carry. These nodes produce two results: the normal
239 /// result of the add or sub, and the output carry so they can be chained
240 /// together. The use of this opcode is preferable to adde/sube if the
241 /// target supports it, as the carry is a regular value rather than a
242 /// glue, which allows further optimisation.
245 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
246 /// These nodes take two operands: the normal LHS and RHS to the add. They
247 /// produce two results: the normal result of the add, and a boolean that
248 /// indicates if an overflow occurred (*not* a flag, because it may be store
249 /// to memory, etc.). If the type of the boolean is not i1 then the high
250 /// bits conform to getBooleanContents.
251 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
254 /// Same for subtraction.
257 /// Same for multiplication.
260 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
261 /// integers with the same bit width (W). If the true value of LHS + RHS
262 /// exceeds the largest value that can be represented by W bits, the
263 /// resulting value is this maximum value. Otherwise, if this value is less
264 /// than the smallest value that can be represented by W bits, the
265 /// resulting value is this minimum value.
268 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
269 /// integers with the same bit width (W). If the true value of LHS - RHS
270 /// exceeds the largest value that can be represented by W bits, the
271 /// resulting value is this maximum value. Otherwise, if this value is less
272 /// than the smallest value that can be represented by W bits, the
273 /// resulting value is this minimum value.
276 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on
277 /// 2 integers with the same width and scale. SCALE represents the scale of
278 /// both operands as fixed point numbers. This SCALE parameter must be a
279 /// constant integer. A scale of zero is effectively performing
280 /// multiplication on 2 integers.
283 /// Same as the corresponding unsaturated fixed point instructions, but the
284 /// result is clamped between the min and max values representable by the
285 /// bits of the first 2 operands.
286 SMULFIXSAT, UMULFIXSAT,
288 /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on
289 /// 2 integers with the same width and scale. SCALE represents the scale
290 /// of both operands as fixed point numbers. This SCALE parameter must be a
291 /// constant integer.
294 /// Simple binary floating point operators.
295 FADD, FSUB, FMUL, FDIV, FREM,
297 /// Constrained versions of the binary floating point operators.
298 /// These will be lowered to the simple operators before final selection.
299 /// They are used to limit optimizations while the DAG is being
301 STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
304 /// Constrained versions of libm-equivalent floating point intrinsics.
305 /// These will be lowered to the equivalent non-constrained pseudo-op
306 /// (or expanded to the equivalent library call) before final selection.
307 /// They are used to limit optimizations while the DAG is being optimized.
308 STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
309 STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
310 STRICT_FRINT, STRICT_FNEARBYINT, STRICT_FMAXNUM, STRICT_FMINNUM,
311 STRICT_FCEIL, STRICT_FFLOOR, STRICT_FROUND, STRICT_FTRUNC,
312 STRICT_LROUND, STRICT_LLROUND, STRICT_LRINT, STRICT_LLRINT,
313 STRICT_FMAXIMUM, STRICT_FMINIMUM,
315 /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or
316 /// unsigned integer. These have the same semantics as fptosi and fptoui
318 /// They are used to limit optimizations while the DAG is being optimized.
322 /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to
323 /// a floating point value. These have the same semantics as sitofp and
325 /// They are used to limit optimizations while the DAG is being optimized.
329 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
330 /// point type down to the precision of the destination VT. TRUNC is a
331 /// flag, which is always an integer that is zero or one. If TRUNC is 0,
332 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
333 /// change the value of Y.
335 /// The TRUNC = 1 case is used in cases where we know that the value will
336 /// not be modified by the node, because Y is not using any of the extra
337 /// precision of source type. This allows certain transformations like
338 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for
339 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't
341 /// It is used to limit optimizations while the DAG is being optimized.
344 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP
346 /// It is used to limit optimizations while the DAG is being optimized.
349 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used
350 /// for floating-point operands only. STRICT_FSETCC performs a quiet
351 /// comparison operation, while STRICT_FSETCCS performs a signaling
352 /// comparison operation.
353 STRICT_FSETCC, STRICT_FSETCCS,
355 /// FMA - Perform a * b + c with no intermediate rounding step.
358 /// FMAD - Perform a * b + c, while getting the same result as the
359 /// separately rounded operations.
362 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
363 /// DAG node does not require that X and Y have the same type, just that
364 /// they are both floating point. X and the result must have the same type.
365 /// FCOPYSIGN(f32, f64) is allowed.
368 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
369 /// value as an integer 0/1 value.
372 /// Returns platform specific canonical encoding of a floating point number.
375 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
376 /// specified, possibly variable, elements. The number of elements is
377 /// required to be a power of two. The types of the operands must all be
378 /// the same and must match the vector element type, except that integer
379 /// types are allowed to be larger than the element type, in which case
380 /// the operands are implicitly truncated.
383 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
384 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
385 /// element type then VAL is truncated before replacement.
388 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
389 /// identified by the (potentially variable) element number IDX. If the
390 /// return type is an integer type larger than the element type of the
391 /// vector, the result is extended to the width of the return type. In
392 /// that case, the high bits are undefined.
395 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
396 /// vector type with the same length and element type, this produces a
397 /// concatenated vector result value, with length equal to the sum of the
398 /// lengths of the input vectors.
401 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
402 /// with VECTOR2 inserted into VECTOR1 at the (potentially
403 /// variable) element number IDX, which must be a multiple of the
404 /// VECTOR2 vector length. The elements of VECTOR1 starting at
405 /// IDX are overwritten with VECTOR2. Elements IDX through
406 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
409 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
410 /// vector value) starting with the element number IDX, which must be a
411 /// constant multiple of the result vector length.
414 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
415 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
416 /// values that indicate which value (or undef) each result element will
417 /// get. These constant ints are accessible through the
418 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
419 /// 'vperm' instruction, except that the indices must be constants and are
420 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
423 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
424 /// scalar value into element 0 of the resultant vector type. The top
425 /// elements 1 to N-1 of the N-element vector are undefined. The type
426 /// of the operand must match the vector element type, except when they
427 /// are integer types. In this case the operand is allowed to be wider
428 /// than the vector element type, and is implicitly truncated to it.
431 /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL
432 /// duplicated in all lanes. The type of the operand must match the vector
433 /// element type, except when they are integer types. In this case the
434 /// operand is allowed to be wider than the vector element type, and is
435 /// implicitly truncated to it.
438 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
439 /// producing an unsigned/signed value of type i[2*N], then return the top
443 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
445 SMIN, SMAX, UMIN, UMAX,
447 /// Bitwise operators - logical and, logical or, logical xor.
450 /// ABS - Determine the unsigned absolute value of a signed integer value of
451 /// the same bitwidth.
452 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
456 /// Shift and rotation operations. After legalization, the type of the
457 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
458 /// the shift amount can be any type, but care must be taken to ensure it is
459 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
460 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
461 /// to represent the shift amount.
462 /// When the 1st operand is a vector, the shift amount must be in the same
463 /// type. (TLI.getShiftAmountTy() will return the same type when the input
464 /// type is a vector.)
465 /// For rotates and funnel shifts, the shift amount is treated as an unsigned
466 /// amount modulo the element size of the first operand.
468 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
469 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
470 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR,
473 /// Byte Swap and Counting operators.
474 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
476 /// Bit counting operators with an undefined result for zero inputs.
477 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
479 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
480 /// i1 then the high bits must conform to getBooleanContents.
483 /// Select with a vector condition (op #0) and two vector operands (ops #1
484 /// and #2), returning a vector result. All vectors have the same length.
485 /// Much like the scalar select and setcc, each bit in the condition selects
486 /// whether the corresponding result element is taken from op #1 or op #2.
487 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
488 /// change the condition type in order to match the VSELECT node using a
489 /// pattern. The condition follows the BooleanContent format of the target.
492 /// Select with condition operator - This selects between a true value and
493 /// a false value (ops #2 and #3) based on the boolean result of comparing
494 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
495 /// condition code in op #4, a CondCodeSDNode.
498 /// SetCC operator - This evaluates to a true value iff the condition is
499 /// true. If the result value type is not i1 then the high bits conform
500 /// to getBooleanContents. The operands to this are the left and right
501 /// operands to compare (ops #0, and #1) and the condition code to compare
502 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
503 /// then the result type must also be a vector type.
506 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
507 /// op #2 is a boolean indicating if there is an incoming carry. This
508 /// operator checks the result of "LHS - RHS - Carry", and can be used to
509 /// compare two wide integers:
510 /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
511 /// Only valid for integers.
514 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
515 /// integer shift operations. The operation ordering is:
516 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
517 SHL_PARTS, SRA_PARTS, SRL_PARTS,
519 /// Conversion operators. These are all single input single output
520 /// operations. For all of these, the result type must be strictly
521 /// wider or narrower (depending on the operation) than the source
524 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
528 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
531 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
534 /// TRUNCATE - Completely drop the high bits.
537 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
538 /// depends on the first letter) to floating point.
542 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
543 /// sign extend a small value in a large integer register (e.g. sign
544 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
545 /// with the 7th bit). The size of the smaller type is indicated by the 1th
546 /// operand, a ValueType node.
549 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
550 /// in-register any-extension of the low lanes of an integer vector. The
551 /// result type must have fewer elements than the operand type, and those
552 /// elements must be larger integer types such that the total size of the
553 /// operand type is less than or equal to the size of the result type. Each
554 /// of the low operand elements is any-extended into the corresponding,
555 /// wider result elements with the high bits becoming undef.
556 /// NOTE: The type legalizer prefers to make the operand and result size
557 /// the same to allow expansion to shuffle vector during op legalization.
558 ANY_EXTEND_VECTOR_INREG,
560 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
561 /// in-register sign-extension of the low lanes of an integer vector. The
562 /// result type must have fewer elements than the operand type, and those
563 /// elements must be larger integer types such that the total size of the
564 /// operand type is less than or equal to the size of the result type. Each
565 /// of the low operand elements is sign-extended into the corresponding,
566 /// wider result elements.
567 /// NOTE: The type legalizer prefers to make the operand and result size
568 /// the same to allow expansion to shuffle vector during op legalization.
569 SIGN_EXTEND_VECTOR_INREG,
571 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
572 /// in-register zero-extension of the low lanes of an integer vector. The
573 /// result type must have fewer elements than the operand type, and those
574 /// elements must be larger integer types such that the total size of the
575 /// operand type is less than or equal to the size of the result type. Each
576 /// of the low operand elements is zero-extended into the corresponding,
577 /// wider result elements.
578 /// NOTE: The type legalizer prefers to make the operand and result size
579 /// the same to allow expansion to shuffle vector during op legalization.
580 ZERO_EXTEND_VECTOR_INREG,
582 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
583 /// integer. These have the same semantics as fptosi and fptoui in IR. If
584 /// the FP value cannot fit in the integer type, the results are undefined.
588 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
589 /// down to the precision of the destination VT. TRUNC is a flag, which is
590 /// always an integer that is zero or one. If TRUNC is 0, this is a
591 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
594 /// The TRUNC = 1 case is used in cases where we know that the value will
595 /// not be modified by the node, because Y is not using any of the extra
596 /// precision of source type. This allows certain transformations like
597 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
598 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
601 /// FLT_ROUNDS_ - Returns current rounding mode:
604 /// 1 Round to nearest
609 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
612 /// BITCAST - This operator converts between integer, vector and FP
613 /// values, as if the value was stored to memory with one type and loaded
614 /// from the same address with the other type (or equivalently for vector
615 /// format conversions, etc). The source and result are required to have
616 /// the same bit size (e.g. f32 <-> i32). This can also be used for
617 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
620 /// This operator is subtly different from the bitcast instruction from
621 /// LLVM-IR since this node may change the bits in the register. For
622 /// example, this occurs on big-endian NEON and big-endian MSA where the
623 /// layout of the bits in the register depends on the vector type and this
624 /// operator acts as a shuffle operation for some vector type combinations.
627 /// ADDRSPACECAST - This operator converts between pointers of different
631 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
632 /// and truncation for half-precision (16 bit) floating numbers. These nodes
633 /// form a semi-softened interface for dealing with f16 (as an i16), which
634 /// is often a storage-only type but has native conversions.
635 FP16_TO_FP, FP_TO_FP16,
637 /// Perform various unary floating-point operations inspired by libm. For
638 /// FPOWI, the result is undefined if if the integer operand doesn't fit
640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW,
641 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
642 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
643 LROUND, LLROUND, LRINT, LLRINT,
645 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
648 /// In the case where a single input is a NaN (either signaling or quiet),
649 /// the non-NaN input is returned.
651 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
654 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
655 /// two values, following the IEEE-754 2008 definition. This differs from
656 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
657 /// signaling NaN, returns a quiet NaN.
658 FMINNUM_IEEE, FMAXNUM_IEEE,
660 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
661 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
662 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
665 /// FSINCOS - Compute both fsin and fcos as a single operation.
668 /// LOAD and STORE have token chains as their first operand, then the same
669 /// operands as an LLVM load/store instruction, then an offset node that
670 /// is added / subtracted from the base pointer to form the address (for
671 /// indexed memory ops).
674 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
675 /// to a specified boundary. This node always has two return values: a new
676 /// stack pointer value and a chain. The first operand is the token chain,
677 /// the second is the number of bytes to allocate, and the third is the
678 /// alignment boundary. The size is guaranteed to be a multiple of the
679 /// stack alignment, and the alignment is guaranteed to be bigger than the
680 /// stack alignment (if required) or 0 to get standard stack alignment.
683 /// Control flow instructions. These all have token chains.
685 /// BR - Unconditional branch. The first operand is the chain
686 /// operand, the second is the MBB to branch to.
689 /// BRIND - Indirect branch. The first operand is the chain, the second
690 /// is the value to branch to, which must be of the same type as the
691 /// target's pointer type.
694 /// BR_JT - Jumptable branch. The first operand is the chain, the second
695 /// is the jumptable index, the last one is the jumptable entry index.
698 /// BRCOND - Conditional branch. The first operand is the chain, the
699 /// second is the condition, the third is the block to branch to if the
700 /// condition is true. If the type of the condition is not i1, then the
701 /// high bits must conform to getBooleanContents.
704 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
705 /// that the condition is represented as condition code, and two nodes to
706 /// compare, rather than as a combined SetCC node. The operands in order
707 /// are chain, cc, lhs, rhs, block to branch to if condition is true.
710 /// INLINEASM - Represents an inline asm block. This node always has two
711 /// return values: a chain and a flag result. The inputs are as follows:
712 /// Operand #0 : Input chain.
713 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
714 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
715 /// Operand #3 : HasSideEffect, IsAlignStack bits.
716 /// After this, it is followed by a list of operands with this format:
717 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
718 /// of operands that follow, etc. See InlineAsm.h.
719 /// ... however many operands ...
720 /// Operand #last: Optional, an incoming flag.
722 /// The variable width operands are required to represent target addressing
723 /// modes as a single "operand", even though they may have multiple
727 /// INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
730 /// EH_LABEL - Represents a label in mid basic block used to track
731 /// locations needed for debug and exception handling tables. These nodes
732 /// take a chain as input and return a chain.
735 /// ANNOTATION_LABEL - Represents a mid basic block label used by
736 /// annotations. This should remain within the basic block and be ordered
737 /// with respect to other call instructions, but loads and stores may float
741 /// CATCHPAD - Represents a catchpad instruction.
744 /// CATCHRET - Represents a return from a catch block funclet. Used for
745 /// MSVC compatible exception handling. Takes a chain operand and a
746 /// destination basic block operand.
749 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
750 /// MSVC compatible exception handling. Takes only a chain operand.
753 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
754 /// value, the same type as the pointer type for the system, and an output
758 /// STACKRESTORE has two operands, an input chain and a pointer to restore
759 /// to it returns an output chain.
762 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
763 /// of a call sequence, and carry arbitrary information that target might
764 /// want to know. The first operand is a chain, the rest are specified by
765 /// the target and not touched by the DAG optimizers.
766 /// Targets that may use stack to pass call arguments define additional
768 /// - size of the call frame part that must be set up within the
769 /// CALLSEQ_START..CALLSEQ_END pair,
770 /// - part of the call frame prepared prior to CALLSEQ_START.
771 /// Both these parameters must be constants, their sum is the total call
773 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
774 CALLSEQ_START, // Beginning of a call sequence
775 CALLSEQ_END, // End of a call sequence
777 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
778 /// and the alignment. It returns a pair of values: the vaarg value and a
782 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
783 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
787 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
788 /// pointer, and a SRCVALUE.
791 /// SRCVALUE - This is a node type that holds a Value* that is used to
792 /// make reference to a value in the LLVM IR.
795 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
796 /// reference metadata in the IR.
799 /// PCMARKER - This corresponds to the pcmarker intrinsic.
802 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
803 /// It produces a chain and one i64 value. The only operand is a chain.
804 /// If i64 is not legal, the result will be expanded into smaller values.
805 /// Still, it returns an i64, so targets should set legality for i64.
806 /// The result is the content of the architecture-specific cycle
807 /// counter-like register (or other high accuracy low latency clock source).
810 /// HANDLENODE node - Used as a handle for various purposes.
813 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
814 /// takes as input a token chain, the pointer to the trampoline, the pointer
815 /// to the nested function, the pointer to pass for the 'nest' parameter, a
816 /// SRCVALUE for the trampoline and another for the nested function
817 /// (allowing targets to access the original Function*).
818 /// It produces a token chain as output.
821 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
822 /// It takes a pointer to the trampoline and produces a (possibly) new
823 /// pointer to the same trampoline with platform-specific adjustments
824 /// applied. The pointer it returns points to an executable block of code.
827 /// TRAP - Trapping instruction
830 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
833 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
834 /// is the chain. The other operands are the address to prefetch,
835 /// read / write specifier, locality specifier and instruction / data cache
839 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
840 /// This corresponds to the fence instruction. It takes an input chain, and
841 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
844 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
845 /// This corresponds to "load atomic" instruction.
848 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
849 /// This corresponds to "store atomic" instruction.
852 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
853 /// For double-word atomic operations:
854 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
856 /// This corresponds to the cmpxchg instruction.
859 /// Val, Success, OUTCHAIN
860 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
861 /// N.b. this is still a strong cmpxchg operation, so
862 /// Success == "Val == cmp".
863 ATOMIC_CMP_SWAP_WITH_SUCCESS,
865 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
866 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
867 /// For double-word atomic operations:
868 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
869 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
870 /// These correspond to the atomicrmw instruction.
886 // Masked load and store - consecutive vector load and store operations
887 // with additional mask operand that prevents memory accesses to the
890 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
891 // OutChain = MSTORE(Value, BasePtr, Mask)
894 // Masked gather and scatter - load and store operations for a vector of
895 // random addresses with additional mask operand that prevents memory
896 // accesses to the masked-off lanes.
898 // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
899 // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
901 // The Index operand can have more vector elements than the other operands
902 // due to type legalization. The extra elements are ignored.
905 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
906 /// is the chain and the second operand is the alloca pointer.
907 LIFETIME_START, LIFETIME_END,
909 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
910 /// beginning and end of GC transition sequence, and carry arbitrary
911 /// information that target might need for lowering. The first operand is
912 /// a chain, the rest are specified by the target and not touched by the DAG
913 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
918 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
919 /// the most recent dynamic alloca. For most targets that would be 0, but
920 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
921 /// known nonzero constant. The only operand here is the chain.
922 GET_DYNAMIC_AREA_OFFSET,
924 /// Generic reduction nodes. These nodes represent horizontal vector
925 /// reduction operations, producing a scalar result.
926 /// The STRICT variants perform reductions in sequential order. The first
927 /// operand is an initial scalar accumulator value, and the second operand
928 /// is the vector to reduce.
929 VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
930 /// These reductions are non-strict, and have a single vector operand.
931 VECREDUCE_FADD, VECREDUCE_FMUL,
932 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
933 VECREDUCE_FMAX, VECREDUCE_FMIN,
934 /// Integer reductions may have a result type larger than the vector element
935 /// type. However, the reduction is performed using the vector element type
936 /// and the value in the top bits is unspecified.
937 VECREDUCE_ADD, VECREDUCE_MUL,
938 VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
941 /// BUILTIN_OP_END - This must be the last enum value in this list.
942 /// The target-specific pre-isel opcode values start here.
946 /// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
947 /// which cannot raise FP exceptions should be less than this value.
948 /// Those that do must not be less than this value.
949 static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END+400;
951 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
952 /// which do not reference a specific memory location should be less than
953 /// this value. Those that do must not be less than this value, and can
954 /// be used with SelectionDAG::getMemIntrinsicNode.
955 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+500;
957 //===--------------------------------------------------------------------===//
958 /// MemIndexedMode enum - This enum defines the load / store indexed
959 /// addressing modes.
961 /// UNINDEXED "Normal" load / store. The effective address is already
962 /// computed and is available in the base pointer. The offset
963 /// operand is always undefined. In addition to producing a
964 /// chain, an unindexed load produces one value (result of the
965 /// load); an unindexed store does not produce a value.
967 /// PRE_INC Similar to the unindexed mode where the effective address is
968 /// PRE_DEC the value of the base pointer add / subtract the offset.
969 /// It considers the computation as being folded into the load /
970 /// store operation (i.e. the load / store does the address
971 /// computation as well as performing the memory transaction).
972 /// The base operand is always undefined. In addition to
973 /// producing a chain, pre-indexed load produces two values
974 /// (result of the load and the result of the address
975 /// computation); a pre-indexed store produces one value (result
976 /// of the address computation).
978 /// POST_INC The effective address is the value of the base pointer. The
979 /// POST_DEC value of the offset operand is then added to / subtracted
980 /// from the base after memory transaction. In addition to
981 /// producing a chain, post-indexed load produces two values
982 /// (the result of the load and the result of the base +/- offset
983 /// computation); a post-indexed store produces one value (the
984 /// the result of the base +/- offset computation).
985 enum MemIndexedMode {
993 static const int LAST_INDEXED_MODE = POST_DEC + 1;
995 //===--------------------------------------------------------------------===//
996 /// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
997 /// index parameter when calculating addresses.
999 /// SIGNED_SCALED Addr = Base + ((signed)Index * sizeof(element))
1000 /// SIGNED_UNSCALED Addr = Base + (signed)Index
1001 /// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * sizeof(element))
1002 /// UNSIGNED_UNSCALED Addr = Base + (unsigned)Index
1010 static const int LAST_MEM_INDEX_TYPE = UNSIGNED_UNSCALED + 1;
1012 //===--------------------------------------------------------------------===//
1013 /// LoadExtType enum - This enum defines the three variants of LOADEXT
1014 /// (load with extension).
1016 /// SEXTLOAD loads the integer operand and sign extends it to a larger
1017 /// integer result type.
1018 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
1019 /// integer result type.
1020 /// EXTLOAD is used for two things: floating point extending loads and
1021 /// integer extending loads [the top bits are undefined].
1029 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
1031 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
1033 //===--------------------------------------------------------------------===//
1034 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1035 /// below work out, when considering SETFALSE (something that never exists
1036 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
1037 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
1038 /// to. If the "N" column is 1, the result of the comparison is undefined if
1039 /// the input is a NAN.
1041 /// All of these (except for the 'always folded ops') should be handled for
1042 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1043 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1045 /// Note that these are laid out in a specific order to allow bit-twiddling
1046 /// to transform conditions.
1048 // Opcode N U L G E Intuitive operation
1049 SETFALSE, // 0 0 0 0 Always false (always folded)
1050 SETOEQ, // 0 0 0 1 True if ordered and equal
1051 SETOGT, // 0 0 1 0 True if ordered and greater than
1052 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
1053 SETOLT, // 0 1 0 0 True if ordered and less than
1054 SETOLE, // 0 1 0 1 True if ordered and less than or equal
1055 SETONE, // 0 1 1 0 True if ordered and operands are unequal
1056 SETO, // 0 1 1 1 True if ordered (no nans)
1057 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
1058 SETUEQ, // 1 0 0 1 True if unordered or equal
1059 SETUGT, // 1 0 1 0 True if unordered or greater than
1060 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
1061 SETULT, // 1 1 0 0 True if unordered or less than
1062 SETULE, // 1 1 0 1 True if unordered, less than, or equal
1063 SETUNE, // 1 1 1 0 True if unordered or not equal
1064 SETTRUE, // 1 1 1 1 Always true (always folded)
1065 // Don't care operations: undefined if the input is a nan.
1066 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
1067 SETEQ, // 1 X 0 0 1 True if equal
1068 SETGT, // 1 X 0 1 0 True if greater than
1069 SETGE, // 1 X 0 1 1 True if greater than or equal
1070 SETLT, // 1 X 1 0 0 True if less than
1071 SETLE, // 1 X 1 0 1 True if less than or equal
1072 SETNE, // 1 X 1 1 0 True if not equal
1073 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
1075 SETCC_INVALID // Marker value.
1078 /// Return true if this is a setcc instruction that performs a signed
1079 /// comparison when used with integer operands.
1080 inline bool isSignedIntSetCC(CondCode Code) {
1081 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
1084 /// Return true if this is a setcc instruction that performs an unsigned
1085 /// comparison when used with integer operands.
1086 inline bool isUnsignedIntSetCC(CondCode Code) {
1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
1090 /// Return true if the specified condition returns true if the two operands to
1091 /// the condition are equal. Note that if one of the two operands is a NaN,
1092 /// this value is meaningless.
1093 inline bool isTrueWhenEqual(CondCode Cond) {
1094 return ((int)Cond & 1) != 0;
1097 /// This function returns 0 if the condition is always false if an operand is
1098 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1099 /// the condition is undefined if the operand is a NaN.
1100 inline unsigned getUnorderedFlavor(CondCode Cond) {
1101 return ((int)Cond >> 3) & 3;
1104 /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1105 /// SetCC operation.
1106 CondCode getSetCCInverse(CondCode Operation, EVT Type);
1108 namespace GlobalISel {
1109 /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1110 /// SetCC operation. The U bit of the condition code has different meanings
1111 /// between floating point and integer comparisons and LLT's don't provide
1112 /// this distinction. As such we need to be told whether the comparison is
1113 /// floating point or integer-like. Pointers should use integer-like
1115 CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike);
1116 } // end namespace GlobalISel
1118 /// Return the operation corresponding to (Y op X) when given the operation
1120 CondCode getSetCCSwappedOperands(CondCode Operation);
1122 /// Return the result of a logical OR between different comparisons of
1123 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1124 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1125 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type);
1127 /// Return the result of a logical AND between different comparisons of
1128 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1129 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1130 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type);
1132 } // end llvm::ISD namespace
1134 } // end llvm namespace