1 //===- LiveIntervals.h - Live Interval Analysis -----------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// \file This file implements the LiveInterval analysis pass. Given some
10 /// numbering of each the machine instructions (in this implemention depth-first
11 /// order) an interval [i, j) is said to be a live interval for register v if
12 /// there is no instruction with number j' > j such that v is live at j' and
13 /// there is no instruction with number i' < i such that v is live at i'. In
14 /// this implementation intervals can have holes, i.e. an interval might look
15 /// like [1,20), [50,65), [1000,1001).
17 //===----------------------------------------------------------------------===//
19 #ifndef LLVM_CODEGEN_LIVEINTERVALS_H
20 #define LLVM_CODEGEN_LIVEINTERVALS_H
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/SlotIndexes.h"
29 #include "llvm/CodeGen/TargetRegisterInfo.h"
30 #include "llvm/MC/LaneBitmask.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/ErrorHandling.h"
40 extern cl::opt<bool> UseSegmentSetForPhysRegs;
44 class LiveIntervalCalc;
45 class MachineBlockFrequencyInfo;
46 class MachineDominatorTree;
47 class MachineFunction;
49 class MachineRegisterInfo;
51 class TargetInstrInfo;
54 class LiveIntervals : public MachineFunctionPass {
56 MachineRegisterInfo* MRI;
57 const TargetRegisterInfo* TRI;
58 const TargetInstrInfo* TII;
61 MachineDominatorTree *DomTree = nullptr;
62 LiveIntervalCalc *LICalc = nullptr;
64 /// Special pool allocator for VNInfo's (LiveInterval val#).
65 VNInfo::Allocator VNInfoAllocator;
67 /// Live interval pointers for all the virtual registers.
68 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
70 /// Sorted list of instructions with register mask operands. Always use the
71 /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
72 SmallVector<SlotIndex, 8> RegMaskSlots;
74 /// This vector is parallel to RegMaskSlots, it holds a pointer to the
75 /// corresponding register mask. This pointer can be recomputed as:
77 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
78 /// unsigned OpNum = findRegMaskOperand(MI);
79 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
81 /// This is kept in a separate vector partly because some standard
82 /// libraries don't support lower_bound() with mixed objects, partly to
83 /// improve locality when searching in RegMaskSlots.
84 /// Also see the comment in LiveInterval::find().
85 SmallVector<const uint32_t*, 8> RegMaskBits;
87 /// For each basic block number, keep (begin, size) pairs indexing into the
88 /// RegMaskSlots and RegMaskBits arrays.
89 /// Note that basic block numbers may not be layout contiguous, that's why
90 /// we can't just keep track of the first register mask in each basic
92 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
94 /// Keeps a live range set for each register unit to track fixed physreg
96 SmallVector<LiveRange*, 0> RegUnitRanges;
102 ~LiveIntervals() override;
104 /// Calculate the spill weight to assign to a single instruction.
105 static float getSpillWeight(bool isDef, bool isUse,
106 const MachineBlockFrequencyInfo *MBFI,
107 const MachineInstr &MI);
109 /// Calculate the spill weight to assign to a single instruction.
110 static float getSpillWeight(bool isDef, bool isUse,
111 const MachineBlockFrequencyInfo *MBFI,
112 const MachineBasicBlock *MBB);
114 LiveInterval &getInterval(Register Reg) {
115 if (hasInterval(Reg))
116 return *VirtRegIntervals[Reg.id()];
118 return createAndComputeVirtRegInterval(Reg);
121 const LiveInterval &getInterval(Register Reg) const {
122 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
125 bool hasInterval(Register Reg) const {
126 return VirtRegIntervals.inBounds(Reg.id()) &&
127 VirtRegIntervals[Reg.id()];
130 /// Interval creation.
131 LiveInterval &createEmptyInterval(Register Reg) {
132 assert(!hasInterval(Reg) && "Interval already exists!");
133 VirtRegIntervals.grow(Reg.id());
134 VirtRegIntervals[Reg.id()] = createInterval(Reg);
135 return *VirtRegIntervals[Reg.id()];
138 LiveInterval &createAndComputeVirtRegInterval(Register Reg) {
139 LiveInterval &LI = createEmptyInterval(Reg);
140 computeVirtRegInterval(LI);
144 /// Interval removal.
145 void removeInterval(unsigned Reg) {
146 delete VirtRegIntervals[Reg];
147 VirtRegIntervals[Reg] = nullptr;
150 /// Given a register and an instruction, adds a live segment from that
151 /// instruction to the end of its MBB.
152 LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
153 MachineInstr &startInst);
155 /// After removing some uses of a register, shrink its live range to just
156 /// the remaining uses. This method does not compute reaching defs for new
157 /// uses, and it doesn't remove dead defs.
158 /// Dead PHIDef values are marked as unused. New dead machine instructions
159 /// are added to the dead vector. Returns true if the interval may have been
160 /// separated into multiple connected components.
161 bool shrinkToUses(LiveInterval *li,
162 SmallVectorImpl<MachineInstr*> *dead = nullptr);
164 /// Specialized version of
165 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
166 /// that works on a subregister live range and only looks at uses matching
167 /// the lane mask of the subregister range.
168 /// This may leave the subrange empty which needs to be cleaned up with
169 /// LiveInterval::removeEmptySubranges() afterwards.
170 void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
172 /// Extend the live range \p LR to reach all points in \p Indices. The
173 /// points in the \p Indices array must be jointly dominated by the union
174 /// of the existing defs in \p LR and points in \p Undefs.
176 /// PHI-defs are added as needed to maintain SSA form.
178 /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
179 /// will be extended to be live out of the basic block.
180 /// If a SlotIndex in \p Indices is jointy dominated only by points in
181 /// \p Undefs, the live range will not be extended to that point.
183 /// See also LiveRangeCalc::extend().
184 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
185 ArrayRef<SlotIndex> Undefs);
187 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) {
188 extendToIndices(LR, Indices, /*Undefs=*/{});
191 /// If \p LR has a live value at \p Kill, prune its live range by removing
192 /// any liveness reachable from Kill. Add live range end points to
193 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
194 /// value's live range.
196 /// Calling pruneValue() and extendToIndices() can be used to reconstruct
197 /// SSA form after adding defs to a virtual register.
198 void pruneValue(LiveRange &LR, SlotIndex Kill,
199 SmallVectorImpl<SlotIndex> *EndPoints);
201 /// This function should not be used. Its intent is to tell you that you are
202 /// doing something wrong if you call pruneValue directly on a
203 /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
204 /// LiveRange and all the LiveRanges of the subranges if any.
205 LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex,
206 SmallVectorImpl<SlotIndex> *) {
208 "Use pruneValue on the main LiveRange and on each subrange");
211 SlotIndexes *getSlotIndexes() const {
215 AAResults *getAliasAnalysis() const {
219 /// Returns true if the specified machine instr has been removed or was
220 /// never entered in the map.
221 bool isNotInMIMap(const MachineInstr &Instr) const {
222 return !Indexes->hasIndex(Instr);
225 /// Returns the base index of the given instruction.
226 SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
227 return Indexes->getInstructionIndex(Instr);
230 /// Returns the instruction associated with the given index.
231 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
232 return Indexes->getInstructionFromIndex(index);
235 /// Return the first index in the given basic block.
236 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
237 return Indexes->getMBBStartIdx(mbb);
240 /// Return the last index in the given basic block.
241 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
242 return Indexes->getMBBEndIdx(mbb);
245 bool isLiveInToMBB(const LiveRange &LR,
246 const MachineBasicBlock *mbb) const {
247 return LR.liveAt(getMBBStartIdx(mbb));
250 bool isLiveOutOfMBB(const LiveRange &LR,
251 const MachineBasicBlock *mbb) const {
252 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
255 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
256 return Indexes->getMBBFromIndex(index);
259 void insertMBBInMaps(MachineBasicBlock *MBB,
260 MachineInstr *InsertionPoint = nullptr) {
261 Indexes->insertMBBInMaps(MBB, InsertionPoint);
262 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
263 "Blocks must be added in order.");
264 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
267 SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
268 return Indexes->insertMachineInstrInMaps(MI);
271 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
272 MachineBasicBlock::iterator E) {
273 for (MachineBasicBlock::iterator I = B; I != E; ++I)
274 Indexes->insertMachineInstrInMaps(*I);
277 void RemoveMachineInstrFromMaps(MachineInstr &MI) {
278 Indexes->removeMachineInstrFromMaps(MI);
281 SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
282 return Indexes->replaceMachineInstrInMaps(MI, NewMI);
285 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
287 void getAnalysisUsage(AnalysisUsage &AU) const override;
288 void releaseMemory() override;
290 /// Pass entry point; Calculates LiveIntervals.
291 bool runOnMachineFunction(MachineFunction&) override;
293 /// Implement the dump method.
294 void print(raw_ostream &O, const Module* = nullptr) const override;
296 /// If LI is confined to a single basic block, return a pointer to that
297 /// block. If LI is live in to or out of any block, return NULL.
298 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
300 /// Returns true if VNI is killed by any PHI-def values in LI.
301 /// This may conservatively return true to avoid expensive computations.
302 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
304 /// Add kill flags to any instruction that kills a virtual register.
305 void addKillFlags(const VirtRegMap*);
307 /// Call this method to notify LiveIntervals that instruction \p MI has been
308 /// moved within a basic block. This will update the live intervals for all
309 /// operands of \p MI. Moves between basic blocks are not supported.
311 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
312 void handleMove(MachineInstr &MI, bool UpdateFlags = false);
314 /// Update intervals of operands of all instructions in the newly
315 /// created bundle specified by \p BundleStart.
317 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
319 /// Assumes existing liveness is accurate.
320 /// \pre BundleStart should be the first instruction in the Bundle.
321 /// \pre BundleStart should not have a have SlotIndex as one will be assigned.
322 void handleMoveIntoNewBundle(MachineInstr &BundleStart,
323 bool UpdateFlags = false);
325 /// Update live intervals for instructions in a range of iterators. It is
326 /// intended for use after target hooks that may insert or remove
327 /// instructions, and is only efficient for a small number of instructions.
329 /// OrigRegs is a vector of registers that were originally used by the
330 /// instructions in the range between the two iterators.
332 /// Currently, the only only changes that are supported are simple removal
333 /// and addition of uses.
334 void repairIntervalsInRange(MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator Begin,
336 MachineBasicBlock::iterator End,
337 ArrayRef<Register> OrigRegs);
339 // Register mask functions.
341 // Machine instructions may use a register mask operand to indicate that a
342 // large number of registers are clobbered by the instruction. This is
343 // typically used for calls.
345 // For compile time performance reasons, these clobbers are not recorded in
346 // the live intervals for individual physical registers. Instead,
347 // LiveIntervalAnalysis maintains a sorted list of instructions with
348 // register mask operands.
350 /// Returns a sorted array of slot indices of all instructions with
351 /// register mask operands.
352 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
354 /// Returns a sorted array of slot indices of all instructions with register
355 /// mask operands in the basic block numbered \p MBBNum.
356 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
357 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
358 return getRegMaskSlots().slice(P.first, P.second);
361 /// Returns an array of register mask pointers corresponding to
362 /// getRegMaskSlots().
363 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
365 /// Returns an array of mask pointers corresponding to
366 /// getRegMaskSlotsInBlock(MBBNum).
367 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
368 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
369 return getRegMaskBits().slice(P.first, P.second);
372 /// Test if \p LI is live across any register mask instructions, and
373 /// compute a bit mask of physical registers that are not clobbered by any
376 /// Returns false if \p LI doesn't cross any register mask instructions. In
377 /// that case, the bit vector is not filled in.
378 bool checkRegMaskInterference(LiveInterval &LI,
379 BitVector &UsableRegs);
381 // Register unit functions.
383 // Fixed interference occurs when MachineInstrs use physregs directly
384 // instead of virtual registers. This typically happens when passing
385 // arguments to a function call, or when instructions require operands in
388 // Each physreg has one or more register units, see MCRegisterInfo. We
389 // track liveness per register unit to handle aliasing registers more
392 /// Return the live range for register unit \p Unit. It will be computed if
393 /// it doesn't exist.
394 LiveRange &getRegUnit(unsigned Unit) {
395 LiveRange *LR = RegUnitRanges[Unit];
397 // Compute missing ranges on demand.
398 // Use segment set to speed-up initial computation of the live range.
399 RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
400 computeRegUnitRange(*LR, Unit);
405 /// Return the live range for register unit \p Unit if it has already been
406 /// computed, or nullptr if it hasn't been computed yet.
407 LiveRange *getCachedRegUnit(unsigned Unit) {
408 return RegUnitRanges[Unit];
411 const LiveRange *getCachedRegUnit(unsigned Unit) const {
412 return RegUnitRanges[Unit];
415 /// Remove computed live range for register unit \p Unit. Subsequent uses
416 /// should rely on on-demand recomputation.
417 void removeRegUnit(unsigned Unit) {
418 delete RegUnitRanges[Unit];
419 RegUnitRanges[Unit] = nullptr;
422 /// Remove associated live ranges for the register units associated with \p
423 /// Reg. Subsequent uses should rely on on-demand recomputation. \note This
424 /// method can result in inconsistent liveness tracking if multiple phyical
425 /// registers share a regunit, and should be used cautiously.
426 void removeAllRegUnitsForPhysReg(unsigned Reg) {
427 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
428 removeRegUnit(*Units);
431 /// Remove value numbers and related live segments starting at position
432 /// \p Pos that are part of any liverange of physical register \p Reg or one
433 /// of its subregisters.
434 void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
436 /// Remove value number and related live segments of \p LI and its subranges
437 /// that start at position \p Pos.
438 void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
440 /// Split separate components in LiveInterval \p LI into separate intervals.
441 void splitSeparateComponents(LiveInterval &LI,
442 SmallVectorImpl<LiveInterval*> &SplitLIs);
444 /// For live interval \p LI with correct SubRanges construct matching
445 /// information for the main live range. Expects the main live range to not
446 /// have any segments or value numbers.
447 void constructMainRangeFromSubranges(LiveInterval &LI);
450 /// Compute live intervals for all virtual registers.
451 void computeVirtRegs();
453 /// Compute RegMaskSlots and RegMaskBits.
454 void computeRegMasks();
456 /// Walk the values in \p LI and check for dead values:
457 /// - Dead PHIDef values are marked as unused.
458 /// - Dead operands are marked as such.
459 /// - Completely dead machine instructions are added to the \p dead vector
460 /// if it is not nullptr.
461 /// Returns true if any PHI value numbers have been removed which may
462 /// have separated the interval into multiple connected components.
463 bool computeDeadValues(LiveInterval &LI,
464 SmallVectorImpl<MachineInstr*> *dead);
466 static LiveInterval* createInterval(unsigned Reg);
468 void printInstrs(raw_ostream &O) const;
469 void dumpInstrs() const;
471 void computeLiveInRegUnits();
472 void computeRegUnitRange(LiveRange&, unsigned Unit);
473 bool computeVirtRegInterval(LiveInterval&);
475 using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
476 void extendSegmentsToUses(LiveRange &Segments,
477 ShrinkToUsesWorkList &WorkList, unsigned Reg,
478 LaneBitmask LaneMask);
480 /// Helper function for repairIntervalsInRange(), walks backwards and
481 /// creates/modifies live segments in \p LR to match the operands found.
482 /// Only full operands or operands with subregisters matching \p LaneMask
484 void repairOldRegInRange(MachineBasicBlock::iterator Begin,
485 MachineBasicBlock::iterator End,
486 const SlotIndex endIdx, LiveRange &LR,
488 LaneBitmask LaneMask = LaneBitmask::getAll());
493 } // end namespace llvm