1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the LiveVariables analysis pass. For each machine
10 // instruction in the function, this pass calculates the set of registers that
11 // are immediately dead after the instruction (i.e., the instruction calculates
12 // the value, but it is never used) and the set of registers that are used by
13 // the instruction, but are never used after the instruction (i.e., they are
16 // This class computes live variables using a sparse implementation based on
17 // the machine code SSA form. This class computes live variable information for
18 // each virtual and _register allocatable_ physical register in a function. It
19 // uses the dominance properties of SSA form to efficiently compute live
20 // variables for virtual registers, and assumes that physical registers are only
21 // live within a single basic block (allowing it to do a single local analysis
22 // to resolve physical register lifetimes in each basic block). If a physical
23 // register is not register allocatable, it is not tracked. This is useful for
24 // things like the stack pointer and condition codes.
26 //===----------------------------------------------------------------------===//
28 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
29 #define LLVM_CODEGEN_LIVEVARIABLES_H
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/IndexedMap.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/ADT/SparseBitVector.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/InitializePasses.h"
43 class MachineBasicBlock;
44 class MachineRegisterInfo;
46 class LiveVariables : public MachineFunctionPass {
48 static char ID; // Pass identification, replacement for typeid
49 LiveVariables() : MachineFunctionPass(ID) {
50 initializeLiveVariablesPass(*PassRegistry::getPassRegistry());
53 /// VarInfo - This represents the regions where a virtual register is live in
54 /// the program. We represent this with three different pieces of
55 /// information: the set of blocks in which the instruction is live
56 /// throughout, the set of blocks in which the instruction is actually used,
57 /// and the set of non-phi instructions that are the last users of the value.
59 /// In the common case where a value is defined and killed in the same block,
60 /// There is one killing instruction, and AliveBlocks is empty.
62 /// Otherwise, the value is live out of the block. If the value is live
63 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
64 /// where the liveness range ends are not included in AliveBlocks, instead
65 /// being captured by the Kills set. In these blocks, the value is live into
66 /// the block (unless the value is defined and killed in the same block) and
67 /// lives until the specified instruction. Note that there cannot ever be a
68 /// value whose Kills set contains two instructions from the same basic block.
70 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
71 /// value in one of its predecessor blocks, it is not listed in the kills set,
72 /// but does include the predecessor block in the AliveBlocks set (unless that
73 /// block also defines the value). This leads to the (perfectly sensical)
74 /// situation where a value is defined in a block, and the last use is a phi
75 /// node in the successor. In this case, AliveBlocks is empty (the value is
76 /// not live across any blocks) and Kills is empty (phi nodes are not
77 /// included). This is sensical because the value must be live to the end of
78 /// the block, but is not live in any successor blocks.
80 /// AliveBlocks - Set of blocks in which this value is alive completely
81 /// through. This is a bit set which uses the basic block number as an
84 SparseBitVector<> AliveBlocks;
86 /// Kills - List of MachineInstruction's which are the last use of this
87 /// virtual register (kill it) in their basic block.
89 std::vector<MachineInstr*> Kills;
91 /// removeKill - Delete a kill corresponding to the specified
92 /// machine instruction. Returns true if there was a kill
93 /// corresponding to this instruction, false otherwise.
94 bool removeKill(MachineInstr &MI) {
95 std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
102 /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
103 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
105 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
106 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
107 /// MBB, it is not considered live in.
108 bool isLiveIn(const MachineBasicBlock &MBB,
110 MachineRegisterInfo &MRI);
116 /// VirtRegInfo - This list is a mapping from virtual register number to
117 /// variable information.
119 IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
121 /// PHIJoins - list of virtual registers that are PHI joins. These registers
122 /// may have multiple definitions, and they require special handling when
123 /// building live intervals.
124 SparseBitVector<> PHIJoins;
126 private: // Intermediate data structures
129 MachineRegisterInfo* MRI;
131 const TargetRegisterInfo *TRI;
133 // PhysRegInfo - Keep track of which instruction was the last def of a
134 // physical register. This is a purely local property, because all physical
135 // register references are presumed dead across basic blocks.
136 std::vector<MachineInstr *> PhysRegDef;
138 // PhysRegInfo - Keep track of which instruction was the last use of a
139 // physical register. This is a purely local property, because all physical
140 // register references are presumed dead across basic blocks.
141 std::vector<MachineInstr *> PhysRegUse;
143 std::vector<SmallVector<unsigned, 4>> PHIVarInfo;
145 // DistanceMap - Keep track the distance of a MI from the start of the
146 // current basic block.
147 DenseMap<MachineInstr*, unsigned> DistanceMap;
149 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
150 /// uses. Pay special attention to the sub-register uses which may come below
151 /// the last use of the whole register.
152 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
154 /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
155 void HandleRegMask(const MachineOperand&);
157 void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
158 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
159 SmallVectorImpl<unsigned> &Defs);
160 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
162 /// FindLastRefOrPartRef - Return the last reference or partial reference of
163 /// the specified register.
164 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
166 /// FindLastPartialDef - Return the last partial def of the specified
167 /// register. Also returns the sub-registers that're defined by the
169 MachineInstr *FindLastPartialDef(unsigned Reg,
170 SmallSet<unsigned,4> &PartDefRegs);
172 /// analyzePHINodes - Gather information about the PHI nodes in here. In
173 /// particular, we want to map the variable information of a virtual
174 /// register which is used in a PHI node. We map that to the BB the vreg
176 void analyzePHINodes(const MachineFunction& Fn);
178 void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
180 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
183 bool runOnMachineFunction(MachineFunction &MF) override;
185 /// RegisterDefIsDead - Return true if the specified instruction defines the
186 /// specified register, but that definition is dead.
187 bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const;
189 //===--------------------------------------------------------------------===//
190 // API to update live variable information
192 /// replaceKillInstruction - Update register kill info by replacing a kill
193 /// instruction with a new one.
194 void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
195 MachineInstr &NewMI);
197 /// addVirtualRegisterKilled - Add information about the fact that the
198 /// specified register is killed after being used by the specified
199 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
201 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI,
202 bool AddIfNotFound = false) {
203 if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
204 getVarInfo(IncomingReg).Kills.push_back(&MI);
207 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
208 /// register from the live variable information. Returns true if the
209 /// variable was marked as killed by the specified instruction,
211 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) {
212 if (!getVarInfo(reg).removeKill(MI))
215 bool Removed = false;
216 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
217 MachineOperand &MO = MI.getOperand(i);
218 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
225 assert(Removed && "Register is not used by this instruction!");
230 /// removeVirtualRegistersKilled - Remove all killed info for the specified
232 void removeVirtualRegistersKilled(MachineInstr &MI);
234 /// addVirtualRegisterDead - Add information about the fact that the specified
235 /// register is dead after being used by the specified instruction. If
236 /// AddIfNotFound is true, add a implicit operand if it's not found.
237 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI,
238 bool AddIfNotFound = false) {
239 if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
240 getVarInfo(IncomingReg).Kills.push_back(&MI);
243 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
244 /// register from the live variable information. Returns true if the
245 /// variable was marked dead at the specified instruction, false
247 bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) {
248 if (!getVarInfo(reg).removeKill(MI))
251 bool Removed = false;
252 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
253 MachineOperand &MO = MI.getOperand(i);
254 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
260 assert(Removed && "Register is not defined by this instruction!");
265 void getAnalysisUsage(AnalysisUsage &AU) const override;
267 void releaseMemory() override {
271 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
273 VarInfo &getVarInfo(unsigned RegIdx);
275 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
276 MachineBasicBlock *BB);
277 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
278 MachineBasicBlock *BB,
279 std::vector<MachineBasicBlock*> &WorkList);
280 void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
281 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);
283 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
284 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
287 /// isLiveOut - Determine if Reg is live out from MBB, when not considering
288 /// PHI nodes. This means that Reg is either killed by a successor block or
289 /// passed through one.
290 bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
292 /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
293 /// variables that are live out of DomBB and live into SuccBB will be marked
294 /// as passing live through BB. This method assumes that the machine code is
295 /// still in SSA form.
296 void addNewBlock(MachineBasicBlock *BB,
297 MachineBasicBlock *DomBB,
298 MachineBasicBlock *SuccBB);
300 /// isPHIJoin - Return true if Reg is a phi join register.
301 bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
303 /// setPHIJoin - Mark Reg as a phi join register.
304 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
307 } // End llvm namespace