1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
2 // combiner ------*- C++ -*-===//
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
10 // This file defines instruction pattern supported by combiner
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
19 /// These are instruction patterns matched by the machine combiner pass.
20 enum class MachineCombinerPattern {
21 // These are commutative variants for reassociating a computation chain. See
22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
28 // These are multiply-add patterns matched by the AArch64 machine combiner.
41 // NEON integers vectors
68 MULADDv4i16_indexed_OP1,
69 MULADDv4i16_indexed_OP2,
70 MULADDv8i16_indexed_OP1,
71 MULADDv8i16_indexed_OP2,
72 MULADDv2i32_indexed_OP1,
73 MULADDv2i32_indexed_OP2,
74 MULADDv4i32_indexed_OP1,
75 MULADDv4i32_indexed_OP2,
77 MULSUBv4i16_indexed_OP1,
78 MULSUBv4i16_indexed_OP2,
79 MULSUBv8i16_indexed_OP1,
80 MULSUBv8i16_indexed_OP2,
81 MULSUBv2i32_indexed_OP1,
82 MULSUBv2i32_indexed_OP2,
83 MULSUBv4i32_indexed_OP1,
84 MULSUBv4i32_indexed_OP2,
102 FMLAv1i32_indexed_OP1,
103 FMLAv1i32_indexed_OP2,
104 FMLAv1i64_indexed_OP1,
105 FMLAv1i64_indexed_OP2,
114 FMLAv4i16_indexed_OP1,
115 FMLAv4i16_indexed_OP2,
116 FMLAv8i16_indexed_OP1,
117 FMLAv8i16_indexed_OP2,
118 FMLAv2i32_indexed_OP1,
119 FMLAv2i32_indexed_OP2,
120 FMLAv2i64_indexed_OP1,
121 FMLAv2i64_indexed_OP2,
124 FMLAv4i32_indexed_OP1,
125 FMLAv4i32_indexed_OP2,
126 FMLSv1i32_indexed_OP2,
127 FMLSv1i64_indexed_OP2,
136 FMLSv4i16_indexed_OP1,
137 FMLSv4i16_indexed_OP2,
138 FMLSv8i16_indexed_OP1,
139 FMLSv8i16_indexed_OP2,
140 FMLSv2i32_indexed_OP1,
141 FMLSv2i32_indexed_OP2,
142 FMLSv2i64_indexed_OP1,
143 FMLSv2i64_indexed_OP2,
146 FMLSv4i32_indexed_OP1,
147 FMLSv4i32_indexed_OP2
150 } // end namespace llvm