contrib/llvm-project/llvm/include/llvm/CodeGen/MachineCombinerPattern.h

   1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
   2 // combiner  ------*- C++ -*-===//
   3 //
   4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   5 // See https://llvm.org/LICENSE.txt for license information.
   6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines instruction pattern supported by combiner
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
  15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
  16
  17 namespace llvm {
  18
  19 /// These are instruction patterns matched by the machine combiner pass.
  20 enum class MachineCombinerPattern {
  21   // These are commutative variants for reassociating a computation chain. See
  22   // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
  23   REASSOC_AX_BY,
  24   REASSOC_AX_YB,
  25   REASSOC_XA_BY,
  26   REASSOC_XA_YB,
  27
  28   // These are multiply-add patterns matched by the AArch64 machine combiner.
  29   MULADDW_OP1,
  30   MULADDW_OP2,
  31   MULSUBW_OP1,
  32   MULSUBW_OP2,
  33   MULADDWI_OP1,
  34   MULSUBWI_OP1,
  35   MULADDX_OP1,
  36   MULADDX_OP2,
  37   MULSUBX_OP1,
  38   MULSUBX_OP2,
  39   MULADDXI_OP1,
  40   MULSUBXI_OP1,
  41   // Floating Point
  42   FMULADDH_OP1,
  43   FMULADDH_OP2,
  44   FMULSUBH_OP1,
  45   FMULSUBH_OP2,
  46   FMULADDS_OP1,
  47   FMULADDS_OP2,
  48   FMULSUBS_OP1,
  49   FMULSUBS_OP2,
  50   FMULADDD_OP1,
  51   FMULADDD_OP2,
  52   FMULSUBD_OP1,
  53   FMULSUBD_OP2,
  54   FNMULSUBH_OP1,
  55   FNMULSUBS_OP1,
  56   FNMULSUBD_OP1,
  57   FMLAv1i32_indexed_OP1,
  58   FMLAv1i32_indexed_OP2,
  59   FMLAv1i64_indexed_OP1,
  60   FMLAv1i64_indexed_OP2,
  61   FMLAv4f16_OP1,
  62   FMLAv4f16_OP2,
  63   FMLAv8f16_OP1,
  64   FMLAv8f16_OP2,
  65   FMLAv2f32_OP2,
  66   FMLAv2f32_OP1,
  67   FMLAv2f64_OP1,
  68   FMLAv2f64_OP2,
  69   FMLAv4i16_indexed_OP1,
  70   FMLAv4i16_indexed_OP2,
  71   FMLAv8i16_indexed_OP1,
  72   FMLAv8i16_indexed_OP2,
  73   FMLAv2i32_indexed_OP1,
  74   FMLAv2i32_indexed_OP2,
  75   FMLAv2i64_indexed_OP1,
  76   FMLAv2i64_indexed_OP2,
  77   FMLAv4f32_OP1,
  78   FMLAv4f32_OP2,
  79   FMLAv4i32_indexed_OP1,
  80   FMLAv4i32_indexed_OP2,
  81   FMLSv1i32_indexed_OP2,
  82   FMLSv1i64_indexed_OP2,
  83   FMLSv4f16_OP1,
  84   FMLSv4f16_OP2,
  85   FMLSv8f16_OP1,
  86   FMLSv8f16_OP2,
  87   FMLSv2f32_OP1,
  88   FMLSv2f32_OP2,
  89   FMLSv2f64_OP1,
  90   FMLSv2f64_OP2,
  91   FMLSv4i16_indexed_OP1,
  92   FMLSv4i16_indexed_OP2,
  93   FMLSv8i16_indexed_OP1,
  94   FMLSv8i16_indexed_OP2,
  95   FMLSv2i32_indexed_OP1,
  96   FMLSv2i32_indexed_OP2,
  97   FMLSv2i64_indexed_OP1,
  98   FMLSv2i64_indexed_OP2,
  99   FMLSv4f32_OP1,
 100   FMLSv4f32_OP2,
 101   FMLSv4i32_indexed_OP1,
 102   FMLSv4i32_indexed_OP2
 103 };
 104
 105 } // end namespace llvm
 106
 107 #endif