1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the SelectionDAGISel class, which is used as the common
10 // base class for SelectionDAG-based instruction selectors.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class OptimizationRemarkEmitter;
34 class TargetLibraryInfo;
35 class FunctionLoweringInfo;
36 class ScheduleHazardRecognizer;
37 class SwiftErrorValueTracking;
39 class ScheduleDAGSDNodes;
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
44 class SelectionDAGISel : public MachineFunctionPass {
47 const TargetLibraryInfo *LibInfo;
48 FunctionLoweringInfo *FuncInfo;
49 SwiftErrorValueTracking *SwiftError;
51 MachineRegisterInfo *RegInfo;
53 SelectionDAGBuilder *SDB;
56 CodeGenOpt::Level OptLevel;
57 const TargetInstrInfo *TII;
58 const TargetLowering *TLI;
60 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
62 /// Current optimization remark emitter.
63 /// Used to report things like combines and FastISel failures.
64 std::unique_ptr<OptimizationRemarkEmitter> ORE;
68 explicit SelectionDAGISel(TargetMachine &tm,
69 CodeGenOpt::Level OL = CodeGenOpt::Default);
70 ~SelectionDAGISel() override;
72 const TargetLowering *getTargetLowering() const { return TLI; }
74 void getAnalysisUsage(AnalysisUsage &AU) const override;
76 bool runOnMachineFunction(MachineFunction &MF) override;
78 virtual void EmitFunctionEntryCode() {}
80 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
81 /// instruction selection starts.
82 virtual void PreprocessISelDAG() {}
84 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
85 /// right after selection.
86 virtual void PostprocessISelDAG() {}
88 /// Main hook for targets to transform nodes into machine nodes.
89 virtual void Select(SDNode *N) = 0;
91 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
92 /// addressing mode, according to the specified constraint. If this does
93 /// not match or is not implemented, return true. The resultant operands
94 /// (which will appear in the machine instruction) should be added to the
96 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
97 unsigned ConstraintID,
98 std::vector<SDValue> &OutOps) {
102 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
103 /// operand node N of U during instruction selection that starts at Root.
104 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
106 /// IsLegalToFold - Returns true if the specific operand node N of
107 /// U can be folded during instruction selection that starts at Root.
108 /// FIXME: This is a static member function because the MSP430/X86
109 /// targets, which uses it during isel. This could become a proper member.
110 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
111 CodeGenOpt::Level OptLevel,
112 bool IgnoreChains = false);
114 static void InvalidateNodeId(SDNode *N);
115 static int getUninvalidatedNodeId(SDNode *N);
117 static void EnforceNodeIdInvariant(SDNode *N);
119 // Opcodes used by the DAG state machine:
120 enum BuiltinOpcodes {
123 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
124 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
126 OPC_CaptureGlueInput,
128 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
129 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
132 OPC_CheckChild0Same, OPC_CheckChild1Same,
133 OPC_CheckChild2Same, OPC_CheckChild3Same,
134 OPC_CheckPatternPredicate,
136 OPC_CheckPredicateWithOperands,
142 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
143 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
144 OPC_CheckChild6Type, OPC_CheckChild7Type,
146 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
147 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
148 OPC_CheckCondCode, OPC_CheckChild2CondCode,
151 OPC_CheckAndImm, OPC_CheckOrImm,
152 OPC_CheckImmAllOnesV,
153 OPC_CheckImmAllZerosV,
154 OPC_CheckFoldableChainNode,
159 OPC_EmitConvertToTarget,
160 OPC_EmitMergeInputChains,
161 OPC_EmitMergeInputChains1_0,
162 OPC_EmitMergeInputChains1_1,
163 OPC_EmitMergeInputChains1_2,
167 // Space-optimized forms that implicitly encode number of result VTs.
168 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
170 // Space-optimized forms that implicitly encode number of result VTs.
171 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
173 // Contains offset in table for pattern being selected
178 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
179 OPFL_Chain = 1, // Node has a chain input.
180 OPFL_GlueInput = 2, // Node has a glue input.
181 OPFL_GlueOutput = 4, // Node has a glue output.
182 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
183 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
184 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
185 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
186 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
187 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
188 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
189 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
191 OPFL_VariadicInfo = OPFL_Variadic6
194 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
195 /// number of fixed arity values that should be skipped when copying from the
197 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
198 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
203 /// DAGSize - Size of DAG being instruction selected.
207 /// ReplaceUses - replace all uses of the old node F with the use
208 /// of the new node T.
209 void ReplaceUses(SDValue F, SDValue T) {
210 CurDAG->ReplaceAllUsesOfValueWith(F, T);
211 EnforceNodeIdInvariant(T.getNode());
214 /// ReplaceUses - replace all uses of the old nodes F with the use
215 /// of the new nodes T.
216 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
217 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
218 for (unsigned i = 0; i < Num; ++i)
219 EnforceNodeIdInvariant(T[i].getNode());
222 /// ReplaceUses - replace all uses of the old node F with the use
223 /// of the new node T.
224 void ReplaceUses(SDNode *F, SDNode *T) {
225 CurDAG->ReplaceAllUsesWith(F, T);
226 EnforceNodeIdInvariant(T);
229 /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
230 void ReplaceNode(SDNode *F, SDNode *T) {
231 CurDAG->ReplaceAllUsesWith(F, T);
232 EnforceNodeIdInvariant(T);
233 CurDAG->RemoveDeadNode(F);
236 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
237 /// by tblgen. Others should not call it.
238 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
241 /// getPatternForIndex - Patterns selected by tablegen during ISEL
242 virtual StringRef getPatternForIndex(unsigned index) {
243 llvm_unreachable("Tblgen should generate the implementation of this!");
246 /// getIncludePathForIndex - get the td source location of pattern instantiation
247 virtual StringRef getIncludePathForIndex(unsigned index) {
248 llvm_unreachable("Tblgen should generate the implementation of this!");
251 // Calls to these predicates are generated by tblgen.
252 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
253 int64_t DesiredMaskS) const;
254 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
255 int64_t DesiredMaskS) const;
258 /// CheckPatternPredicate - This function is generated by tblgen in the
259 /// target. It runs the specified pattern predicate and returns true if it
260 /// succeeds or false if it fails. The number is a private implementation
261 /// detail to the code tblgen produces.
262 virtual bool CheckPatternPredicate(unsigned PredNo) const {
263 llvm_unreachable("Tblgen should generate the implementation of this!");
266 /// CheckNodePredicate - This function is generated by tblgen in the target.
267 /// It runs node predicate number PredNo and returns true if it succeeds or
268 /// false if it fails. The number is a private implementation
269 /// detail to the code tblgen produces.
270 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
271 llvm_unreachable("Tblgen should generate the implementation of this!");
274 /// CheckNodePredicateWithOperands - This function is generated by tblgen in
276 /// It runs node predicate number PredNo and returns true if it succeeds or
277 /// false if it fails. The number is a private implementation detail to the
278 /// code tblgen produces.
279 virtual bool CheckNodePredicateWithOperands(
280 SDNode *N, unsigned PredNo,
281 const SmallVectorImpl<SDValue> &Operands) const {
282 llvm_unreachable("Tblgen should generate the implementation of this!");
285 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
287 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
288 llvm_unreachable("Tblgen should generate the implementation of this!");
291 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
292 llvm_unreachable("Tblgen should generate this!");
295 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
298 /// Return true if complex patterns for this target can mutate the
300 virtual bool ComplexPatternFuncMutatesDAG() const {
304 bool isOrEquivalentToAdd(const SDNode *N) const;
308 // Calls to these functions are generated by tblgen.
309 void Select_INLINEASM(SDNode *N, bool Branch);
310 void Select_READ_REGISTER(SDNode *Op);
311 void Select_WRITE_REGISTER(SDNode *Op);
312 void Select_UNDEF(SDNode *N);
313 void CannotYetSelect(SDNode *N);
316 void DoInstructionSelection();
317 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
318 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
320 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
322 /// Prepares the landing pad to take incoming values or do other EH
323 /// personality specific tasks. Returns true if the block should be
324 /// instruction selected, false if no code should be emitted for it.
325 bool PrepareEHLandingPad();
327 /// Perform instruction selection on all basic blocks in the function.
328 void SelectAllBasicBlocks(const Function &Fn);
330 /// Perform instruction selection on a single basic block, for
331 /// instructions between \p Begin and \p End. \p HadTailCall will be set
332 /// to true if a call in the block was translated as a tail call.
333 void SelectBasicBlock(BasicBlock::const_iterator Begin,
334 BasicBlock::const_iterator End,
336 void FinishBasicBlock();
338 void CodeGenAndEmitDAG();
340 /// Generate instructions for lowering the incoming arguments of the
342 void LowerArguments(const Function &F);
344 void ComputeLiveOutVRegInfo();
346 /// Create the scheduler. If a specific scheduler was specified
347 /// via the SchedulerRegistry, use it, otherwise select the
348 /// one preferred by the target.
350 ScheduleDAGSDNodes *CreateScheduler();
352 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
353 /// state machines that start with a OPC_SwitchOpcode node.
354 std::vector<unsigned> OpcodeOffset;
356 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
357 SmallVectorImpl<SDNode *> &ChainNodesMatched,
363 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */