1 //===- StackMaps.h - StackMaps ----------------------------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_STACKMAPS_H
10 #define LLVM_CODEGEN_STACKMAPS_H
12 #include "llvm/ADT/MapVector.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/IR/CallingConv.h"
16 #include "llvm/MC/MCSymbol.h"
17 #include "llvm/Support/Debug.h"
29 class TargetRegisterInfo;
31 /// MI-level stackmap operands.
33 /// MI stackmap operations take the form:
34 /// <id>, <numBytes>, live args...
37 /// Enumerate the meta operands.
38 enum { IDPos, NBytesPos };
41 const MachineInstr* MI;
44 explicit StackMapOpers(const MachineInstr *MI);
46 /// Return the ID for the given stackmap
47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
49 /// Return the number of patchable bytes the given stackmap should emit.
50 uint32_t getNumPatchBytes() const {
51 return MI->getOperand(NBytesPos).getImm();
54 /// Get the operand index of the variable list of non-argument operands.
55 /// These hold the "live state".
56 unsigned getVarIdx() const {
57 // Skip ID, nShadowBytes.
62 /// MI-level patchpoint operands.
64 /// MI patchpoint operations take the form:
65 /// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
67 /// IR patchpoint intrinsics do not have the <cc> operand because calling
68 /// convention is part of the subclass data.
70 /// SD patchpoint nodes do not have a def operand because it is part of the
73 /// Patchpoints following the anyregcc convention are handled specially. For
74 /// these, the stack map also records the location of the return value and
76 class PatchPointOpers {
78 /// Enumerate the meta operands.
79 enum { IDPos, NBytesPos, TargetPos, NArgPos, CCPos, MetaEnd };
82 const MachineInstr *MI;
85 unsigned getMetaIdx(unsigned Pos = 0) const {
86 assert(Pos < MetaEnd && "Meta operand index out of range.");
87 return (HasDef ? 1 : 0) + Pos;
90 const MachineOperand &getMetaOper(unsigned Pos) const {
91 return MI->getOperand(getMetaIdx(Pos));
95 explicit PatchPointOpers(const MachineInstr *MI);
97 bool isAnyReg() const { return (getCallingConv() == CallingConv::AnyReg); }
98 bool hasDef() const { return HasDef; }
100 /// Return the ID for the given patchpoint.
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); }
103 /// Return the number of patchable bytes the given patchpoint should emit.
104 uint32_t getNumPatchBytes() const {
105 return getMetaOper(NBytesPos).getImm();
108 /// Returns the target of the underlying call.
109 const MachineOperand &getCallTarget() const {
110 return getMetaOper(TargetPos);
113 /// Returns the calling convention
114 CallingConv::ID getCallingConv() const {
115 return getMetaOper(CCPos).getImm();
118 unsigned getArgIdx() const { return getMetaIdx() + MetaEnd; }
120 /// Return the number of call arguments
121 uint32_t getNumCallArgs() const {
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm();
125 /// Get the operand index of the variable list of non-argument operands.
126 /// These hold the "live state".
127 unsigned getVarIdx() const {
128 return getMetaIdx() + MetaEnd + getNumCallArgs();
131 /// Get the index at which stack map locations will be recorded.
132 /// Arguments are not recorded unless the anyregcc convention is used.
133 unsigned getStackMapStartIdx() const {
139 /// Get the next scratch register operand index.
140 unsigned getNextScratchIdx(unsigned StartIdx = 0) const;
143 /// MI-level Statepoint operands
145 /// Statepoint operands take the form:
146 /// <id>, <num patch bytes >, <num call arguments>, <call target>,
147 /// [call arguments...],
148 /// <StackMaps::ConstantOp>, <calling convention>,
149 /// <StackMaps::ConstantOp>, <statepoint flags>,
150 /// <StackMaps::ConstantOp>, <num deopt args>, [deopt args...],
151 /// <gc base/derived pairs...> <gc allocas...>
152 /// Note that the last two sets of arguments are not currently length
154 class StatepointOpers {
155 // TODO:: we should change the STATEPOINT representation so that CC and
156 // Flags should be part of meta operands, with args and deopt operands, and
157 // gc operands all prefixed by their length and a type code. This would be
158 // much more consistent.
160 // These values are aboolute offsets into the operands of the statepoint
162 enum { IDPos, NBytesPos, NCallArgsPos, CallTargetPos, MetaEnd };
164 // These values are relative offests from the start of the statepoint meta
165 // arguments (i.e. the end of the call arguments).
166 enum { CCOffset = 1, FlagsOffset = 3, NumDeoptOperandsOffset = 5 };
168 explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {}
170 /// Get starting index of non call related arguments
171 /// (calling convention, statepoint flags, vm state and gc state).
172 unsigned getVarIdx() const {
173 return MI->getOperand(NCallArgsPos).getImm() + MetaEnd;
176 /// Return the ID for the given statepoint.
177 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
179 /// Return the number of patchable bytes the given statepoint should emit.
180 uint32_t getNumPatchBytes() const {
181 return MI->getOperand(NBytesPos).getImm();
184 /// Returns the target of the underlying call.
185 const MachineOperand &getCallTarget() const {
186 return MI->getOperand(CallTargetPos);
190 const MachineInstr *MI;
204 LocationType Type = Unprocessed;
209 Location() = default;
210 Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset)
211 : Type(Type), Size(Size), Reg(Reg), Offset(Offset) {}
215 unsigned short Reg = 0;
216 unsigned short DwarfRegNum = 0;
217 unsigned short Size = 0;
219 LiveOutReg() = default;
220 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum,
222 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {}
225 // OpTypes are used to encode information about the following logical
226 // operand (which may consist of several MachineOperands) for the
228 using OpType = enum { DirectMemRefOp, IndirectMemRefOp, ConstantOp };
230 StackMaps(AsmPrinter &AP);
238 using LocationVec = SmallVector<Location, 8>;
239 using LiveOutVec = SmallVector<LiveOutReg, 8>;
240 using ConstantPool = MapVector<uint64_t, uint64_t>;
242 struct FunctionInfo {
243 uint64_t StackSize = 0;
244 uint64_t RecordCount = 1;
246 FunctionInfo() = default;
247 explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize) {}
250 struct CallsiteInfo {
251 const MCExpr *CSOffsetExpr = nullptr;
253 LocationVec Locations;
256 CallsiteInfo() = default;
257 CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
258 LocationVec &&Locations, LiveOutVec &&LiveOuts)
259 : CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(std::move(Locations)),
260 LiveOuts(std::move(LiveOuts)) {}
263 using FnInfoMap = MapVector<const MCSymbol *, FunctionInfo>;
264 using CallsiteInfoList = std::vector<CallsiteInfo>;
266 /// Generate a stackmap record for a stackmap instruction.
268 /// MI must be a raw STACKMAP, not a PATCHPOINT.
269 void recordStackMap(const MCSymbol &L,
270 const MachineInstr &MI);
272 /// Generate a stackmap record for a patchpoint instruction.
273 void recordPatchPoint(const MCSymbol &L,
274 const MachineInstr &MI);
276 /// Generate a stackmap record for a statepoint instruction.
277 void recordStatepoint(const MCSymbol &L,
278 const MachineInstr &MI);
280 /// If there is any stack map data, create a stack map section and serialize
281 /// the map info into it. This clears the stack map data structures
283 void serializeToStackMapSection();
285 /// Get call site info.
286 CallsiteInfoList &getCSInfos() { return CSInfos; }
288 /// Get function info.
289 FnInfoMap &getFnInfos() { return FnInfos; }
292 static const char *WSMP;
295 CallsiteInfoList CSInfos;
296 ConstantPool ConstPool;
299 MachineInstr::const_mop_iterator
300 parseOperand(MachineInstr::const_mop_iterator MOI,
301 MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
302 LiveOutVec &LiveOuts) const;
304 /// Create a live-out register record for the given register @p Reg.
305 LiveOutReg createLiveOutReg(unsigned Reg,
306 const TargetRegisterInfo *TRI) const;
308 /// Parse the register live-out mask and return a vector of live-out
309 /// registers that need to be recorded in the stackmap.
310 LiveOutVec parseRegisterLiveOutMask(const uint32_t *Mask) const;
312 /// Record the locations of the operands of the provided instruction in a
313 /// record keyed by the provided label. For instructions w/AnyReg calling
314 /// convention the return register is also recorded if requested. For
315 /// STACKMAP, and PATCHPOINT the label is expected to immediately *preceed*
316 /// lowering of the MI to MCInsts. For STATEPOINT, it expected to
317 /// immediately *follow*. It's not clear this difference was intentional,
318 /// but it exists today.
319 void recordStackMapOpers(const MCSymbol &L,
320 const MachineInstr &MI, uint64_t ID,
321 MachineInstr::const_mop_iterator MOI,
322 MachineInstr::const_mop_iterator MOE,
323 bool recordResult = false);
325 /// Emit the stackmap header.
326 void emitStackmapHeader(MCStreamer &OS);
328 /// Emit the function frame record for each function.
329 void emitFunctionFrameRecords(MCStreamer &OS);
331 /// Emit the constant pool.
332 void emitConstantPoolEntries(MCStreamer &OS);
334 /// Emit the callsite info for each stackmap/patchpoint intrinsic call.
335 void emitCallsiteEntries(MCStreamer &OS);
337 void print(raw_ostream &OS);
338 void debug() { print(dbgs()); }
341 } // end namespace llvm
343 #endif // LLVM_CODEGEN_STACKMAPS_H