1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file describes how to lower LLVM code to machine code. This has two
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
17 /// In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/Analysis/ProfileSummaryInfo.h"
32 #include "llvm/CodeGen/DAGCombine.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/TargetCallingConv.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Alignment.h"
52 #include "llvm/Support/AtomicOrdering.h"
53 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MachineValueType.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Transforms/Utils/SizeOpts.h"
70 class BranchProbability;
75 class FunctionLoweringInfo;
80 class LegacyDivergenceAnalysis;
82 class MachineBasicBlock;
83 class MachineFunction;
85 class MachineJumpTableInfo;
87 class MachineRegisterInfo;
91 class TargetRegisterClass;
92 class TargetLibraryInfo;
93 class TargetRegisterInfo;
99 None, // No preference
100 Source, // Follow source order.
101 RegPressure, // Scheduling for lowest register pressure.
102 Hybrid, // Scheduling for both latency and register pressure.
103 ILP, // Scheduling for ILP in low register pressure mode.
104 VLIW // Scheduling for VLIW targets.
107 } // end namespace Sched
109 /// This base class for TargetLowering contains the SelectionDAG-independent
110 /// parts that can be used from the rest of CodeGen.
111 class TargetLoweringBase {
113 /// This enum indicates whether operations are valid for a target, and if not,
114 /// what action should be used to make them valid.
115 enum LegalizeAction : uint8_t {
116 Legal, // The target natively supports this operation.
117 Promote, // This operation should be executed in a larger type.
118 Expand, // Try to expand this to other ops, otherwise use a libcall.
119 LibCall, // Don't try to expand this to other ops, always use a libcall.
120 Custom // Use the LowerOperation hook to implement custom lowering.
123 /// This enum indicates whether a types are legal for a target, and if not,
124 /// what action should be used to make them valid.
125 enum LegalizeTypeAction : uint8_t {
126 TypeLegal, // The target natively supports this type.
127 TypePromoteInteger, // Replace this integer with a larger one.
128 TypeExpandInteger, // Split this integer into two of half the size.
129 TypeSoftenFloat, // Convert this float to a same size integer type.
130 TypeExpandFloat, // Split this float into two of half the size.
131 TypeScalarizeVector, // Replace this one-element vector with its element.
132 TypeSplitVector, // Split this vector into two of half the size.
133 TypeWidenVector, // This vector should be widened into a larger vector.
134 TypePromoteFloat // Replace this float with a larger one.
137 /// LegalizeKind holds the legalization kind that needs to happen to EVT
138 /// in order to type-legalize it.
139 using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
141 /// Enum that describes how the target represents true/false values.
142 enum BooleanContent {
143 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
144 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
145 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
148 /// Enum that describes what type of support for selects the target has.
149 enum SelectSupportKind {
150 ScalarValSelect, // The target supports scalar selects (ex: cmov).
151 ScalarCondVectorVal, // The target supports selects with a scalar condition
152 // and vector values (ex: cmov).
153 VectorMaskSelect // The target supports vector selects with a vector
154 // mask (ex: x86 blends).
157 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
158 /// to, if at all. Exists because different targets have different levels of
159 /// support for these atomic instructions, and also have different options
160 /// w.r.t. what they should expand to.
161 enum class AtomicExpansionKind {
162 None, // Don't expand the instruction.
163 LLSC, // Expand the instruction into loadlinked/storeconditional; used
165 LLOnly, // Expand the (load) instruction into just a load-linked, which has
166 // greater atomic guarantees than a normal load.
167 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
168 MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
171 /// Enum that specifies when a multiplication should be expanded.
172 enum class MulExpansionKind {
173 Always, // Always expand the instruction.
174 OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
180 Value *Val = nullptr;
181 SDValue Node = SDValue();
191 bool IsSwiftSelf : 1;
192 bool IsSwiftError : 1;
193 bool IsCFGuardTarget : 1;
194 uint16_t Alignment = 0;
195 Type *ByValType = nullptr;
198 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
199 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
200 IsSwiftSelf(false), IsSwiftError(false), IsCFGuardTarget(false) {}
202 void setAttributes(const CallBase *Call, unsigned ArgIdx);
204 void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
205 return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
208 using ArgListTy = std::vector<ArgListEntry>;
210 virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
211 ArgListTy &Args) const {};
213 static ISD::NodeType getExtendForContent(BooleanContent Content) {
215 case UndefinedBooleanContent:
216 // Extend by adding rubbish bits.
217 return ISD::ANY_EXTEND;
218 case ZeroOrOneBooleanContent:
219 // Extend by adding zero bits.
220 return ISD::ZERO_EXTEND;
221 case ZeroOrNegativeOneBooleanContent:
222 // Extend by copying the sign bit.
223 return ISD::SIGN_EXTEND;
225 llvm_unreachable("Invalid content kind");
228 explicit TargetLoweringBase(const TargetMachine &TM);
229 TargetLoweringBase(const TargetLoweringBase &) = delete;
230 TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
231 virtual ~TargetLoweringBase() = default;
233 /// Return true if the target support strict float operation
234 bool isStrictFPEnabled() const {
235 return IsStrictFPEnabled;
239 /// Initialize all of the actions to default values.
243 const TargetMachine &getTargetMachine() const { return TM; }
245 virtual bool useSoftFloat() const { return false; }
247 /// Return the pointer type for the given address space, defaults to
248 /// the pointer type from the data layout.
249 /// FIXME: The default needs to be removed once all the code is updated.
250 virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
251 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
254 /// Return the in-memory pointer type for the given address space, defaults to
255 /// the pointer type from the data layout. FIXME: The default needs to be
256 /// removed once all the code is updated.
257 MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
258 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
261 /// Return the type for frame index, which is determined by
262 /// the alloca address space specified through the data layout.
263 MVT getFrameIndexTy(const DataLayout &DL) const {
264 return getPointerTy(DL, DL.getAllocaAddrSpace());
267 /// Return the type for operands of fence.
268 /// TODO: Let fence operands be of i32 type and remove this.
269 virtual MVT getFenceOperandTy(const DataLayout &DL) const {
270 return getPointerTy(DL);
273 /// EVT is not used in-tree, but is used by out-of-tree target.
274 /// A documentation for this function would be nice...
275 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
277 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
278 bool LegalTypes = true) const;
280 /// Returns the type to be used for the index operand of:
281 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
282 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
283 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
284 return getPointerTy(DL);
287 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
291 /// Return true if it is profitable to convert a select of FP constants into
292 /// a constant pool load whose address depends on the select condition. The
293 /// parameter may be used to differentiate a select with FP compare from
295 virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
299 /// Return true if multiple condition registers are available.
300 bool hasMultipleConditionRegisters() const {
301 return HasMultipleConditionRegisters;
304 /// Return true if the target has BitExtract instructions.
305 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
307 /// Return the preferred vector type legalization action.
308 virtual TargetLoweringBase::LegalizeTypeAction
309 getPreferredVectorAction(MVT VT) const {
310 // The default action for one element vectors is to scalarize
311 if (VT.getVectorNumElements() == 1)
312 return TypeScalarizeVector;
313 // The default action for an odd-width vector is to widen.
314 if (!VT.isPow2VectorType())
315 return TypeWidenVector;
316 // The default action for other vectors is to promote
317 return TypePromoteInteger;
320 // There are two general methods for expanding a BUILD_VECTOR node:
321 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
323 // 2. Build the vector on the stack and then load it.
324 // If this function returns true, then method (1) will be used, subject to
325 // the constraint that all of the necessary shuffles are legal (as determined
326 // by isShuffleMaskLegal). If this function returns false, then method (2) is
327 // always used. The vector type, and the number of defined values, are
330 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
331 unsigned DefinedValues) const {
332 return DefinedValues < 3;
335 /// Return true if integer divide is usually cheaper than a sequence of
336 /// several shifts, adds, and multiplies for this target.
337 /// The definition of "cheaper" may depend on whether we're optimizing
338 /// for speed or for size.
339 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
341 /// Return true if the target can handle a standalone remainder operation.
342 virtual bool hasStandaloneRem(EVT VT) const {
346 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
347 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
348 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
352 /// Reciprocal estimate status values used by the functions below.
353 enum ReciprocalEstimate : int {
359 /// Return a ReciprocalEstimate enum value for a square root of the given type
360 /// based on the function's attributes. If the operation is not overridden by
361 /// the function's attributes, "Unspecified" is returned and target defaults
362 /// are expected to be used for instruction selection.
363 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
365 /// Return a ReciprocalEstimate enum value for a division of the given type
366 /// based on the function's attributes. If the operation is not overridden by
367 /// the function's attributes, "Unspecified" is returned and target defaults
368 /// are expected to be used for instruction selection.
369 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
371 /// Return the refinement step count for a square root of the given type based
372 /// on the function's attributes. If the operation is not overridden by
373 /// the function's attributes, "Unspecified" is returned and target defaults
374 /// are expected to be used for instruction selection.
375 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
377 /// Return the refinement step count for a division of the given type based
378 /// on the function's attributes. If the operation is not overridden by
379 /// the function's attributes, "Unspecified" is returned and target defaults
380 /// are expected to be used for instruction selection.
381 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
383 /// Returns true if target has indicated at least one type should be bypassed.
384 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
386 /// Returns map of slow types for division or remainder with corresponding
388 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
389 return BypassSlowDivWidths;
392 /// Return true if Flow Control is an expensive operation that should be
394 bool isJumpExpensive() const { return JumpIsExpensive; }
396 /// Return true if selects are only cheaper than branches if the branch is
397 /// unlikely to be predicted right.
398 bool isPredictableSelectExpensive() const {
399 return PredictableSelectIsExpensive;
402 /// If a branch or a select condition is skewed in one direction by more than
403 /// this factor, it is very likely to be predicted correctly.
404 virtual BranchProbability getPredictableBranchThreshold() const;
406 /// Return true if the following transform is beneficial:
407 /// fold (conv (load x)) -> (load (conv*)x)
408 /// On architectures that don't natively support some vector loads
409 /// efficiently, casting the load to a smaller vector of larger types and
410 /// loading is more efficient, however, this can be undone by optimizations in
412 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
413 const SelectionDAG &DAG,
414 const MachineMemOperand &MMO) const {
415 // Don't do if we could do an indexed load on the original type, but not on
417 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
420 MVT LoadMVT = LoadVT.getSimpleVT();
422 // Don't bother doing this if it's just going to be promoted again later, as
423 // doing so might interfere with other combines.
424 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
425 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
429 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
433 /// Return true if the following transform is beneficial:
434 /// (store (y (conv x)), y*)) -> (store x, (x*))
435 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
436 const SelectionDAG &DAG,
437 const MachineMemOperand &MMO) const {
438 // Default to the same logic as loads.
439 return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
442 /// Return true if it is expected to be cheaper to do a store of a non-zero
443 /// vector constant with the given size and type for the address space than to
444 /// store the individual scalar element constants.
445 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
447 unsigned AddrSpace) const {
451 /// Allow store merging for the specified type after legalization in addition
452 /// to before legalization. This may transform stores that do not exist
453 /// earlier (for example, stores created from intrinsics).
454 virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
458 /// Returns if it's reasonable to merge stores to MemVT size.
459 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
460 const SelectionDAG &DAG) const {
464 /// Return true if it is cheap to speculate a call to intrinsic cttz.
465 virtual bool isCheapToSpeculateCttz() const {
469 /// Return true if it is cheap to speculate a call to intrinsic ctlz.
470 virtual bool isCheapToSpeculateCtlz() const {
474 /// Return true if ctlz instruction is fast.
475 virtual bool isCtlzFast() const {
479 /// Return true if instruction generated for equality comparison is folded
480 /// with instruction generated for signed comparison.
481 virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
483 /// Return true if it is safe to transform an integer-domain bitwise operation
484 /// into the equivalent floating-point operation. This should be set to true
485 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
487 virtual bool hasBitPreservingFPLogic(EVT VT) const {
491 /// Return true if it is cheaper to split the store of a merged int val
492 /// from a pair of smaller values into multiple stores.
493 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
497 /// Return if the target supports combining a
500 /// %andResult = and %val1, #mask
501 /// %icmpResult = icmp %andResult, 0
503 /// into a single machine instruction of a form like:
505 /// cc = test %register, #mask
507 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
511 /// Use bitwise logic to make pairs of compares more efficient. For example:
512 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
513 /// This should be true when it takes more than one instruction to lower
514 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
515 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
516 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
520 /// Return the preferred operand type if the target has a quick way to compare
521 /// integer values of the given size. Assume that any legal integer type can
522 /// be compared efficiently. Targets may override this to allow illegal wide
523 /// types to return a vector type if there is support to compare that type.
524 virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
525 MVT VT = MVT::getIntegerVT(NumBits);
526 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
529 /// Return true if the target should transform:
530 /// (X & Y) == Y ---> (~X & Y) == 0
531 /// (X & Y) != Y ---> (~X & Y) != 0
533 /// This may be profitable if the target has a bitwise and-not operation that
534 /// sets comparison flags. A target may want to limit the transformation based
535 /// on the type of Y or if Y is a constant.
537 /// Note that the transform will not occur if Y is known to be a power-of-2
538 /// because a mask and compare of a single bit can be handled by inverting the
539 /// predicate, for example:
540 /// (X & 8) == 8 ---> (X & 8) != 0
541 virtual bool hasAndNotCompare(SDValue Y) const {
545 /// Return true if the target has a bitwise and-not operation:
547 /// This can be used to simplify select or other instructions.
548 virtual bool hasAndNot(SDValue X) const {
549 // If the target has the more complex version of this operation, assume that
550 // it has this operation too.
551 return hasAndNotCompare(X);
554 /// Return true if the target has a bit-test instruction:
555 /// (X & (1 << Y)) ==/!= 0
556 /// This knowledge can be used to prevent breaking the pattern,
557 /// or creating it if it could be recognized.
558 virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
560 /// There are two ways to clear extreme bits (either low or high):
561 /// Mask: x & (-1 << y) (the instcombine canonical form)
562 /// Shifts: x >> y << y
563 /// Return true if the variant with 2 variable shifts is preferred.
564 /// Return false if there is no preference.
565 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const {
566 // By default, let's assume that no one prefers shifts.
570 /// Return true if it is profitable to fold a pair of shifts into a mask.
571 /// This is usually true on most targets. But some targets, like Thumb1,
572 /// have immediate shift instructions, but no immediate "and" instruction;
573 /// this makes the fold unprofitable.
574 virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,
575 CombineLevel Level) const {
579 /// Should we tranform the IR-optimal check for whether given truncation
580 /// down into KeptBits would be truncating or not:
581 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
582 /// Into it's more traditional form:
583 /// ((%x << C) a>> C) dstcond %x
584 /// Return true if we should transform.
585 /// Return false if there is no preference.
586 virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
587 unsigned KeptBits) const {
588 // By default, let's assume that no one prefers shifts.
592 /// Given the pattern
593 /// (X & (C l>>/<< Y)) ==/!= 0
594 /// return true if it should be transformed into:
595 /// ((X <</l>> Y) & C) ==/!= 0
596 /// WARNING: if 'X' is a constant, the fold may deadlock!
597 /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
598 /// here because it can end up being not linked in.
599 virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
600 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
601 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
602 SelectionDAG &DAG) const {
603 if (hasBitTest(X, Y)) {
604 // One interesting pattern that we'd want to form is 'bit test':
605 // ((1 << Y) & C) ==/!= 0
606 // But we also need to be careful not to try to reverse that fold.
608 // Is this '1 << Y' ?
609 if (OldShiftOpcode == ISD::SHL && CC->isOne())
610 return false; // Keep the 'bit test' pattern.
612 // Will it be '1 << Y' after the transform ?
613 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
614 return true; // Do form the 'bit test' pattern.
617 // If 'X' is a constant, and we transform, then we will immediately
618 // try to undo the fold, thus causing endless combine loop.
619 // So by default, let's assume everyone prefers the fold
620 // iff 'X' is not a constant.
624 /// These two forms are equivalent:
625 /// sub %y, (xor %x, -1)
626 /// add (add %x, 1), %y
627 /// The variant with two add's is IR-canonical.
628 /// Some targets may prefer one to the other.
629 virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
630 // By default, let's assume that everyone prefers the form with two add's.
634 /// Return true if the target wants to use the optimization that
635 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
636 /// promotedInst1(...(promotedInstN(ext(load)))).
637 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
639 /// Return true if the target can combine store(extractelement VectorTy,
641 /// \p Cost[out] gives the cost of that transformation when this is true.
642 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
643 unsigned &Cost) const {
647 /// Return true if inserting a scalar into a variable element of an undef
648 /// vector is more efficiently handled by splatting the scalar instead.
649 virtual bool shouldSplatInsEltVarIndex(EVT) const {
653 /// Return true if target always beneficiates from combining into FMA for a
654 /// given value type. This must typically return false on targets where FMA
655 /// takes more cycles to execute than FADD.
656 virtual bool enableAggressiveFMAFusion(EVT VT) const {
660 /// Return the ValueType of the result of SETCC operations.
661 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
664 /// Return the ValueType for comparison libcalls. Comparions libcalls include
665 /// floating point comparion calls, and Ordered/Unordered check calls on
666 /// floating point numbers.
668 MVT::SimpleValueType getCmpLibcallReturnType() const;
670 /// For targets without i1 registers, this gives the nature of the high-bits
671 /// of boolean values held in types wider than i1.
673 /// "Boolean values" are special true/false values produced by nodes like
674 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
675 /// Not to be confused with general values promoted from i1. Some cpus
676 /// distinguish between vectors of boolean and scalars; the isVec parameter
677 /// selects between the two kinds. For example on X86 a scalar boolean should
678 /// be zero extended from i1, while the elements of a vector of booleans
679 /// should be sign extended from i1.
681 /// Some cpus also treat floating point types the same way as they treat
682 /// vectors instead of the way they treat scalars.
683 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
685 return BooleanVectorContents;
686 return isFloat ? BooleanFloatContents : BooleanContents;
689 BooleanContent getBooleanContents(EVT Type) const {
690 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
693 /// Return target scheduling preference.
694 Sched::Preference getSchedulingPreference() const {
695 return SchedPreferenceInfo;
698 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
699 /// for different nodes. This function returns the preference (or none) for
701 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
705 /// Return the register class that should be used for the specified value
707 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
709 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
710 assert(RC && "This value type is not natively supported!");
714 /// Allows target to decide about the register class of the
715 /// specific value that is live outside the defining block.
716 /// Returns true if the value needs uniform register class.
717 virtual bool requiresUniformRegister(MachineFunction &MF,
718 const Value *) const {
722 /// Return the 'representative' register class for the specified value
725 /// The 'representative' register class is the largest legal super-reg
726 /// register class for the register class of the value type. For example, on
727 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
728 /// register class is GR64 on x86_64.
729 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
730 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
734 /// Return the cost of the 'representative' register class for the specified
736 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
737 return RepRegClassCostForVT[VT.SimpleTy];
740 /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
741 /// instructions, and false if a library call is preferred (e.g for code-size
743 virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
747 /// Return true if the target has native support for the specified value type.
748 /// This means that it has a register that directly holds it without
749 /// promotions or expansions.
750 bool isTypeLegal(EVT VT) const {
751 assert(!VT.isSimple() ||
752 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
753 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
756 class ValueTypeActionImpl {
757 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
758 /// that indicates how instruction selection should deal with the type.
759 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
762 ValueTypeActionImpl() {
763 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
767 LegalizeTypeAction getTypeAction(MVT VT) const {
768 return ValueTypeActions[VT.SimpleTy];
771 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
772 ValueTypeActions[VT.SimpleTy] = Action;
776 const ValueTypeActionImpl &getValueTypeActions() const {
777 return ValueTypeActions;
780 /// Return how we should legalize values of this type, either it is already
781 /// legal (return 'Legal') or we need to promote it to a larger type (return
782 /// 'Promote'), or we need to expand it into multiple registers of smaller
783 /// integer type (return 'Expand'). 'Custom' is not an option.
784 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
785 return getTypeConversion(Context, VT).first;
787 LegalizeTypeAction getTypeAction(MVT VT) const {
788 return ValueTypeActions.getTypeAction(VT);
791 /// For types supported by the target, this is an identity function. For
792 /// types that must be promoted to larger types, this returns the larger type
793 /// to promote to. For integer types that are larger than the largest integer
794 /// register, this contains one step in the expansion to get to the smaller
795 /// register. For illegal floating point types, this returns the integer type
797 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
798 return getTypeConversion(Context, VT).second;
801 /// For types supported by the target, this is an identity function. For
802 /// types that must be expanded (i.e. integer types that are larger than the
803 /// largest integer register or illegal floating point types), this returns
804 /// the largest legal type it will be expanded to.
805 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
806 assert(!VT.isVector());
808 switch (getTypeAction(Context, VT)) {
811 case TypeExpandInteger:
812 VT = getTypeToTransformTo(Context, VT);
815 llvm_unreachable("Type is not legal nor is it to be expanded!");
820 /// Vector types are broken down into some number of legal first class types.
821 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
822 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
823 /// turns into 4 EVT::i32 values with both PPC and X86.
825 /// This method returns the number of registers needed, and the VT for each
826 /// register. It also returns the VT and quantity of the intermediate values
827 /// before they are promoted/expanded.
828 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
830 unsigned &NumIntermediates,
831 MVT &RegisterVT) const;
833 /// Certain targets such as MIPS require that some types such as vectors are
834 /// always broken down into scalars in some contexts. This occurs even if the
835 /// vector type is legal.
836 virtual unsigned getVectorTypeBreakdownForCallingConv(
837 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
838 unsigned &NumIntermediates, MVT &RegisterVT) const {
839 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
843 struct IntrinsicInfo {
844 unsigned opc = 0; // target opcode
845 EVT memVT; // memory VT
847 // value representing memory location
848 PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
850 int offset = 0; // offset off of ptrVal
851 uint64_t size = 0; // the size of the memory location
852 // (taken from memVT if zero)
853 MaybeAlign align = Align::None(); // alignment
855 MachineMemOperand::Flags flags = MachineMemOperand::MONone;
856 IntrinsicInfo() = default;
859 /// Given an intrinsic, checks if on the target the intrinsic will need to map
860 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
861 /// true and store the intrinsic information into the IntrinsicInfo that was
862 /// passed to the function.
863 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
865 unsigned /*Intrinsic*/) const {
869 /// Returns true if the target can instruction select the specified FP
870 /// immediate natively. If false, the legalizer will materialize the FP
871 /// immediate as a load from a constant pool.
872 virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
873 bool ForCodeSize = false) const {
877 /// Targets can use this to indicate that they only support *some*
878 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
879 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
881 virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
885 /// Returns true if the operation can trap for the value type.
887 /// VT must be a legal type. By default, we optimistically assume most
888 /// operations don't trap except for integer divide and remainder.
889 virtual bool canOpTrap(unsigned Op, EVT VT) const;
891 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
892 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
893 /// constant pool entry.
894 virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
899 /// Return how this operation should be treated: either it is legal, needs to
900 /// be promoted to a larger size, needs to be expanded to some other code
901 /// sequence, or the target has a custom expander for it.
902 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
903 if (VT.isExtended()) return Expand;
904 // If a target-specific SDNode requires legalization, require the target
905 // to provide custom legalization for it.
906 if (Op >= array_lengthof(OpActions[0])) return Custom;
907 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
910 /// Custom method defined by each target to indicate if an operation which
911 /// may require a scale is supported natively by the target.
912 /// If not, the operation is illegal.
913 virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
914 unsigned Scale) const {
918 /// Some fixed point operations may be natively supported by the target but
919 /// only for specific scales. This method allows for checking
920 /// if the width is supported by the target for a given operation that may
922 LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT,
923 unsigned Scale) const {
924 auto Action = getOperationAction(Op, VT);
928 // This operation is supported in this type but may only work on specific
933 llvm_unreachable("Unexpected fixed point operation.");
935 case ISD::SMULFIXSAT:
937 case ISD::UMULFIXSAT:
940 Supported = isSupportedFixedPointOperation(Op, VT, Scale);
944 return Supported ? Action : Expand;
947 // If Op is a strict floating-point operation, return the result
948 // of getOperationAction for the equivalent non-strict operation.
949 LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
952 default: llvm_unreachable("Unexpected FP pseudo-opcode");
953 #define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
954 case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
955 #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
956 case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
957 #include "llvm/IR/ConstrainedOps.def"
960 return getOperationAction(EqOpc, VT);
963 /// Return true if the specified operation is legal on this target or can be
964 /// made legal with custom lowering. This is used to help guide high-level
965 /// lowering decisions.
966 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
967 return (VT == MVT::Other || isTypeLegal(VT)) &&
968 (getOperationAction(Op, VT) == Legal ||
969 getOperationAction(Op, VT) == Custom);
972 /// Return true if the specified operation is legal on this target or can be
973 /// made legal using promotion. This is used to help guide high-level lowering
975 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
976 return (VT == MVT::Other || isTypeLegal(VT)) &&
977 (getOperationAction(Op, VT) == Legal ||
978 getOperationAction(Op, VT) == Promote);
981 /// Return true if the specified operation is legal on this target or can be
982 /// made legal with custom lowering or using promotion. This is used to help
983 /// guide high-level lowering decisions.
984 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
985 return (VT == MVT::Other || isTypeLegal(VT)) &&
986 (getOperationAction(Op, VT) == Legal ||
987 getOperationAction(Op, VT) == Custom ||
988 getOperationAction(Op, VT) == Promote);
991 /// Return true if the operation uses custom lowering, regardless of whether
992 /// the type is legal or not.
993 bool isOperationCustom(unsigned Op, EVT VT) const {
994 return getOperationAction(Op, VT) == Custom;
997 /// Return true if lowering to a jump table is allowed.
998 virtual bool areJTsAllowed(const Function *Fn) const {
999 if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1002 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1003 isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
1006 /// Check whether the range [Low,High] fits in a machine word.
1007 bool rangeFitsInWord(const APInt &Low, const APInt &High,
1008 const DataLayout &DL) const {
1009 // FIXME: Using the pointer type doesn't seem ideal.
1010 uint64_t BW = DL.getIndexSizeInBits(0u);
1011 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
1015 /// Return true if lowering to a jump table is suitable for a set of case
1016 /// clusters which may contain \p NumCases cases, \p Range range of values.
1017 virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1018 uint64_t Range, ProfileSummaryInfo *PSI,
1019 BlockFrequencyInfo *BFI) const;
1021 /// Return true if lowering to a bit test is suitable for a set of case
1022 /// clusters which contains \p NumDests unique destinations, \p Low and
1023 /// \p High as its lowest and highest case values, and expects \p NumCmps
1024 /// case value comparisons. Check if the number of destinations, comparison
1025 /// metric, and range are all suitable.
1026 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1027 const APInt &Low, const APInt &High,
1028 const DataLayout &DL) const {
1029 // FIXME: I don't think NumCmps is the correct metric: a single case and a
1030 // range of cases both require only one branch to lower. Just looking at the
1031 // number of clusters and destinations should be enough to decide whether to
1034 // To lower a range with bit tests, the range must fit the bitwidth of a
1036 if (!rangeFitsInWord(Low, High, DL))
1039 // Decide whether it's profitable to lower this range with bit tests. Each
1040 // destination requires a bit test and branch, and there is an overall range
1041 // check branch. For a small number of clusters, separate comparisons might
1042 // be cheaper, and for many destinations, splitting the range might be
1044 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1045 (NumDests == 3 && NumCmps >= 6);
1048 /// Return true if the specified operation is illegal on this target or
1049 /// unlikely to be made legal with custom lowering. This is used to help guide
1050 /// high-level lowering decisions.
1051 bool isOperationExpand(unsigned Op, EVT VT) const {
1052 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1055 /// Return true if the specified operation is legal on this target.
1056 bool isOperationLegal(unsigned Op, EVT VT) const {
1057 return (VT == MVT::Other || isTypeLegal(VT)) &&
1058 getOperationAction(Op, VT) == Legal;
1061 /// Return how this load with extension should be treated: either it is legal,
1062 /// needs to be promoted to a larger size, needs to be expanded to some other
1063 /// code sequence, or the target has a custom expander for it.
1064 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
1066 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1067 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1068 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1069 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1070 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1071 unsigned Shift = 4 * ExtType;
1072 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1075 /// Return true if the specified load with extension is legal on this target.
1076 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1077 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1080 /// Return true if the specified load with extension is legal or custom
1082 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1083 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1084 getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1087 /// Return how this store with truncation should be treated: either it is
1088 /// legal, needs to be promoted to a larger size, needs to be expanded to some
1089 /// other code sequence, or the target has a custom expander for it.
1090 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
1091 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1092 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1093 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1094 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1095 "Table isn't big enough!");
1096 return TruncStoreActions[ValI][MemI];
1099 /// Return true if the specified store with truncation is legal on this
1101 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1102 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1105 /// Return true if the specified store with truncation has solution on this
1107 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1108 return isTypeLegal(ValVT) &&
1109 (getTruncStoreAction(ValVT, MemVT) == Legal ||
1110 getTruncStoreAction(ValVT, MemVT) == Custom);
1113 /// Return how the indexed load should be treated: either it is legal, needs
1114 /// to be promoted to a larger size, needs to be expanded to some other code
1115 /// sequence, or the target has a custom expander for it.
1116 LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1117 return getIndexedModeAction(IdxMode, VT, IMAB_Load);
1120 /// Return true if the specified indexed load is legal on this target.
1121 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1122 return VT.isSimple() &&
1123 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1124 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1127 /// Return how the indexed store should be treated: either it is legal, needs
1128 /// to be promoted to a larger size, needs to be expanded to some other code
1129 /// sequence, or the target has a custom expander for it.
1130 LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1131 return getIndexedModeAction(IdxMode, VT, IMAB_Store);
1134 /// Return true if the specified indexed load is legal on this target.
1135 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1136 return VT.isSimple() &&
1137 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1138 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1141 /// Return how the indexed load should be treated: either it is legal, needs
1142 /// to be promoted to a larger size, needs to be expanded to some other code
1143 /// sequence, or the target has a custom expander for it.
1144 LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const {
1145 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
1148 /// Return true if the specified indexed load is legal on this target.
1149 bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const {
1150 return VT.isSimple() &&
1151 (getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1152 getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1155 /// Return how the indexed store should be treated: either it is legal, needs
1156 /// to be promoted to a larger size, needs to be expanded to some other code
1157 /// sequence, or the target has a custom expander for it.
1158 LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const {
1159 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
1162 /// Return true if the specified indexed load is legal on this target.
1163 bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const {
1164 return VT.isSimple() &&
1165 (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1166 getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1169 /// Return how the condition code should be treated: either it is legal, needs
1170 /// to be expanded to some other code sequence, or the target has a custom
1171 /// expander for it.
1173 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1174 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1175 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1176 "Table isn't big enough!");
1177 // See setCondCodeAction for how this is encoded.
1178 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1179 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1180 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1181 assert(Action != Promote && "Can't promote condition code!");
1185 /// Return true if the specified condition code is legal on this target.
1186 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1187 return getCondCodeAction(CC, VT) == Legal;
1190 /// Return true if the specified condition code is legal or custom on this
1192 bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1193 return getCondCodeAction(CC, VT) == Legal ||
1194 getCondCodeAction(CC, VT) == Custom;
1197 /// If the action for this operation is to promote, this method returns the
1198 /// ValueType to promote to.
1199 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1200 assert(getOperationAction(Op, VT) == Promote &&
1201 "This operation isn't promoted!");
1203 // See if this has an explicit type specified.
1204 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1205 MVT::SimpleValueType>::const_iterator PTTI =
1206 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1207 if (PTTI != PromoteToType.end()) return PTTI->second;
1209 assert((VT.isInteger() || VT.isFloatingPoint()) &&
1210 "Cannot autopromote this type, add it with AddPromotedToType.");
1214 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1215 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1216 "Didn't find type to promote to!");
1217 } while (!isTypeLegal(NVT) ||
1218 getOperationAction(Op, NVT) == Promote);
1222 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1223 /// operations except for the pointer size. If AllowUnknown is true, this
1224 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1225 /// otherwise it will assert.
1226 EVT getValueType(const DataLayout &DL, Type *Ty,
1227 bool AllowUnknown = false) const {
1228 // Lower scalar pointers to native pointer types.
1229 if (auto *PTy = dyn_cast<PointerType>(Ty))
1230 return getPointerTy(DL, PTy->getAddressSpace());
1232 if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1233 Type *EltTy = VTy->getElementType();
1234 // Lower vectors of pointers to native pointer types.
1235 if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1236 EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1237 EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1239 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1240 VTy->getElementCount());
1243 return EVT::getEVT(Ty, AllowUnknown);
1246 EVT getMemValueType(const DataLayout &DL, Type *Ty,
1247 bool AllowUnknown = false) const {
1248 // Lower scalar pointers to native pointer types.
1249 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1250 return getPointerMemTy(DL, PTy->getAddressSpace());
1251 else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1252 Type *Elm = VTy->getElementType();
1253 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1254 EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1255 Elm = PointerTy.getTypeForEVT(Ty->getContext());
1257 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1258 VTy->getElementCount());
1261 return getValueType(DL, Ty, AllowUnknown);
1265 /// Return the MVT corresponding to this LLVM type. See getValueType.
1266 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1267 bool AllowUnknown = false) const {
1268 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1271 /// Return the desired alignment for ByVal or InAlloca aggregate function
1272 /// arguments in the caller parameter area. This is the actual alignment, not
1274 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1276 /// Return the type of registers that this ValueType will eventually require.
1277 MVT getRegisterType(MVT VT) const {
1278 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1279 return RegisterTypeForVT[VT.SimpleTy];
1282 /// Return the type of registers that this ValueType will eventually require.
1283 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1284 if (VT.isSimple()) {
1285 assert((unsigned)VT.getSimpleVT().SimpleTy <
1286 array_lengthof(RegisterTypeForVT));
1287 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1289 if (VT.isVector()) {
1292 unsigned NumIntermediates;
1293 (void)getVectorTypeBreakdown(Context, VT, VT1,
1294 NumIntermediates, RegisterVT);
1297 if (VT.isInteger()) {
1298 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1300 llvm_unreachable("Unsupported extended type!");
1303 /// Return the number of registers that this ValueType will eventually
1306 /// This is one for any types promoted to live in larger registers, but may be
1307 /// more than one for types (like i64) that are split into pieces. For types
1308 /// like i140, which are first promoted then expanded, it is the number of
1309 /// registers needed to hold all the bits of the original type. For an i140
1310 /// on a 32 bit machine this means 5 registers.
1311 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1312 if (VT.isSimple()) {
1313 assert((unsigned)VT.getSimpleVT().SimpleTy <
1314 array_lengthof(NumRegistersForVT));
1315 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1317 if (VT.isVector()) {
1320 unsigned NumIntermediates;
1321 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1323 if (VT.isInteger()) {
1324 unsigned BitWidth = VT.getSizeInBits();
1325 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1326 return (BitWidth + RegWidth - 1) / RegWidth;
1328 llvm_unreachable("Unsupported extended type!");
1331 /// Certain combinations of ABIs, Targets and features require that types
1332 /// are legal for some operations and not for other operations.
1333 /// For MIPS all vector types must be passed through the integer register set.
1334 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1335 CallingConv::ID CC, EVT VT) const {
1336 return getRegisterType(Context, VT);
1339 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1340 /// this occurs when a vector type is used, as vector are passed through the
1341 /// integer register set.
1342 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1345 return getNumRegisters(Context, VT);
1348 /// Certain targets have context senstive alignment requirements, where one
1349 /// type has the alignment requirement of another type.
1350 virtual Align getABIAlignmentForCallingConv(Type *ArgTy,
1351 DataLayout DL) const {
1352 return Align(DL.getABITypeAlignment(ArgTy));
1355 /// If true, then instruction selection should seek to shrink the FP constant
1356 /// of the specified type to a smaller type in order to save space and / or
1358 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1360 /// Return true if it is profitable to reduce a load to a smaller type.
1361 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1362 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1364 // By default, assume that it is cheaper to extract a subvector from a wide
1365 // vector load rather than creating multiple narrow vector loads.
1366 if (NewVT.isVector() && !Load->hasOneUse())
1372 /// When splitting a value of the specified type into parts, does the Lo
1373 /// or Hi part come first? This usually follows the endianness, except
1374 /// for ppcf128, where the Hi part always comes first.
1375 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1376 return DL.isBigEndian() || VT == MVT::ppcf128;
1379 /// If true, the target has custom DAG combine transformations that it can
1380 /// perform for the specified node.
1381 bool hasTargetDAGCombine(ISD::NodeType NT) const {
1382 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1383 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1386 unsigned getGatherAllAliasesMaxDepth() const {
1387 return GatherAllAliasesMaxDepth;
1390 /// Returns the size of the platform's va_list object.
1391 virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1392 return getPointerTy(DL).getSizeInBits();
1395 /// Get maximum # of store operations permitted for llvm.memset
1397 /// This function returns the maximum number of store operations permitted
1398 /// to replace a call to llvm.memset. The value is set by the target at the
1399 /// performance threshold for such a replacement. If OptSize is true,
1400 /// return the limit for functions that have OptSize attribute.
1401 unsigned getMaxStoresPerMemset(bool OptSize) const {
1402 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1405 /// Get maximum # of store operations permitted for llvm.memcpy
1407 /// This function returns the maximum number of store operations permitted
1408 /// to replace a call to llvm.memcpy. The value is set by the target at the
1409 /// performance threshold for such a replacement. If OptSize is true,
1410 /// return the limit for functions that have OptSize attribute.
1411 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1412 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1415 /// \brief Get maximum # of store operations to be glued together
1417 /// This function returns the maximum number of store operations permitted
1418 /// to glue together during lowering of llvm.memcpy. The value is set by
1419 // the target at the performance threshold for such a replacement.
1420 virtual unsigned getMaxGluedStoresPerMemcpy() const {
1421 return MaxGluedStoresPerMemcpy;
1424 /// Get maximum # of load operations permitted for memcmp
1426 /// This function returns the maximum number of load operations permitted
1427 /// to replace a call to memcmp. The value is set by the target at the
1428 /// performance threshold for such a replacement. If OptSize is true,
1429 /// return the limit for functions that have OptSize attribute.
1430 unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1431 return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1434 /// Get maximum # of store operations permitted for llvm.memmove
1436 /// This function returns the maximum number of store operations permitted
1437 /// to replace a call to llvm.memmove. The value is set by the target at the
1438 /// performance threshold for such a replacement. If OptSize is true,
1439 /// return the limit for functions that have OptSize attribute.
1440 unsigned getMaxStoresPerMemmove(bool OptSize) const {
1441 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1444 /// Determine if the target supports unaligned memory accesses.
1446 /// This function returns true if the target allows unaligned memory accesses
1447 /// of the specified type in the given address space. If true, it also returns
1448 /// whether the unaligned memory access is "fast" in the last argument by
1449 /// reference. This is used, for example, in situations where an array
1450 /// copy/move/set is converted to a sequence of store operations. Its use
1451 /// helps to ensure that such replacements don't generate code that causes an
1452 /// alignment error (trap) on the target machine.
1453 virtual bool allowsMisalignedMemoryAccesses(
1454 EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1455 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1456 bool * /*Fast*/ = nullptr) const {
1460 /// LLT handling variant.
1461 virtual bool allowsMisalignedMemoryAccesses(
1462 LLT, unsigned AddrSpace = 0, unsigned Align = 1,
1463 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1464 bool * /*Fast*/ = nullptr) const {
1468 /// This function returns true if the memory access is aligned or if the
1469 /// target allows this specific unaligned memory access. If the access is
1470 /// allowed, the optional final parameter returns if the access is also fast
1471 /// (as defined by the target).
1472 bool allowsMemoryAccessForAlignment(
1473 LLVMContext &Context, const DataLayout &DL, EVT VT,
1474 unsigned AddrSpace = 0, unsigned Alignment = 1,
1475 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1476 bool *Fast = nullptr) const;
1478 /// Return true if the memory access of this type is aligned or if the target
1479 /// allows this specific unaligned access for the given MachineMemOperand.
1480 /// If the access is allowed, the optional final parameter returns if the
1481 /// access is also fast (as defined by the target).
1482 bool allowsMemoryAccessForAlignment(LLVMContext &Context,
1483 const DataLayout &DL, EVT VT,
1484 const MachineMemOperand &MMO,
1485 bool *Fast = nullptr) const;
1487 /// Return true if the target supports a memory access of this type for the
1488 /// given address space and alignment. If the access is allowed, the optional
1489 /// final parameter returns if the access is also fast (as defined by the
1492 allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1493 unsigned AddrSpace = 0, unsigned Alignment = 1,
1494 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
1495 bool *Fast = nullptr) const;
1497 /// Return true if the target supports a memory access of this type for the
1498 /// given MachineMemOperand. If the access is allowed, the optional
1499 /// final parameter returns if the access is also fast (as defined by the
1501 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1502 const MachineMemOperand &MMO,
1503 bool *Fast = nullptr) const;
1505 /// Returns the target specific optimal type for load and store operations as
1506 /// a result of memset, memcpy, and memmove lowering.
1508 /// If DstAlign is zero that means it's safe to destination alignment can
1509 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1510 /// a need to check it against alignment requirement, probably because the
1511 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1512 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1513 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1514 /// does not need to be loaded. It returns EVT::Other if the type should be
1515 /// determined using generic target-independent logic.
1517 getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1518 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1519 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1520 const AttributeList & /*FuncAttributes*/) const {
1525 /// LLT returning variant.
1527 getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1528 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1529 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1530 const AttributeList & /*FuncAttributes*/) const {
1534 /// Returns true if it's safe to use load / store of the specified type to
1535 /// expand memcpy / memset inline.
1537 /// This is mostly true for all types except for some special cases. For
1538 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1539 /// fstpl which also does type conversion. Note the specified type doesn't
1540 /// have to be legal as the hook is used before type legalization.
1541 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1543 /// Return lower limit for number of blocks in a jump table.
1544 virtual unsigned getMinimumJumpTableEntries() const;
1546 /// Return lower limit of the density in a jump table.
1547 unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1549 /// Return upper limit for number of entries in a jump table.
1550 /// Zero if no limit.
1551 unsigned getMaximumJumpTableSize() const;
1553 virtual bool isJumpTableRelative() const {
1554 return TM.isPositionIndependent();
1557 /// If a physical register, this specifies the register that
1558 /// llvm.savestack/llvm.restorestack should save and restore.
1559 unsigned getStackPointerRegisterToSaveRestore() const {
1560 return StackPointerRegisterToSaveRestore;
1563 /// If a physical register, this returns the register that receives the
1564 /// exception address on entry to an EH pad.
1566 getExceptionPointerRegister(const Constant *PersonalityFn) const {
1567 // 0 is guaranteed to be the NoRegister value on all targets
1571 /// If a physical register, this returns the register that receives the
1572 /// exception typeid on entry to a landing pad.
1574 getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1575 // 0 is guaranteed to be the NoRegister value on all targets
1579 virtual bool needsFixedCatchObjects() const {
1580 report_fatal_error("Funclet EH is not implemented for this target");
1583 /// Return the minimum stack alignment of an argument.
1584 Align getMinStackArgumentAlignment() const {
1585 return MinStackArgumentAlignment;
1588 /// Return the minimum function alignment.
1589 Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
1591 /// Return the preferred function alignment.
1592 Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
1594 /// Return the preferred loop alignment.
1595 virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1596 return PrefLoopAlignment;
1599 /// Should loops be aligned even when the function is marked OptSize (but not
1601 virtual bool alignLoopsWithOptSize() const {
1605 /// If the target has a standard location for the stack protector guard,
1606 /// returns the address of that location. Otherwise, returns nullptr.
1607 /// DEPRECATED: please override useLoadStackGuardNode and customize
1608 /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1609 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1611 /// Inserts necessary declarations for SSP (stack protection) purpose.
1612 /// Should be used only when getIRStackGuard returns nullptr.
1613 virtual void insertSSPDeclarations(Module &M) const;
1615 /// Return the variable that's previously inserted by insertSSPDeclarations,
1616 /// if any, otherwise return nullptr. Should be used only when
1617 /// getIRStackGuard returns nullptr.
1618 virtual Value *getSDagStackGuard(const Module &M) const;
1620 /// If this function returns true, stack protection checks should XOR the
1621 /// frame pointer (or whichever pointer is used to address locals) into the
1622 /// stack guard value before checking it. getIRStackGuard must return nullptr
1623 /// if this returns true.
1624 virtual bool useStackGuardXorFP() const { return false; }
1626 /// If the target has a standard stack protection check function that
1627 /// performs validation and error handling, returns the function. Otherwise,
1628 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1629 /// Should be used only when getIRStackGuard returns nullptr.
1630 virtual Function *getSSPStackGuardCheck(const Module &M) const;
1633 Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1637 /// Returns the target-specific address of the unsafe stack pointer.
1638 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1640 /// Returns the name of the symbol used to emit stack probes or the empty
1641 /// string if not applicable.
1642 virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1646 /// Returns true if a cast between SrcAS and DestAS is a noop.
1647 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1651 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1652 /// are happy to sink it into basic blocks. A cast may be free, but not
1653 /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1654 virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1655 return isNoopAddrSpaceCast(SrcAS, DestAS);
1658 /// Return true if the pointer arguments to CI should be aligned by aligning
1659 /// the object whose address is being passed. If so then MinSize is set to the
1660 /// minimum size the object must be to be aligned and PrefAlign is set to the
1661 /// preferred alignment.
1662 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1663 unsigned & /*PrefAlign*/) const {
1667 //===--------------------------------------------------------------------===//
1668 /// \name Helpers for TargetTransformInfo implementations
1671 /// Get the ISD node that corresponds to the Instruction class opcode.
1672 int InstructionOpcodeToISD(unsigned Opcode) const;
1674 /// Estimate the cost of type-legalization and the legalized type.
1675 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1680 //===--------------------------------------------------------------------===//
1681 /// \name Helpers for atomic expansion.
1684 /// Returns the maximum atomic operation size (in bits) supported by
1685 /// the backend. Atomic operations greater than this size (as well
1686 /// as ones that are not naturally aligned), will be expanded by
1687 /// AtomicExpandPass into an __atomic_* library call.
1688 unsigned getMaxAtomicSizeInBitsSupported() const {
1689 return MaxAtomicSizeInBitsSupported;
1692 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1693 /// the backend supports. Any smaller operations are widened in
1694 /// AtomicExpandPass.
1696 /// Note that *unlike* operations above the maximum size, atomic ops
1697 /// are still natively supported below the minimum; they just
1698 /// require a more complex expansion.
1699 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1701 /// Whether the target supports unaligned atomic operations.
1702 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1704 /// Whether AtomicExpandPass should automatically insert fences and reduce
1705 /// ordering for this atomic. This should be true for most architectures with
1706 /// weak memory ordering. Defaults to false.
1707 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1711 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1712 /// corresponding pointee type. This may entail some non-trivial operations to
1713 /// truncate or reconstruct types that will be illegal in the backend. See
1714 /// ARMISelLowering for an example implementation.
1715 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1716 AtomicOrdering Ord) const {
1717 llvm_unreachable("Load linked unimplemented on this target");
1720 /// Perform a store-conditional operation to Addr. Return the status of the
1721 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1722 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1723 Value *Addr, AtomicOrdering Ord) const {
1724 llvm_unreachable("Store conditional unimplemented on this target");
1727 /// Perform a masked atomicrmw using a target-specific intrinsic. This
1728 /// represents the core LL/SC loop which will be lowered at a late stage by
1730 virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1732 Value *AlignedAddr, Value *Incr,
1733 Value *Mask, Value *ShiftAmt,
1734 AtomicOrdering Ord) const {
1735 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1738 /// Perform a masked cmpxchg using a target-specific intrinsic. This
1739 /// represents the core LL/SC loop which will be lowered at a late stage by
1741 virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1742 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1743 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1744 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1747 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1748 /// It is called by AtomicExpandPass before expanding an
1749 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1750 /// if shouldInsertFencesForAtomic returns true.
1752 /// Inst is the original atomic instruction, prior to other expansions that
1753 /// may be performed.
1755 /// This function should either return a nullptr, or a pointer to an IR-level
1756 /// Instruction*. Even complex fence sequences can be represented by a
1757 /// single Instruction* through an intrinsic to be lowered later.
1758 /// Backends should override this method to produce target-specific intrinsic
1759 /// for their fences.
1760 /// FIXME: Please note that the default implementation here in terms of
1761 /// IR-level fences exists for historical/compatibility reasons and is
1762 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1763 /// consistency. For example, consider the following example:
1764 /// atomic<int> x = y = 0;
1765 /// int r1, r2, r3, r4;
1776 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1777 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1778 /// IR-level fences can prevent it.
1780 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1781 AtomicOrdering Ord) const {
1782 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1783 return Builder.CreateFence(Ord);
1788 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1790 AtomicOrdering Ord) const {
1791 if (isAcquireOrStronger(Ord))
1792 return Builder.CreateFence(Ord);
1798 // Emits code that executes when the comparison result in the ll/sc
1799 // expansion of a cmpxchg instruction is such that the store-conditional will
1800 // not execute. This makes it possible to balance out the load-linked with
1801 // a dedicated instruction, if desired.
1802 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1803 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1804 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1806 /// Returns true if the given (atomic) store should be expanded by the
1807 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1808 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1812 /// Returns true if arguments should be sign-extended in lib calls.
1813 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1817 /// Returns true if arguments should be extended in lib calls.
1818 virtual bool shouldExtendTypeInLibCall(EVT Type) const {
1822 /// Returns how the given (atomic) load should be expanded by the
1823 /// IR-level AtomicExpand pass.
1824 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1825 return AtomicExpansionKind::None;
1828 /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1829 /// AtomicExpand pass.
1830 virtual AtomicExpansionKind
1831 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1832 return AtomicExpansionKind::None;
1835 /// Returns how the IR-level AtomicExpand pass should expand the given
1836 /// AtomicRMW, if at all. Default is to never expand.
1837 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1838 return RMW->isFloatingPointOperation() ?
1839 AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1842 /// On some platforms, an AtomicRMW that never actually modifies the value
1843 /// (such as fetch_add of 0) can be turned into a fence followed by an
1844 /// atomic load. This may sound useless, but it makes it possible for the
1845 /// processor to keep the cacheline shared, dramatically improving
1846 /// performance. And such idempotent RMWs are useful for implementing some
1847 /// kinds of locks, see for example (justification + benchmarks):
1848 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1849 /// This method tries doing that transformation, returning the atomic load if
1850 /// it succeeds, and nullptr otherwise.
1851 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1852 /// another round of expansion.
1854 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1858 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1859 /// SIGN_EXTEND, or ANY_EXTEND).
1860 virtual ISD::NodeType getExtendForAtomicOps() const {
1861 return ISD::ZERO_EXTEND;
1866 /// Returns true if we should normalize
1867 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1868 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1869 /// that it saves us from materializing N0 and N1 in an integer register.
1870 /// Targets that are able to perform and/or on flags should return false here.
1871 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1873 // If a target has multiple condition registers, then it likely has logical
1874 // operations on those registers.
1875 if (hasMultipleConditionRegisters())
1877 // Only do the transform if the value won't be split into multiple
1879 LegalizeTypeAction Action = getTypeAction(Context, VT);
1880 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1881 Action != TypeSplitVector;
1884 virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1886 /// Return true if a select of constants (select Cond, C1, C2) should be
1887 /// transformed into simple math ops with the condition value. For example:
1888 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1889 virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1893 /// Return true if it is profitable to transform an integer
1894 /// multiplication-by-constant into simpler operations like shifts and adds.
1895 /// This may be true if the target does not directly support the
1896 /// multiplication operation for the specified type or the sequence of simpler
1897 /// ops is faster than the multiply.
1898 virtual bool decomposeMulByConstant(LLVMContext &Context,
1899 EVT VT, SDValue C) const {
1903 /// Return true if it is more correct/profitable to use strict FP_TO_INT
1904 /// conversion operations - canonicalizing the FP source value instead of
1905 /// converting all cases and then selecting based on value.
1906 /// This may be true if the target throws exceptions for out of bounds
1907 /// conversions or has fast FP CMOV.
1908 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1909 bool IsSigned) const {
1913 //===--------------------------------------------------------------------===//
1914 // TargetLowering Configuration Methods - These methods should be invoked by
1915 // the derived class constructor to configure this object for the target.
1918 /// Specify how the target extends the result of integer and floating point
1919 /// boolean values from i1 to a wider type. See getBooleanContents.
1920 void setBooleanContents(BooleanContent Ty) {
1921 BooleanContents = Ty;
1922 BooleanFloatContents = Ty;
1925 /// Specify how the target extends the result of integer and floating point
1926 /// boolean values from i1 to a wider type. See getBooleanContents.
1927 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1928 BooleanContents = IntTy;
1929 BooleanFloatContents = FloatTy;
1932 /// Specify how the target extends the result of a vector boolean value from a
1933 /// vector of i1 to a wider type. See getBooleanContents.
1934 void setBooleanVectorContents(BooleanContent Ty) {
1935 BooleanVectorContents = Ty;
1938 /// Specify the target scheduling preference.
1939 void setSchedulingPreference(Sched::Preference Pref) {
1940 SchedPreferenceInfo = Pref;
1943 /// Indicate the minimum number of blocks to generate jump tables.
1944 void setMinimumJumpTableEntries(unsigned Val);
1946 /// Indicate the maximum number of entries in jump tables.
1947 /// Set to zero to generate unlimited jump tables.
1948 void setMaximumJumpTableSize(unsigned);
1950 /// If set to a physical register, this specifies the register that
1951 /// llvm.savestack/llvm.restorestack should save and restore.
1952 void setStackPointerRegisterToSaveRestore(unsigned R) {
1953 StackPointerRegisterToSaveRestore = R;
1956 /// Tells the code generator that the target has multiple (allocatable)
1957 /// condition registers that can be used to store the results of comparisons
1958 /// for use by selects and conditional branches. With multiple condition
1959 /// registers, the code generator will not aggressively sink comparisons into
1960 /// the blocks of their users.
1961 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1962 HasMultipleConditionRegisters = hasManyRegs;
1965 /// Tells the code generator that the target has BitExtract instructions.
1966 /// The code generator will aggressively sink "shift"s into the blocks of
1967 /// their users if the users will generate "and" instructions which can be
1968 /// combined with "shift" to BitExtract instructions.
1969 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1970 HasExtractBitsInsn = hasExtractInsn;
1973 /// Tells the code generator not to expand logic operations on comparison
1974 /// predicates into separate sequences that increase the amount of flow
1976 void setJumpIsExpensive(bool isExpensive = true);
1978 /// Tells the code generator which bitwidths to bypass.
1979 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1980 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1983 /// Add the specified register class as an available regclass for the
1984 /// specified value type. This indicates the selector can handle values of
1985 /// that class natively.
1986 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1987 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1988 RegClassForVT[VT.SimpleTy] = RC;
1991 /// Return the largest legal super-reg register class of the register class
1992 /// for the specified type and its associated "cost".
1993 virtual std::pair<const TargetRegisterClass *, uint8_t>
1994 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1996 /// Once all of the register classes are added, this allows us to compute
1997 /// derived properties we expose.
1998 void computeRegisterProperties(const TargetRegisterInfo *TRI);
2000 /// Indicate that the specified operation does not work with the specified
2001 /// type and indicate what to do about it. Note that VT may refer to either
2002 /// the type of a result or that of an operand of Op.
2003 void setOperationAction(unsigned Op, MVT VT,
2004 LegalizeAction Action) {
2005 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
2006 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
2009 /// Indicate that the specified load with extension does not work with the
2010 /// specified type and indicate what to do about it.
2011 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
2012 LegalizeAction Action) {
2013 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
2014 MemVT.isValid() && "Table isn't big enough!");
2015 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2016 unsigned Shift = 4 * ExtType;
2017 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
2018 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
2021 /// Indicate that the specified truncating store does not work with the
2022 /// specified type and indicate what to do about it.
2023 void setTruncStoreAction(MVT ValVT, MVT MemVT,
2024 LegalizeAction Action) {
2025 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
2026 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
2029 /// Indicate that the specified indexed load does or does not work with the
2030 /// specified type and indicate what to do abort it.
2032 /// NOTE: All indexed mode loads are initialized to Expand in
2033 /// TargetLowering.cpp
2034 void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) {
2035 setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
2038 /// Indicate that the specified indexed store does or does not work with the
2039 /// specified type and indicate what to do about it.
2041 /// NOTE: All indexed mode stores are initialized to Expand in
2042 /// TargetLowering.cpp
2043 void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) {
2044 setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
2047 /// Indicate that the specified indexed masked load does or does not work with
2048 /// the specified type and indicate what to do about it.
2050 /// NOTE: All indexed mode masked loads are initialized to Expand in
2051 /// TargetLowering.cpp
2052 void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT,
2053 LegalizeAction Action) {
2054 setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
2057 /// Indicate that the specified indexed masked store does or does not work
2058 /// with the specified type and indicate what to do about it.
2060 /// NOTE: All indexed mode masked stores are initialized to Expand in
2061 /// TargetLowering.cpp
2062 void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT,
2063 LegalizeAction Action) {
2064 setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
2067 /// Indicate that the specified condition code is or isn't supported on the
2068 /// target and indicate what to do about it.
2069 void setCondCodeAction(ISD::CondCode CC, MVT VT,
2070 LegalizeAction Action) {
2071 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
2072 "Table isn't big enough!");
2073 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2074 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2075 /// value and the upper 29 bits index into the second dimension of the array
2076 /// to select what 32-bit value to use.
2077 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2078 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2079 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2082 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2083 /// to trying a larger integer/fp until it can find one that works. If that
2084 /// default is insufficient, this method can be used by the target to override
2086 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2087 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2090 /// Convenience method to set an operation to Promote and specify the type
2091 /// in a single call.
2092 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2093 setOperationAction(Opc, OrigVT, Promote);
2094 AddPromotedToType(Opc, OrigVT, DestVT);
2097 /// Targets should invoke this method for each target independent node that
2098 /// they want to provide a custom DAG combiner for by implementing the
2099 /// PerformDAGCombine virtual method.
2100 void setTargetDAGCombine(ISD::NodeType NT) {
2101 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2102 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2105 /// Set the target's minimum function alignment.
2106 void setMinFunctionAlignment(Align Alignment) {
2107 MinFunctionAlignment = Alignment;
2110 /// Set the target's preferred function alignment. This should be set if
2111 /// there is a performance benefit to higher-than-minimum alignment
2112 void setPrefFunctionAlignment(Align Alignment) {
2113 PrefFunctionAlignment = Alignment;
2116 /// Set the target's preferred loop alignment. Default alignment is one, it
2117 /// means the target does not care about loop alignment. The target may also
2118 /// override getPrefLoopAlignment to provide per-loop values.
2119 void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }
2121 /// Set the minimum stack alignment of an argument.
2122 void setMinStackArgumentAlignment(Align Alignment) {
2123 MinStackArgumentAlignment = Alignment;
2126 /// Set the maximum atomic operation size supported by the
2127 /// backend. Atomic operations greater than this size (as well as
2128 /// ones that are not naturally aligned), will be expanded by
2129 /// AtomicExpandPass into an __atomic_* library call.
2130 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2131 MaxAtomicSizeInBitsSupported = SizeInBits;
2134 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2135 void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2136 MinCmpXchgSizeInBits = SizeInBits;
2139 /// Sets whether unaligned atomic operations are supported.
2140 void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2141 SupportsUnalignedAtomics = UnalignedSupported;
2145 //===--------------------------------------------------------------------===//
2146 // Addressing mode description hooks (used by LSR etc).
2149 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2150 /// instructions reading the address. This allows as much computation as
2151 /// possible to be done in the address mode for that operand. This hook lets
2152 /// targets also pass back when this should be done on intrinsics which
2154 virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2155 SmallVectorImpl<Value*> &/*Ops*/,
2156 Type *&/*AccessTy*/) const {
2160 /// This represents an addressing mode of:
2161 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2162 /// If BaseGV is null, there is no BaseGV.
2163 /// If BaseOffs is zero, there is no base offset.
2164 /// If HasBaseReg is false, there is no base register.
2165 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2168 GlobalValue *BaseGV = nullptr;
2169 int64_t BaseOffs = 0;
2170 bool HasBaseReg = false;
2172 AddrMode() = default;
2175 /// Return true if the addressing mode represented by AM is legal for this
2176 /// target, for a load/store of the specified type.
2178 /// The type may be VoidTy, in which case only return true if the addressing
2179 /// mode is legal for a load/store of any legal type. TODO: Handle
2180 /// pre/postinc as well.
2182 /// If the address space cannot be determined, it will be -1.
2184 /// TODO: Remove default argument
2185 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2186 Type *Ty, unsigned AddrSpace,
2187 Instruction *I = nullptr) const;
2189 /// Return the cost of the scaling factor used in the addressing mode
2190 /// represented by AM for this target, for a load/store of the specified type.
2192 /// If the AM is supported, the return value must be >= 0.
2193 /// If the AM is not supported, it returns a negative value.
2194 /// TODO: Handle pre/postinc as well.
2195 /// TODO: Remove default argument
2196 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2197 Type *Ty, unsigned AS = 0) const {
2198 // Default: assume that any scaling factor used in a legal AM is free.
2199 if (isLegalAddressingMode(DL, AM, Ty, AS))
2204 /// Return true if the specified immediate is legal icmp immediate, that is
2205 /// the target has icmp instructions which can compare a register against the
2206 /// immediate without having to materialize the immediate into a register.
2207 virtual bool isLegalICmpImmediate(int64_t) const {
2211 /// Return true if the specified immediate is legal add immediate, that is the
2212 /// target has add instructions which can add a register with the immediate
2213 /// without having to materialize the immediate into a register.
2214 virtual bool isLegalAddImmediate(int64_t) const {
2218 /// Return true if the specified immediate is legal for the value input of a
2219 /// store instruction.
2220 virtual bool isLegalStoreImmediate(int64_t Value) const {
2221 // Default implementation assumes that at least 0 works since it is likely
2222 // that a zero register exists or a zero immediate is allowed.
2226 /// Return true if it's significantly cheaper to shift a vector by a uniform
2227 /// scalar than by an amount which will vary across each lane. On x86, for
2228 /// example, there is a "psllw" instruction for the former case, but no simple
2229 /// instruction for a general "a << b" operation on vectors.
2230 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2234 /// Returns true if the opcode is a commutative binary operation.
2235 virtual bool isCommutativeBinOp(unsigned Opcode) const {
2236 // FIXME: This should get its info from the td file.
2246 case ISD::SMUL_LOHI:
2247 case ISD::UMUL_LOHI:
2261 case ISD::FMINNUM_IEEE:
2262 case ISD::FMAXNUM_IEEE:
2266 default: return false;
2270 /// Return true if the node is a math/logic binary operator.
2271 virtual bool isBinOp(unsigned Opcode) const {
2272 // A commutative binop must be a binop.
2273 if (isCommutativeBinOp(Opcode))
2275 // These are non-commutative binops.
2294 /// Return true if it's free to truncate a value of type FromTy to type
2295 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2296 /// by referencing its sub-register AX.
2297 /// Targets must return false when FromTy <= ToTy.
2298 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2302 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2303 /// whether a call is in tail position. Typically this means that both results
2304 /// would be assigned to the same register or stack slot, but it could mean
2305 /// the target performs adequate checks of its own before proceeding with the
2306 /// tail call. Targets must return false when FromTy <= ToTy.
2307 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2311 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2315 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2317 /// Return true if the extension represented by \p I is free.
2318 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2319 /// this method can use the context provided by \p I to decide
2320 /// whether or not \p I is free.
2321 /// This method extends the behavior of the is[Z|FP]ExtFree family.
2322 /// In other words, if is[Z|FP]Free returns true, then this method
2323 /// returns true as well. The converse is not true.
2324 /// The target can perform the adequate checks by overriding isExtFreeImpl.
2325 /// \pre \p I must be a sign, zero, or fp extension.
2326 bool isExtFree(const Instruction *I) const {
2327 switch (I->getOpcode()) {
2328 case Instruction::FPExt:
2329 if (isFPExtFree(EVT::getEVT(I->getType()),
2330 EVT::getEVT(I->getOperand(0)->getType())))
2333 case Instruction::ZExt:
2334 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2337 case Instruction::SExt:
2340 llvm_unreachable("Instruction is not an extension");
2342 return isExtFreeImpl(I);
2345 /// Return true if \p Load and \p Ext can form an ExtLoad.
2346 /// For example, in AArch64
2347 /// %L = load i8, i8* %ptr
2348 /// %E = zext i8 %L to i32
2349 /// can be lowered into one load instruction
2351 bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2352 const DataLayout &DL) const {
2353 EVT VT = getValueType(DL, Ext->getType());
2354 EVT LoadVT = getValueType(DL, Load->getType());
2356 // If the load has other users and the truncate is not free, the ext
2357 // probably isn't free.
2358 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2359 !isTruncateFree(Ext->getType(), Load->getType()))
2362 // Check whether the target supports casts folded into loads.
2364 if (isa<ZExtInst>(Ext))
2365 LType = ISD::ZEXTLOAD;
2367 assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2368 LType = ISD::SEXTLOAD;
2371 return isLoadExtLegal(LType, VT, LoadVT);
2374 /// Return true if any actual instruction that defines a value of type FromTy
2375 /// implicitly zero-extends the value to ToTy in the result register.
2377 /// The function should return true when it is likely that the truncate can
2378 /// be freely folded with an instruction defining a value of FromTy. If
2379 /// the defining instruction is unknown (because you're looking at a
2380 /// function argument, PHI, etc.) then the target may require an
2381 /// explicit truncate, which is not necessarily free, but this function
2382 /// does not deal with those cases.
2383 /// Targets must return false when FromTy >= ToTy.
2384 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2388 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2392 /// Return true if sign-extension from FromTy to ToTy is cheaper than
2394 virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2398 /// Return true if sinking I's operands to the same basic block as I is
2399 /// profitable, e.g. because the operands can be folded into a target
2400 /// instruction during instruction selection. After calling the function
2401 /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2403 virtual bool shouldSinkOperands(Instruction *I,
2404 SmallVectorImpl<Use *> &Ops) const {
2408 /// Return true if the target supplies and combines to a paired load
2409 /// two loaded values of type LoadedType next to each other in memory.
2410 /// RequiredAlignment gives the minimal alignment constraints that must be met
2411 /// to be able to select this paired load.
2413 /// This information is *not* used to generate actual paired loads, but it is
2414 /// used to generate a sequence of loads that is easier to combine into a
2416 /// For instance, something like this:
2417 /// a = load i64* addr
2418 /// b = trunc i64 a to i32
2419 /// c = lshr i64 a, 32
2420 /// d = trunc i64 c to i32
2421 /// will be optimized into:
2422 /// b = load i32* addr1
2423 /// d = load i32* addr2
2424 /// Where addr1 = addr2 +/- sizeof(i32).
2426 /// In other words, unless the target performs a post-isel load combining,
2427 /// this information should not be provided because it will generate more
2429 virtual bool hasPairedLoad(EVT /*LoadedType*/,
2430 unsigned & /*RequiredAlignment*/) const {
2434 /// Return true if the target has a vector blend instruction.
2435 virtual bool hasVectorBlend() const { return false; }
2437 /// Get the maximum supported factor for interleaved memory accesses.
2438 /// Default to be the minimum interleave factor: 2.
2439 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2441 /// Lower an interleaved load to target specific intrinsics. Return
2442 /// true on success.
2444 /// \p LI is the vector load instruction.
2445 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2446 /// \p Indices is the corresponding indices for each shufflevector.
2447 /// \p Factor is the interleave factor.
2448 virtual bool lowerInterleavedLoad(LoadInst *LI,
2449 ArrayRef<ShuffleVectorInst *> Shuffles,
2450 ArrayRef<unsigned> Indices,
2451 unsigned Factor) const {
2455 /// Lower an interleaved store to target specific intrinsics. Return
2456 /// true on success.
2458 /// \p SI is the vector store instruction.
2459 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2460 /// \p Factor is the interleave factor.
2461 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2462 unsigned Factor) const {
2466 /// Return true if zero-extending the specific node Val to type VT2 is free
2467 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2468 /// because it's folded such as X86 zero-extending loads).
2469 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2470 return isZExtFree(Val.getValueType(), VT2);
2473 /// Return true if an fpext operation is free (for instance, because
2474 /// single-precision floating-point numbers are implicitly extended to
2475 /// double-precision).
2476 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2477 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2478 "invalid fpext types");
2482 /// Return true if an fpext operation input to an \p Opcode operation is free
2483 /// (for instance, because half-precision floating-point numbers are
2484 /// implicitly extended to float-precision) for an FMA instruction.
2485 virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
2486 EVT DestVT, EVT SrcVT) const {
2487 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2488 "invalid fpext types");
2489 return isFPExtFree(DestVT, SrcVT);
2492 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2493 /// extend node) is profitable.
2494 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2496 /// Return true if an fneg operation is free to the point where it is never
2497 /// worthwhile to replace it with a bitwise operation.
2498 virtual bool isFNegFree(EVT VT) const {
2499 assert(VT.isFloatingPoint());
2503 /// Return true if an fabs operation is free to the point where it is never
2504 /// worthwhile to replace it with a bitwise operation.
2505 virtual bool isFAbsFree(EVT VT) const {
2506 assert(VT.isFloatingPoint());
2510 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2511 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2512 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2514 /// NOTE: This may be called before legalization on types for which FMAs are
2515 /// not legal, but should return true if those types will eventually legalize
2516 /// to types that support FMAs. After legalization, it will only be called on
2517 /// types that support FMAs (via Legal or Custom actions)
2518 virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
2524 virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const {
2528 /// Returns true if the FADD or FSUB node passed could legally be combined with
2529 /// an fmul to form an ISD::FMAD.
2530 virtual bool isFMADLegalForFAddFSub(const SelectionDAG &DAG,
2531 const SDNode *N) const {
2532 assert(N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB);
2533 return isOperationLegal(ISD::FMAD, N->getValueType(0));
2536 /// Return true if it's profitable to narrow operations of type VT1 to
2537 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2539 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2543 /// Return true if it is beneficial to convert a load of a constant to
2544 /// just the constant itself.
2545 /// On some targets it might be more efficient to use a combination of
2546 /// arithmetic instructions to materialize the constant instead of loading it
2547 /// from a constant pool.
2548 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2553 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2554 /// from this source type with this index. This is needed because
2555 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2556 /// the first element, and only the target knows which lowering is cheap.
2557 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2558 unsigned Index) const {
2562 /// Try to convert an extract element of a vector binary operation into an
2563 /// extract element followed by a scalar operation.
2564 virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2568 /// Return true if extraction of a scalar element from the given vector type
2569 /// at the given index is cheap. For example, if scalar operations occur on
2570 /// the same register file as vector operations, then an extract element may
2571 /// be a sub-register rename rather than an actual instruction.
2572 virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2576 /// Try to convert math with an overflow comparison into the corresponding DAG
2577 /// node operation. Targets may want to override this independently of whether
2578 /// the operation is legal/custom for the given type because it may obscure
2579 /// matching of other patterns.
2580 virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2581 // TODO: The default logic is inherited from code in CodeGenPrepare.
2582 // The opcode should not make a difference by default?
2583 if (Opcode != ISD::UADDO)
2586 // Allow the transform as long as we have an integer type that is not
2587 // obviously illegal and unsupported.
2590 return VT.isSimple() || !isOperationExpand(Opcode, VT);
2593 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2594 // even if the vector itself has multiple uses.
2595 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2599 // Return true if CodeGenPrepare should consider splitting large offset of a
2600 // GEP to make the GEP fit into the addressing mode and can be sunk into the
2601 // same blocks of its users.
2602 virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2604 /// Return true if creating a shift of the type by the given
2605 /// amount is not profitable.
2606 virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const {
2610 //===--------------------------------------------------------------------===//
2611 // Runtime Library hooks
2614 /// Rename the default libcall routine name for the specified libcall.
2615 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2616 LibcallRoutineNames[Call] = Name;
2619 /// Get the libcall routine name for the specified libcall.
2620 const char *getLibcallName(RTLIB::Libcall Call) const {
2621 return LibcallRoutineNames[Call];
2624 /// Override the default CondCode to be used to test the result of the
2625 /// comparison libcall against zero.
2626 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2627 CmpLibcallCCs[Call] = CC;
2630 /// Get the CondCode that's to be used to test the result of the comparison
2631 /// libcall against zero.
2632 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2633 return CmpLibcallCCs[Call];
2636 /// Set the CallingConv that should be used for the specified libcall.
2637 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2638 LibcallCallingConvs[Call] = CC;
2641 /// Get the CallingConv that should be used for the specified libcall.
2642 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2643 return LibcallCallingConvs[Call];
2646 /// Execute target specific actions to finalize target lowering.
2647 /// This is used to set extra flags in MachineFrameInformation and freezing
2648 /// the set of reserved registers.
2649 /// The default implementation just freezes the set of reserved registers.
2650 virtual void finalizeLowering(MachineFunction &MF) const;
2653 const TargetMachine &TM;
2655 /// Tells the code generator that the target has multiple (allocatable)
2656 /// condition registers that can be used to store the results of comparisons
2657 /// for use by selects and conditional branches. With multiple condition
2658 /// registers, the code generator will not aggressively sink comparisons into
2659 /// the blocks of their users.
2660 bool HasMultipleConditionRegisters;
2662 /// Tells the code generator that the target has BitExtract instructions.
2663 /// The code generator will aggressively sink "shift"s into the blocks of
2664 /// their users if the users will generate "and" instructions which can be
2665 /// combined with "shift" to BitExtract instructions.
2666 bool HasExtractBitsInsn;
2668 /// Tells the code generator to bypass slow divide or remainder
2669 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2670 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2671 /// div/rem when the operands are positive and less than 256.
2672 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2674 /// Tells the code generator that it shouldn't generate extra flow control
2675 /// instructions and should attempt to combine flow control instructions via
2677 bool JumpIsExpensive;
2679 /// Information about the contents of the high-bits in boolean values held in
2680 /// a type wider than i1. See getBooleanContents.
2681 BooleanContent BooleanContents;
2683 /// Information about the contents of the high-bits in boolean values held in
2684 /// a type wider than i1. See getBooleanContents.
2685 BooleanContent BooleanFloatContents;
2687 /// Information about the contents of the high-bits in boolean vector values
2688 /// when the element type is wider than i1. See getBooleanContents.
2689 BooleanContent BooleanVectorContents;
2691 /// The target scheduling preference: shortest possible total cycles or lowest
2693 Sched::Preference SchedPreferenceInfo;
2695 /// The minimum alignment that any argument on the stack needs to have.
2696 Align MinStackArgumentAlignment;
2698 /// The minimum function alignment (used when optimizing for size, and to
2699 /// prevent explicitly provided alignment from leading to incorrect code).
2700 Align MinFunctionAlignment;
2702 /// The preferred function alignment (used when alignment unspecified and
2703 /// optimizing for speed).
2704 Align PrefFunctionAlignment;
2706 /// The preferred loop alignment (in log2 bot in bytes).
2707 Align PrefLoopAlignment;
2709 /// Size in bits of the maximum atomics size the backend supports.
2710 /// Accesses larger than this will be expanded by AtomicExpandPass.
2711 unsigned MaxAtomicSizeInBitsSupported;
2713 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2714 /// backend supports.
2715 unsigned MinCmpXchgSizeInBits;
2717 /// This indicates if the target supports unaligned atomic operations.
2718 bool SupportsUnalignedAtomics;
2720 /// If set to a physical register, this specifies the register that
2721 /// llvm.savestack/llvm.restorestack should save and restore.
2722 unsigned StackPointerRegisterToSaveRestore;
2724 /// This indicates the default register class to use for each ValueType the
2725 /// target supports natively.
2726 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2727 uint16_t NumRegistersForVT[MVT::LAST_VALUETYPE];
2728 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2730 /// This indicates the "representative" register class to use for each
2731 /// ValueType the target supports natively. This information is used by the
2732 /// scheduler to track register pressure. By default, the representative
2733 /// register class is the largest legal super-reg register class of the
2734 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2735 /// representative class would be GR32.
2736 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2738 /// This indicates the "cost" of the "representative" register class for each
2739 /// ValueType. The cost is used by the scheduler to approximate register
2741 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2743 /// For any value types we are promoting or expanding, this contains the value
2744 /// type that we are changing to. For Expanded types, this contains one step
2745 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2746 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2747 /// the same type (e.g. i32 -> i32).
2748 MVT TransformToType[MVT::LAST_VALUETYPE];
2750 /// For each operation and each value type, keep a LegalizeAction that
2751 /// indicates how instruction selection should deal with the operation. Most
2752 /// operations are Legal (aka, supported natively by the target), but
2753 /// operations that are not should be described. Note that operations on
2754 /// non-legal value types are not described here.
2755 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2757 /// For each load extension type and each value type, keep a LegalizeAction
2758 /// that indicates how instruction selection should deal with a load of a
2759 /// specific value type and extension type. Uses 4-bits to store the action
2760 /// for each of the 4 load ext types.
2761 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2763 /// For each value type pair keep a LegalizeAction that indicates whether a
2764 /// truncating store of a specific value type and truncating type is legal.
2765 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2767 /// For each indexed mode and each value type, keep a quad of LegalizeAction
2768 /// that indicates how instruction selection should deal with the load /
2769 /// store / maskedload / maskedstore.
2771 /// The first dimension is the value_type for the reference. The second
2772 /// dimension represents the various modes for load store.
2773 uint16_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2775 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2776 /// indicates how instruction selection should deal with the condition code.
2778 /// Because each CC action takes up 4 bits, we need to have the array size be
2779 /// large enough to fit all of the value types. This can be done by rounding
2780 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2781 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2783 ValueTypeActionImpl ValueTypeActions;
2786 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2788 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2789 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2792 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2794 /// For operations that must be promoted to a specific type, this holds the
2795 /// destination type. This map should be sparse, so don't hold it as an
2798 /// Targets add entries to this map with AddPromotedToType(..), clients access
2799 /// this with getTypeToPromoteTo(..).
2800 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2803 /// Stores the name each libcall.
2804 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2806 /// The ISD::CondCode that should be used to test the result of each of the
2807 /// comparison libcall against zero.
2808 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2810 /// Stores the CallingConv that should be used for each libcall.
2811 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2813 /// Set default libcall names and calling conventions.
2814 void InitLibcalls(const Triple &TT);
2816 /// The bits of IndexedModeActions used to store the legalisation actions
2817 /// We store the data as | ML | MS | L | S | each taking 4 bits.
2818 enum IndexedModeActionsBits {
2821 IMAB_MaskedStore = 8,
2822 IMAB_MaskedLoad = 12
2825 void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift,
2826 LegalizeAction Action) {
2827 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2828 (unsigned)Action < 0xf && "Table isn't big enough!");
2829 unsigned Ty = (unsigned)VT.SimpleTy;
2830 IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift);
2831 IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift;
2834 LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT,
2835 unsigned Shift) const {
2836 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
2837 "Table isn't big enough!");
2838 unsigned Ty = (unsigned)VT.SimpleTy;
2839 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf);
2843 /// Return true if the extension represented by \p I is free.
2844 /// \pre \p I is a sign, zero, or fp extension and
2845 /// is[Z|FP]ExtFree of the related types is not true.
2846 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2848 /// Depth that GatherAllAliases should should continue looking for chain
2849 /// dependencies when trying to find a more preferable chain. As an
2850 /// approximation, this should be more than the number of consecutive stores
2851 /// expected to be merged.
2852 unsigned GatherAllAliasesMaxDepth;
2854 /// \brief Specify maximum number of store instructions per memset call.
2856 /// When lowering \@llvm.memset this field specifies the maximum number of
2857 /// store operations that may be substituted for the call to memset. Targets
2858 /// must set this value based on the cost threshold for that target. Targets
2859 /// should assume that the memset will be done using as many of the largest
2860 /// store operations first, followed by smaller ones, if necessary, per
2861 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2862 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2863 /// store. This only applies to setting a constant array of a constant size.
2864 unsigned MaxStoresPerMemset;
2865 /// Likewise for functions with the OptSize attribute.
2866 unsigned MaxStoresPerMemsetOptSize;
2868 /// \brief Specify maximum number of store instructions per memcpy call.
2870 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2871 /// store operations that may be substituted for a call to memcpy. Targets
2872 /// must set this value based on the cost threshold for that target. Targets
2873 /// should assume that the memcpy will be done using as many of the largest
2874 /// store operations first, followed by smaller ones, if necessary, per
2875 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2876 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2877 /// and one 1-byte store. This only applies to copying a constant array of
2879 unsigned MaxStoresPerMemcpy;
2880 /// Likewise for functions with the OptSize attribute.
2881 unsigned MaxStoresPerMemcpyOptSize;
2882 /// \brief Specify max number of store instructions to glue in inlined memcpy.
2884 /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2885 /// of store instructions to keep together. This helps in pairing and
2886 // vectorization later on.
2887 unsigned MaxGluedStoresPerMemcpy = 0;
2889 /// \brief Specify maximum number of load instructions per memcmp call.
2891 /// When lowering \@llvm.memcmp this field specifies the maximum number of
2892 /// pairs of load operations that may be substituted for a call to memcmp.
2893 /// Targets must set this value based on the cost threshold for that target.
2894 /// Targets should assume that the memcmp will be done using as many of the
2895 /// largest load operations first, followed by smaller ones, if necessary, per
2896 /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2897 /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2898 /// and one 1-byte load. This only applies to copying a constant array of
2900 unsigned MaxLoadsPerMemcmp;
2901 /// Likewise for functions with the OptSize attribute.
2902 unsigned MaxLoadsPerMemcmpOptSize;
2904 /// \brief Specify maximum number of store instructions per memmove call.
2906 /// When lowering \@llvm.memmove this field specifies the maximum number of
2907 /// store instructions that may be substituted for a call to memmove. Targets
2908 /// must set this value based on the cost threshold for that target. Targets
2909 /// should assume that the memmove will be done using as many of the largest
2910 /// store operations first, followed by smaller ones, if necessary, per
2911 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2912 /// with 8-bit alignment would result in nine 1-byte stores. This only
2913 /// applies to copying a constant array of constant size.
2914 unsigned MaxStoresPerMemmove;
2915 /// Likewise for functions with the OptSize attribute.
2916 unsigned MaxStoresPerMemmoveOptSize;
2918 /// Tells the code generator that select is more expensive than a branch if
2919 /// the branch is usually predicted right.
2920 bool PredictableSelectIsExpensive;
2922 /// \see enableExtLdPromotion.
2923 bool EnableExtLdPromotion;
2925 /// Return true if the value types that can be represented by the specified
2926 /// register class are all legal.
2927 bool isLegalRC(const TargetRegisterInfo &TRI,
2928 const TargetRegisterClass &RC) const;
2930 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2931 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2932 MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2933 MachineBasicBlock *MBB) const;
2935 /// Replace/modify the XRay custom event operands with target-dependent
2937 MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2938 MachineBasicBlock *MBB) const;
2940 /// Replace/modify the XRay typed event operands with target-dependent
2942 MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2943 MachineBasicBlock *MBB) const;
2945 bool IsStrictFPEnabled;
2948 /// This class defines information used to lower LLVM code to legal SelectionDAG
2949 /// operators that the target instruction selector can accept natively.
2951 /// This class also defines callbacks that targets must implement to lower
2952 /// target-specific constructs to SelectionDAG operators.
2953 class TargetLowering : public TargetLoweringBase {
2955 struct DAGCombinerInfo;
2956 struct MakeLibCallOptions;
2958 TargetLowering(const TargetLowering &) = delete;
2959 TargetLowering &operator=(const TargetLowering &) = delete;
2961 explicit TargetLowering(const TargetMachine &TM);
2963 bool isPositionIndependent() const;
2965 virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2966 FunctionLoweringInfo *FLI,
2967 LegacyDivergenceAnalysis *DA) const {
2971 virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2975 /// Returns true by value, base pointer and offset pointer and addressing mode
2976 /// by reference if the node's address can be legally represented as
2977 /// pre-indexed load / store address.
2978 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2979 SDValue &/*Offset*/,
2980 ISD::MemIndexedMode &/*AM*/,
2981 SelectionDAG &/*DAG*/) const {
2985 /// Returns true by value, base pointer and offset pointer and addressing mode
2986 /// by reference if this node can be combined with a load / store to form a
2987 /// post-indexed load / store.
2988 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2990 SDValue &/*Offset*/,
2991 ISD::MemIndexedMode &/*AM*/,
2992 SelectionDAG &/*DAG*/) const {
2996 /// Returns true if the specified base+offset is a legal indexed addressing
2997 /// mode for this target. \p MI is the load or store instruction that is being
2998 /// considered for transformation.
2999 virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
3000 bool IsPre, MachineRegisterInfo &MRI) const {
3004 /// Return the entry encoding for a jump table in the current function. The
3005 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
3006 virtual unsigned getJumpTableEncoding() const;
3008 virtual const MCExpr *
3009 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
3010 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
3011 MCContext &/*Ctx*/) const {
3012 llvm_unreachable("Need to implement this hook if target has custom JTIs");
3015 /// Returns relocation base for the given PIC jumptable.
3016 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
3017 SelectionDAG &DAG) const;
3019 /// This returns the relocation base for the given PIC jumptable, the same as
3020 /// getPICJumpTableRelocBase, but as an MCExpr.
3021 virtual const MCExpr *
3022 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3023 unsigned JTI, MCContext &Ctx) const;
3025 /// Return true if folding a constant offset with the given GlobalAddress is
3026 /// legal. It is frequently not legal in PIC relocation models.
3027 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
3029 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
3030 SDValue &Chain) const;
3032 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3033 SDValue &NewRHS, ISD::CondCode &CCCode,
3034 const SDLoc &DL, const SDValue OldLHS,
3035 const SDValue OldRHS) const;
3037 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3038 SDValue &NewRHS, ISD::CondCode &CCCode,
3039 const SDLoc &DL, const SDValue OldLHS,
3040 const SDValue OldRHS, SDValue &Chain,
3041 bool IsSignaling = false) const;
3043 /// Returns a pair of (return value, chain).
3044 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
3045 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
3046 EVT RetVT, ArrayRef<SDValue> Ops,
3047 MakeLibCallOptions CallOptions,
3049 SDValue Chain = SDValue()) const;
3051 /// Check whether parameters to a call that are passed in callee saved
3052 /// registers are the same as from the calling function. This needs to be
3053 /// checked for tail call eligibility.
3054 bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
3055 const uint32_t *CallerPreservedMask,
3056 const SmallVectorImpl<CCValAssign> &ArgLocs,
3057 const SmallVectorImpl<SDValue> &OutVals) const;
3059 //===--------------------------------------------------------------------===//
3060 // TargetLowering Optimization Methods
3063 /// A convenience struct that encapsulates a DAG, and two SDValues for
3064 /// returning information from TargetLowering to its clients that want to
3066 struct TargetLoweringOpt {
3073 explicit TargetLoweringOpt(SelectionDAG &InDAG,
3075 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
3077 bool LegalTypes() const { return LegalTys; }
3078 bool LegalOperations() const { return LegalOps; }
3080 bool CombineTo(SDValue O, SDValue N) {
3087 /// Determines the optimal series of memory ops to replace the memset / memcpy.
3088 /// Return true if the number of memory ops is below the threshold (Limit).
3089 /// It returns the types of the sequence of memory ops to perform
3090 /// memset / memcpy by reference.
3091 bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
3092 unsigned Limit, uint64_t Size,
3093 unsigned DstAlign, unsigned SrcAlign,
3098 unsigned DstAS, unsigned SrcAS,
3099 const AttributeList &FuncAttributes) const;
3101 /// Check to see if the specified operand of the specified instruction is a
3102 /// constant integer. If so, check to see if there are any bits set in the
3103 /// constant that are not demanded. If so, shrink the constant and return
3105 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3106 TargetLoweringOpt &TLO) const;
3108 // Target hook to do target-specific const optimization, which is called by
3109 // ShrinkDemandedConstant. This function should return true if the target
3110 // doesn't want ShrinkDemandedConstant to further optimize the constant.
3111 virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3112 TargetLoweringOpt &TLO) const {
3116 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3117 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3118 /// generalized for targets with other types of implicit widening casts.
3119 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3120 TargetLoweringOpt &TLO) const;
3122 /// Look at Op. At this point, we know that only the DemandedBits bits of the
3123 /// result of Op are ever used downstream. If we can use this information to
3124 /// simplify Op, create a new simplified DAG node and return true, returning
3125 /// the original and new nodes in Old and New. Otherwise, analyze the
3126 /// expression and return a mask of KnownOne and KnownZero bits for the
3127 /// expression (used to simplify the caller). The KnownZero/One bits may only
3128 /// be accurate for those bits in the Demanded masks.
3129 /// \p AssumeSingleUse When this parameter is true, this function will
3130 /// attempt to simplify \p Op even if there are multiple uses.
3131 /// Callers are responsible for correctly updating the DAG based on the
3132 /// results of this function, because simply replacing replacing TLO.Old
3133 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3134 /// has multiple uses.
3135 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3136 const APInt &DemandedElts, KnownBits &Known,
3137 TargetLoweringOpt &TLO, unsigned Depth = 0,
3138 bool AssumeSingleUse = false) const;
3140 /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3141 /// Adds Op back to the worklist upon success.
3142 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3143 KnownBits &Known, TargetLoweringOpt &TLO,
3145 bool AssumeSingleUse = false) const;
3147 /// Helper wrapper around SimplifyDemandedBits.
3148 /// Adds Op back to the worklist upon success.
3149 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
3150 DAGCombinerInfo &DCI) const;
3152 /// More limited version of SimplifyDemandedBits that can be used to "look
3153 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3154 /// bitwise ops etc.
3155 SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3156 const APInt &DemandedElts,
3158 unsigned Depth) const;
3160 /// Look at Vector Op. At this point, we know that only the DemandedElts
3161 /// elements of the result of Op are ever used downstream. If we can use
3162 /// this information to simplify Op, create a new simplified DAG node and
3163 /// return true, storing the original and new nodes in TLO.
3164 /// Otherwise, analyze the expression and return a mask of KnownUndef and
3165 /// KnownZero elements for the expression (used to simplify the caller).
3166 /// The KnownUndef/Zero elements may only be accurate for those bits
3167 /// in the DemandedMask.
3168 /// \p AssumeSingleUse When this parameter is true, this function will
3169 /// attempt to simplify \p Op even if there are multiple uses.
3170 /// Callers are responsible for correctly updating the DAG based on the
3171 /// results of this function, because simply replacing replacing TLO.Old
3172 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3173 /// has multiple uses.
3174 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3175 APInt &KnownUndef, APInt &KnownZero,
3176 TargetLoweringOpt &TLO, unsigned Depth = 0,
3177 bool AssumeSingleUse = false) const;
3179 /// Helper wrapper around SimplifyDemandedVectorElts.
3180 /// Adds Op back to the worklist upon success.
3181 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3182 APInt &KnownUndef, APInt &KnownZero,
3183 DAGCombinerInfo &DCI) const;
3185 /// Determine which of the bits specified in Mask are known to be either zero
3186 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3187 /// argument allows us to only collect the known bits that are shared by the
3188 /// requested vector elements.
3189 virtual void computeKnownBitsForTargetNode(const SDValue Op,
3191 const APInt &DemandedElts,
3192 const SelectionDAG &DAG,
3193 unsigned Depth = 0) const;
3194 /// Determine which of the bits specified in Mask are known to be either zero
3195 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3196 /// argument allows us to only collect the known bits that are shared by the
3197 /// requested vector elements. This is for GISel.
3198 virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis,
3199 Register R, KnownBits &Known,
3200 const APInt &DemandedElts,
3201 const MachineRegisterInfo &MRI,
3202 unsigned Depth = 0) const;
3204 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3205 /// Default implementation computes low bits based on alignment
3206 /// information. This should preserve known bits passed into it.
3207 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3209 const APInt &DemandedElts,
3210 const SelectionDAG &DAG,
3211 unsigned Depth = 0) const;
3213 /// This method can be implemented by targets that want to expose additional
3214 /// information about sign bits to the DAG Combiner. The DemandedElts
3215 /// argument allows us to only collect the minimum sign bits that are shared
3216 /// by the requested vector elements.
3217 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3218 const APInt &DemandedElts,
3219 const SelectionDAG &DAG,
3220 unsigned Depth = 0) const;
3222 /// Attempt to simplify any target nodes based on the demanded vector
3223 /// elements, returning true on success. Otherwise, analyze the expression and
3224 /// return a mask of KnownUndef and KnownZero elements for the expression
3225 /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3226 /// accurate for those bits in the DemandedMask.
3227 virtual bool SimplifyDemandedVectorEltsForTargetNode(
3228 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3229 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3231 /// Attempt to simplify any target nodes based on the demanded bits/elts,
3232 /// returning true on success. Otherwise, analyze the
3233 /// expression and return a mask of KnownOne and KnownZero bits for the
3234 /// expression (used to simplify the caller). The KnownZero/One bits may only
3235 /// be accurate for those bits in the Demanded masks.
3236 virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3237 const APInt &DemandedBits,
3238 const APInt &DemandedElts,
3240 TargetLoweringOpt &TLO,
3241 unsigned Depth = 0) const;
3243 /// More limited version of SimplifyDemandedBits that can be used to "look
3244 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3245 /// bitwise ops etc.
3246 virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
3247 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3248 SelectionDAG &DAG, unsigned Depth) const;
3250 /// Tries to build a legal vector shuffle using the provided parameters
3251 /// or equivalent variations. The Mask argument maybe be modified as the
3252 /// function tries different variations.
3253 /// Returns an empty SDValue if the operation fails.
3254 SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
3255 SDValue N1, MutableArrayRef<int> Mask,
3256 SelectionDAG &DAG) const;
3258 /// This method returns the constant pool value that will be loaded by LD.
3259 /// NOTE: You must check for implicit extensions of the constant by LD.
3260 virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
3262 /// If \p SNaN is false, \returns true if \p Op is known to never be any
3263 /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3265 virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3266 const SelectionDAG &DAG,
3268 unsigned Depth = 0) const;
3269 struct DAGCombinerInfo {
3270 void *DC; // The DAG Combiner object.
3272 bool CalledByLegalizer;
3277 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3278 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3280 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3281 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3282 bool isAfterLegalizeDAG() const { return Level >= AfterLegalizeDAG; }
3283 CombineLevel getDAGCombineLevel() { return Level; }
3284 bool isCalledByLegalizer() const { return CalledByLegalizer; }
3286 void AddToWorklist(SDNode *N);
3287 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3288 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3289 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3291 bool recursivelyDeleteUnusedNodes(SDNode *N);
3293 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3296 /// Return if the N is a constant or constant vector equal to the true value
3297 /// from getBooleanContents().
3298 bool isConstTrueVal(const SDNode *N) const;
3300 /// Return if the N is a constant or constant vector equal to the false value
3301 /// from getBooleanContents().
3302 bool isConstFalseVal(const SDNode *N) const;
3304 /// Return if \p N is a True value when extended to \p VT.
3305 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3307 /// Try to simplify a setcc built with the specified operands and cc. If it is
3308 /// unable to simplify it, return a null SDValue.
3309 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3310 bool foldBooleans, DAGCombinerInfo &DCI,
3311 const SDLoc &dl) const;
3313 // For targets which wrap address, unwrap for analysis.
3314 virtual SDValue unwrapAddress(SDValue N) const { return N; }
3316 /// Returns true (and the GlobalValue and the offset) if the node is a
3317 /// GlobalAddress + offset.
3319 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3321 /// This method will be invoked for all target nodes and for any
3322 /// target-independent nodes that the target has registered with invoke it
3325 /// The semantics are as follows:
3327 /// SDValue.Val == 0 - No change was made
3328 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3329 /// otherwise - N should be replaced by the returned Operand.
3331 /// In addition, methods provided by DAGCombinerInfo may be used to perform
3332 /// more complex transformations.
3334 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3336 /// Return true if it is profitable to move this shift by a constant amount
3337 /// though its operand, adjusting any immediate operands as necessary to
3338 /// preserve semantics. This transformation may not be desirable if it
3339 /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3340 /// extraction in AArch64). By default, it returns true.
3342 /// @param N the shift node
3343 /// @param Level the current DAGCombine legalization level.
3344 virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3345 CombineLevel Level) const {
3349 // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3350 // to a shuffle and a truncate.
3351 // Example of such a combine:
3352 // v4i32 build_vector((extract_elt V, 1),
3353 // (extract_elt V, 3),
3354 // (extract_elt V, 5),
3355 // (extract_elt V, 7))
3357 // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3358 virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3359 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3363 /// Return true if the target has native support for the specified value type
3364 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3365 /// i16 is legal, but undesirable since i16 instruction encodings are longer
3366 /// and some i16 instructions are slow.
3367 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3368 // By default, assume all legal types are desirable.
3369 return isTypeLegal(VT);
3372 /// Return true if it is profitable for dag combiner to transform a floating
3373 /// point op of specified opcode to a equivalent op of an integer
3374 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3375 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3380 /// This method query the target whether it is beneficial for dag combiner to
3381 /// promote the specified node. If true, it should return the desired
3382 /// promotion type by reference.
3383 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3387 /// Return true if the target supports swifterror attribute. It optimizes
3388 /// loads and stores to reading and writing a specific register.
3389 virtual bool supportSwiftError() const {
3393 /// Return true if the target supports that a subset of CSRs for the given
3394 /// machine function is handled explicitly via copies.
3395 virtual bool supportSplitCSR(MachineFunction *MF) const {
3399 /// Perform necessary initialization to handle a subset of CSRs explicitly
3400 /// via copies. This function is called at the beginning of instruction
3402 virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3403 llvm_unreachable("Not Implemented");
3406 /// Insert explicit copies in entry and exit blocks. We copy a subset of
3407 /// CSRs to virtual registers in the entry block, and copy them back to
3408 /// physical registers in the exit blocks. This function is called at the end
3409 /// of instruction selection.
3410 virtual void insertCopiesSplitCSR(
3411 MachineBasicBlock *Entry,
3412 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3413 llvm_unreachable("Not Implemented");
3416 /// Return 1 if we can compute the negated form of the specified expression
3417 /// for the same cost as the expression itself, or 2 if we can compute the
3418 /// negated form more cheaply than the expression itself. Else return 0.
3419 virtual char isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
3420 bool LegalOperations, bool ForCodeSize,
3421 unsigned Depth = 0) const;
3423 /// If isNegatibleForFree returns true, return the newly negated expression.
3424 virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
3425 bool LegalOperations, bool ForCodeSize,
3426 unsigned Depth = 0) const;
3428 //===--------------------------------------------------------------------===//
3429 // Lowering methods - These methods must be implemented by targets so that
3430 // the SelectionDAGBuilder code knows how to lower these.
3433 /// This hook must be implemented to lower the incoming (formal) arguments,
3434 /// described by the Ins array, into the specified DAG. The implementation
3435 /// should fill in the InVals array with legal-type argument values, and
3436 /// return the resulting token chain value.
3437 virtual SDValue LowerFormalArguments(
3438 SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3439 const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3440 SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3441 llvm_unreachable("Not Implemented");
3444 /// This structure contains all information that is necessary for lowering
3445 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3446 /// needs to lower a call, and targets will see this struct in their LowerCall
3448 struct CallLoweringInfo {
3450 Type *RetTy = nullptr;
3455 bool DoesNotReturn : 1;
3456 bool IsReturnValueUsed : 1;
3457 bool IsConvergent : 1;
3458 bool IsPatchPoint : 1;
3460 // IsTailCall should be modified by implementations of
3461 // TargetLowering::LowerCall that perform tail call conversions.
3462 bool IsTailCall = false;
3464 // Is Call lowering done post SelectionDAG type legalization.
3465 bool IsPostTypeLegalization = false;
3467 unsigned NumFixedArgs = -1;
3468 CallingConv::ID CallConv = CallingConv::C;
3473 ImmutableCallSite CS;
3474 SmallVector<ISD::OutputArg, 32> Outs;
3475 SmallVector<SDValue, 32> OutVals;
3476 SmallVector<ISD::InputArg, 32> Ins;
3477 SmallVector<SDValue, 4> InVals;
3479 CallLoweringInfo(SelectionDAG &DAG)
3480 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3481 DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3482 IsPatchPoint(false), DAG(DAG) {}
3484 CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3489 CallLoweringInfo &setChain(SDValue InChain) {
3494 // setCallee with target/module-specific attributes
3495 CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3496 SDValue Target, ArgListTy &&ArgsList) {
3500 NumFixedArgs = ArgsList.size();
3501 Args = std::move(ArgsList);
3503 DAG.getTargetLoweringInfo().markLibCallAttributes(
3504 &(DAG.getMachineFunction()), CC, Args);
3508 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3509 SDValue Target, ArgListTy &&ArgsList) {
3513 NumFixedArgs = ArgsList.size();
3514 Args = std::move(ArgsList);
3518 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3519 SDValue Target, ArgListTy &&ArgsList,
3520 ImmutableCallSite Call) {
3523 IsInReg = Call.hasRetAttr(Attribute::InReg);
3525 Call.doesNotReturn() ||
3526 (!Call.isInvoke() &&
3527 isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3528 IsVarArg = FTy->isVarArg();
3529 IsReturnValueUsed = !Call.getInstruction()->use_empty();
3530 RetSExt = Call.hasRetAttr(Attribute::SExt);
3531 RetZExt = Call.hasRetAttr(Attribute::ZExt);
3535 CallConv = Call.getCallingConv();
3536 NumFixedArgs = FTy->getNumParams();
3537 Args = std::move(ArgsList);
3544 CallLoweringInfo &setInRegister(bool Value = true) {
3549 CallLoweringInfo &setNoReturn(bool Value = true) {
3550 DoesNotReturn = Value;
3554 CallLoweringInfo &setVarArg(bool Value = true) {
3559 CallLoweringInfo &setTailCall(bool Value = true) {
3564 CallLoweringInfo &setDiscardResult(bool Value = true) {
3565 IsReturnValueUsed = !Value;
3569 CallLoweringInfo &setConvergent(bool Value = true) {
3570 IsConvergent = Value;
3574 CallLoweringInfo &setSExtResult(bool Value = true) {
3579 CallLoweringInfo &setZExtResult(bool Value = true) {
3584 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3585 IsPatchPoint = Value;
3589 CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3590 IsPostTypeLegalization = Value;
3594 ArgListTy &getArgs() {
3599 /// This structure is used to pass arguments to makeLibCall function.
3600 struct MakeLibCallOptions {
3601 // By passing type list before soften to makeLibCall, the target hook
3602 // shouldExtendTypeInLibCall can get the original type before soften.
3603 ArrayRef<EVT> OpsVTBeforeSoften;
3604 EVT RetVTBeforeSoften;
3606 bool DoesNotReturn : 1;
3607 bool IsReturnValueUsed : 1;
3608 bool IsPostTypeLegalization : 1;
3611 MakeLibCallOptions()
3612 : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
3613 IsPostTypeLegalization(false), IsSoften(false) {}
3615 MakeLibCallOptions &setSExt(bool Value = true) {
3620 MakeLibCallOptions &setNoReturn(bool Value = true) {
3621 DoesNotReturn = Value;
3625 MakeLibCallOptions &setDiscardResult(bool Value = true) {
3626 IsReturnValueUsed = !Value;
3630 MakeLibCallOptions &setIsPostTypeLegalization(bool Value = true) {
3631 IsPostTypeLegalization = Value;
3635 MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT,
3636 bool Value = true) {
3637 OpsVTBeforeSoften = OpsVT;
3638 RetVTBeforeSoften = RetVT;
3644 /// This function lowers an abstract call to a function into an actual call.
3645 /// This returns a pair of operands. The first element is the return value
3646 /// for the function (if RetTy is not VoidTy). The second element is the
3647 /// outgoing token chain. It calls LowerCall to do the actual lowering.
3648 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3650 /// This hook must be implemented to lower calls into the specified
3651 /// DAG. The outgoing arguments to the call are described by the Outs array,
3652 /// and the values to be returned by the call are described by the Ins
3653 /// array. The implementation should fill in the InVals array with legal-type
3654 /// return values from the call, and return the resulting token chain value.
3656 LowerCall(CallLoweringInfo &/*CLI*/,
3657 SmallVectorImpl<SDValue> &/*InVals*/) const {
3658 llvm_unreachable("Not Implemented");
3661 /// Target-specific cleanup for formal ByVal parameters.
3662 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3664 /// This hook should be implemented to check whether the return values
3665 /// described by the Outs array can fit into the return registers. If false
3666 /// is returned, an sret-demotion is performed.
3667 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3668 MachineFunction &/*MF*/, bool /*isVarArg*/,
3669 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3670 LLVMContext &/*Context*/) const
3672 // Return true by default to get preexisting behavior.
3676 /// This hook must be implemented to lower outgoing return values, described
3677 /// by the Outs array, into the specified DAG. The implementation should
3678 /// return the resulting token chain value.
3679 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3681 const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3682 const SmallVectorImpl<SDValue> & /*OutVals*/,
3683 const SDLoc & /*dl*/,
3684 SelectionDAG & /*DAG*/) const {
3685 llvm_unreachable("Not Implemented");
3688 /// Return true if result of the specified node is used by a return node
3689 /// only. It also compute and return the input chain for the tail call.
3691 /// This is used to determine whether it is possible to codegen a libcall as
3692 /// tail call at legalization time.
3693 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3697 /// Return true if the target may be able emit the call instruction as a tail
3698 /// call. This is used by optimization passes to determine if it's profitable
3699 /// to duplicate return instructions to enable tailcall optimization.
3700 virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3704 /// Return the builtin name for the __builtin___clear_cache intrinsic
3705 /// Default is to invoke the clear cache library call
3706 virtual const char * getClearCacheBuiltinName() const {
3707 return "__clear_cache";
3710 /// Return the register ID of the name passed in. Used by named register
3711 /// global variables extension. There is no target-independent behaviour
3712 /// so the default action is to bail.
3713 virtual Register getRegisterByName(const char* RegName, LLT Ty,
3714 const MachineFunction &MF) const {
3715 report_fatal_error("Named registers not implemented for this target");
3718 /// Return the type that should be used to zero or sign extend a
3719 /// zeroext/signext integer return value. FIXME: Some C calling conventions
3720 /// require the return type to be promoted, but this is not true all the time,
3721 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3722 /// conventions. The frontend should handle this and include all of the
3723 /// necessary information.
3724 virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3725 ISD::NodeType /*ExtendKind*/) const {
3726 EVT MinVT = getRegisterType(Context, MVT::i32);
3727 return VT.bitsLT(MinVT) ? MinVT : VT;
3730 /// For some targets, an LLVM struct type must be broken down into multiple
3731 /// simple types, but the calling convention specifies that the entire struct
3732 /// must be passed in a block of consecutive registers.
3734 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3735 bool isVarArg) const {
3739 /// For most targets, an LLVM type must be broken down into multiple
3740 /// smaller types. Usually the halves are ordered according to the endianness
3741 /// but for some platform that would break. So this method will default to
3742 /// matching the endianness but can be overridden.
3744 shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const {
3745 return DL.isLittleEndian();
3748 /// Returns a 0 terminated array of registers that can be safely used as
3749 /// scratch registers.
3750 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3754 /// This callback is used to prepare for a volatile or atomic load.
3755 /// It takes a chain node as input and returns the chain for the load itself.
3757 /// Having a callback like this is necessary for targets like SystemZ,
3758 /// which allows a CPU to reuse the result of a previous load indefinitely,
3759 /// even if a cache-coherent store is performed by another CPU. The default
3760 /// implementation does nothing.
3761 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3762 SelectionDAG &DAG) const {
3766 /// This callback is used to inspect load/store instructions and add
3767 /// target-specific MachineMemOperand flags to them. The default
3768 /// implementation does nothing.
3769 virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3770 return MachineMemOperand::MONone;
3773 /// Should SelectionDAG lower an atomic store of the given kind as a normal
3774 /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3775 /// eventually migrate all targets to the using StoreSDNodes, but porting is
3776 /// being done target at a time.
3777 virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const {
3778 assert(SI.isAtomic() && "violated precondition");
3782 /// Should SelectionDAG lower an atomic load of the given kind as a normal
3783 /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3784 /// eventually migrate all targets to the using LoadSDNodes, but porting is
3785 /// being done target at a time.
3786 virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const {
3787 assert(LI.isAtomic() && "violated precondition");
3792 /// This callback is invoked by the type legalizer to legalize nodes with an
3793 /// illegal operand type but legal result types. It replaces the
3794 /// LowerOperation callback in the type Legalizer. The reason we can not do
3795 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3796 /// use this callback.
3798 /// TODO: Consider merging with ReplaceNodeResults.
3800 /// The target places new result values for the node in Results (their number
3801 /// and types must exactly match those of the original return values of
3802 /// the node), or leaves Results empty, which indicates that the node is not
3803 /// to be custom lowered after all.
3804 /// The default implementation calls LowerOperation.
3805 virtual void LowerOperationWrapper(SDNode *N,
3806 SmallVectorImpl<SDValue> &Results,
3807 SelectionDAG &DAG) const;
3809 /// This callback is invoked for operations that are unsupported by the
3810 /// target, which are registered to use 'custom' lowering, and whose defined
3811 /// values are all legal. If the target has no operations that require custom
3812 /// lowering, it need not implement this. The default implementation of this
3814 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3816 /// This callback is invoked when a node result type is illegal for the
3817 /// target, and the operation was registered to use 'custom' lowering for that
3818 /// result type. The target places new result values for the node in Results
3819 /// (their number and types must exactly match those of the original return
3820 /// values of the node), or leaves Results empty, which indicates that the
3821 /// node is not to be custom lowered after all.
3823 /// If the target has no operations that require custom lowering, it need not
3824 /// implement this. The default implementation aborts.
3825 virtual void ReplaceNodeResults(SDNode * /*N*/,
3826 SmallVectorImpl<SDValue> &/*Results*/,
3827 SelectionDAG &/*DAG*/) const {
3828 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3831 /// This method returns the name of a target specific DAG node.
3832 virtual const char *getTargetNodeName(unsigned Opcode) const;
3834 /// This method returns a target specific FastISel object, or null if the
3835 /// target does not support "fast" ISel.
3836 virtual FastISel *createFastISel(FunctionLoweringInfo &,
3837 const TargetLibraryInfo *) const {
3841 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3842 SelectionDAG &DAG) const;
3844 //===--------------------------------------------------------------------===//
3845 // Inline Asm Support hooks
3848 /// This hook allows the target to expand an inline asm call to be explicit
3849 /// llvm code if it wants to. This is useful for turning simple inline asms
3850 /// into LLVM intrinsics, which gives the compiler more information about the
3851 /// behavior of the code.
3852 virtual bool ExpandInlineAsm(CallInst *) const {
3856 enum ConstraintType {
3857 C_Register, // Constraint represents specific register(s).
3858 C_RegisterClass, // Constraint represents any of register(s) in class.
3859 C_Memory, // Memory constraint.
3860 C_Immediate, // Requires an immediate.
3861 C_Other, // Something else.
3862 C_Unknown // Unsupported constraint.
3865 enum ConstraintWeight {
3867 CW_Invalid = -1, // No match.
3868 CW_Okay = 0, // Acceptable.
3869 CW_Good = 1, // Good weight.
3870 CW_Better = 2, // Better weight.
3871 CW_Best = 3, // Best weight.
3873 // Well-known weights.
3874 CW_SpecificReg = CW_Okay, // Specific register operands.
3875 CW_Register = CW_Good, // Register operands.
3876 CW_Memory = CW_Better, // Memory operands.
3877 CW_Constant = CW_Best, // Constant operand.
3878 CW_Default = CW_Okay // Default or don't know type.
3881 /// This contains information for each constraint that we are lowering.
3882 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3883 /// This contains the actual string for the code, like "m". TargetLowering
3884 /// picks the 'best' code from ConstraintInfo::Codes that most closely
3885 /// matches the operand.
3886 std::string ConstraintCode;
3888 /// Information about the constraint code, e.g. Register, RegisterClass,
3889 /// Memory, Other, Unknown.
3890 TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3892 /// If this is the result output operand or a clobber, this is null,
3893 /// otherwise it is the incoming operand to the CallInst. This gets
3894 /// modified as the asm is processed.
3895 Value *CallOperandVal = nullptr;
3897 /// The ValueType for the operand value.
3898 MVT ConstraintVT = MVT::Other;
3900 /// Copy constructor for copying from a ConstraintInfo.
3901 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3902 : InlineAsm::ConstraintInfo(std::move(Info)) {}
3904 /// Return true of this is an input operand that is a matching constraint
3906 bool isMatchingInputConstraint() const;
3908 /// If this is an input matching constraint, this method returns the output
3909 /// operand it matches.
3910 unsigned getMatchedOperand() const;
3913 using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3915 /// Split up the constraint string from the inline assembly value into the
3916 /// specific constraints and their prefixes, and also tie in the associated
3917 /// operand values. If this returns an empty vector, and if the constraint
3918 /// string itself isn't empty, there was an error parsing.
3919 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3920 const TargetRegisterInfo *TRI,
3921 ImmutableCallSite CS) const;
3923 /// Examine constraint type and operand type and determine a weight value.
3924 /// The operand object must already have been set up with the operand type.
3925 virtual ConstraintWeight getMultipleConstraintMatchWeight(
3926 AsmOperandInfo &info, int maIndex) const;
3928 /// Examine constraint string and operand type and determine a weight value.
3929 /// The operand object must already have been set up with the operand type.
3930 virtual ConstraintWeight getSingleConstraintMatchWeight(
3931 AsmOperandInfo &info, const char *constraint) const;
3933 /// Determines the constraint code and constraint type to use for the specific
3934 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3935 /// If the actual operand being passed in is available, it can be passed in as
3936 /// Op, otherwise an empty SDValue can be passed.
3937 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3939 SelectionDAG *DAG = nullptr) const;
3941 /// Given a constraint, return the type of constraint it is for this target.
3942 virtual ConstraintType getConstraintType(StringRef Constraint) const;
3944 /// Given a physical register constraint (e.g. {edx}), return the register
3945 /// number and the register class for the register.
3947 /// Given a register class constraint, like 'r', if this corresponds directly
3948 /// to an LLVM register class, return a register of 0 and the register class
3951 /// This should only be used for C_Register constraints. On error, this
3952 /// returns a register number of 0 and a null register class pointer.
3953 virtual std::pair<unsigned, const TargetRegisterClass *>
3954 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3955 StringRef Constraint, MVT VT) const;
3957 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3958 if (ConstraintCode == "m")
3959 return InlineAsm::Constraint_m;
3960 return InlineAsm::Constraint_Unknown;
3963 /// Try to replace an X constraint, which matches anything, with another that
3964 /// has more specific requirements based on the type of the corresponding
3965 /// operand. This returns null if there is no replacement to make.
3966 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3968 /// Lower the specified operand into the Ops vector. If it is invalid, don't
3969 /// add anything to Ops.
3970 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3971 std::vector<SDValue> &Ops,
3972 SelectionDAG &DAG) const;
3974 // Lower custom output constraints. If invalid, return SDValue().
3975 virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3977 const AsmOperandInfo &OpInfo,
3978 SelectionDAG &DAG) const;
3980 //===--------------------------------------------------------------------===//
3981 // Div utility functions
3983 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3984 SmallVectorImpl<SDNode *> &Created) const;
3985 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3986 SmallVectorImpl<SDNode *> &Created) const;
3988 /// Targets may override this function to provide custom SDIV lowering for
3989 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3990 /// assumes SDIV is expensive and replaces it with a series of other integer
3992 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3994 SmallVectorImpl<SDNode *> &Created) const;
3996 /// Indicate whether this target prefers to combine FDIVs with the same
3997 /// divisor. If the transform should never be done, return zero. If the
3998 /// transform should be done, return the minimum number of divisor uses
3999 /// that must exist.
4000 virtual unsigned combineRepeatedFPDivisors() const {
4004 /// Hooks for building estimates in place of slower divisions and square
4007 /// Return either a square root or its reciprocal estimate value for the input
4009 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
4010 /// 'Enabled' as set by a potential default override attribute.
4011 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
4012 /// refinement iterations required to generate a sufficient (though not
4013 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
4014 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
4015 /// algorithm implementation that uses either one or two constants.
4016 /// The boolean Reciprocal is used to select whether the estimate is for the
4017 /// square root of the input operand or the reciprocal of its square root.
4018 /// A target may choose to implement its own refinement within this function.
4019 /// If that's true, then return '0' as the number of RefinementSteps to avoid
4020 /// any further refinement of the estimate.
4021 /// An empty SDValue return means no estimate sequence can be created.
4022 virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
4023 int Enabled, int &RefinementSteps,
4024 bool &UseOneConstNR, bool Reciprocal) const {
4028 /// Return a reciprocal estimate value for the input operand.
4029 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
4030 /// 'Enabled' as set by a potential default override attribute.
4031 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
4032 /// refinement iterations required to generate a sufficient (though not
4033 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
4034 /// A target may choose to implement its own refinement within this function.
4035 /// If that's true, then return '0' as the number of RefinementSteps to avoid
4036 /// any further refinement of the estimate.
4037 /// An empty SDValue return means no estimate sequence can be created.
4038 virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
4039 int Enabled, int &RefinementSteps) const {
4043 //===--------------------------------------------------------------------===//
4044 // Legalization utility functions
4047 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
4048 /// respectively, each computing an n/2-bit part of the result.
4049 /// \param Result A vector that will be filled with the parts of the result
4050 /// in little-endian order.
4051 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4052 /// if you want to control how low bits are extracted from the LHS.
4053 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4054 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4055 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4056 /// \returns true if the node has been expanded, false if it has not
4057 bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
4058 SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
4059 SelectionDAG &DAG, MulExpansionKind Kind,
4060 SDValue LL = SDValue(), SDValue LH = SDValue(),
4061 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4063 /// Expand a MUL into two nodes. One that computes the high bits of
4064 /// the result and one that computes the low bits.
4065 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
4066 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4067 /// if you want to control how low bits are extracted from the LHS.
4068 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4069 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4070 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4071 /// \returns true if the node has been expanded. false if it has not
4072 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
4073 SelectionDAG &DAG, MulExpansionKind Kind,
4074 SDValue LL = SDValue(), SDValue LH = SDValue(),
4075 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4077 /// Expand funnel shift.
4078 /// \param N Node to expand
4079 /// \param Result output after conversion
4080 /// \returns True, if the expansion was successful, false otherwise
4081 bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4083 /// Expand rotations.
4084 /// \param N Node to expand
4085 /// \param Result output after conversion
4086 /// \returns True, if the expansion was successful, false otherwise
4087 bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4089 /// Expand float(f32) to SINT(i64) conversion
4090 /// \param N Node to expand
4091 /// \param Result output after conversion
4092 /// \returns True, if the expansion was successful, false otherwise
4093 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4095 /// Expand float to UINT conversion
4096 /// \param N Node to expand
4097 /// \param Result output after conversion
4098 /// \param Chain output chain after conversion
4099 /// \returns True, if the expansion was successful, false otherwise
4100 bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain,
4101 SelectionDAG &DAG) const;
4103 /// Expand UINT(i64) to double(f64) conversion
4104 /// \param N Node to expand
4105 /// \param Result output after conversion
4106 /// \param Chain output chain after conversion
4107 /// \returns True, if the expansion was successful, false otherwise
4108 bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain,
4109 SelectionDAG &DAG) const;
4111 /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
4112 SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
4114 /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4115 /// vector nodes can only succeed if all operations are legal/custom.
4116 /// \param N Node to expand
4117 /// \param Result output after conversion
4118 /// \returns True, if the expansion was successful, false otherwise
4119 bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4121 /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4122 /// vector nodes can only succeed if all operations are legal/custom.
4123 /// \param N Node to expand
4124 /// \param Result output after conversion
4125 /// \returns True, if the expansion was successful, false otherwise
4126 bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4128 /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4129 /// vector nodes can only succeed if all operations are legal/custom.
4130 /// \param N Node to expand
4131 /// \param Result output after conversion
4132 /// \returns True, if the expansion was successful, false otherwise
4133 bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4135 /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4136 /// vector nodes can only succeed if all operations are legal/custom.
4137 /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4138 /// \param N Node to expand
4139 /// \param Result output after conversion
4140 /// \returns True, if the expansion was successful, false otherwise
4141 bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4143 /// Turn load of vector type into a load of the individual elements.
4144 /// \param LD load to expand
4145 /// \returns BUILD_VECTOR and TokenFactor nodes.
4146 std::pair<SDValue, SDValue> scalarizeVectorLoad(LoadSDNode *LD,
4147 SelectionDAG &DAG) const;
4149 // Turn a store of a vector type into stores of the individual elements.
4150 /// \param ST Store with a vector value type
4151 /// \returns TokenFactor of the individual store chains.
4152 SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
4154 /// Expands an unaligned load to 2 half-size loads for an integer, and
4155 /// possibly more for vectors.
4156 std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
4157 SelectionDAG &DAG) const;
4159 /// Expands an unaligned store to 2 half-size stores for integer values, and
4160 /// possibly more for vectors.
4161 SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
4163 /// Increments memory address \p Addr according to the type of the value
4164 /// \p DataVT that should be stored. If the data is stored in compressed
4165 /// form, the memory address should be incremented according to the number of
4166 /// the stored elements. This number is equal to the number of '1's bits
4168 /// \p DataVT is a vector type. \p Mask is a vector value.
4169 /// \p DataVT and \p Mask have the same number of vector elements.
4170 SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
4171 EVT DataVT, SelectionDAG &DAG,
4172 bool IsCompressedMemory) const;
4174 /// Get a pointer to vector element \p Idx located in memory for a vector of
4175 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4176 /// bounds the returned pointer is unspecified, but will be within the vector
4178 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4179 SDValue Index) const;
4181 /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4182 /// method accepts integers as its arguments.
4183 SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
4185 /// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This
4186 /// method accepts integers as its arguments.
4187 SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
4189 /// Method for building the DAG expansion of ISD::[US]DIVFIX. This
4190 /// method accepts integers as its arguments.
4191 /// Note: This method may fail if the division could not be performed
4192 /// within the type. Clients must retry with a wider type if this happens.
4193 SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
4194 SDValue LHS, SDValue RHS,
4195 unsigned Scale, SelectionDAG &DAG) const;
4197 /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4198 /// always suceeds and populates the Result and Overflow arguments.
4199 void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4200 SelectionDAG &DAG) const;
4202 /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4203 /// always suceeds and populates the Result and Overflow arguments.
4204 void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4205 SelectionDAG &DAG) const;
4207 /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4208 /// expansion was successful and populates the Result and Overflow arguments.
4209 bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4210 SelectionDAG &DAG) const;
4212 /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4213 /// only the first Count elements of the vector are used.
4214 SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
4216 //===--------------------------------------------------------------------===//
4217 // Instruction Emitting Hooks
4220 /// This method should be implemented by targets that mark instructions with
4221 /// the 'usesCustomInserter' flag. These instructions are special in various
4222 /// ways, which require special support to insert. The specified MachineInstr
4223 /// is created but not inserted into any basic blocks, and this method is
4224 /// called to expand it into a sequence of instructions, potentially also
4225 /// creating new basic blocks and control flow.
4226 /// As long as the returned basic block is different (i.e., we created a new
4227 /// one), the custom inserter is free to modify the rest of \p MBB.
4228 virtual MachineBasicBlock *
4229 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4231 /// This method should be implemented by targets that mark instructions with
4232 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4233 /// instruction selection by target hooks. e.g. To fill in optional defs for
4234 /// ARM 's' setting instructions.
4235 virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4236 SDNode *Node) const;
4238 /// If this function returns true, SelectionDAGBuilder emits a
4239 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4240 virtual bool useLoadStackGuardNode() const {
4244 virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
4245 const SDLoc &DL) const {
4246 llvm_unreachable("not implemented for this target");
4249 /// Lower TLS global address SDNode for target independent emulated TLS model.
4250 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4251 SelectionDAG &DAG) const;
4253 /// Expands target specific indirect branch for the case of JumpTable
4255 virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
4256 SelectionDAG &DAG) const {
4257 return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4260 // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4261 // If we're comparing for equality to zero and isCtlzFast is true, expose the
4262 // fact that this can be implemented as a ctlz/srl pair, so that the dag
4263 // combiner can fold the new nodes.
4264 SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4267 SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4268 const SDLoc &DL, DAGCombinerInfo &DCI) const;
4269 SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4270 const SDLoc &DL, DAGCombinerInfo &DCI) const;
4272 SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4273 SDValue N1, ISD::CondCode Cond,
4274 DAGCombinerInfo &DCI,
4275 const SDLoc &DL) const;
4277 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4278 SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
4279 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
4280 DAGCombinerInfo &DCI, const SDLoc &DL) const;
4282 SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4283 SDValue CompTargetNode, ISD::CondCode Cond,
4284 DAGCombinerInfo &DCI, const SDLoc &DL,
4285 SmallVectorImpl<SDNode *> &Created) const;
4286 SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4287 ISD::CondCode Cond, DAGCombinerInfo &DCI,
4288 const SDLoc &DL) const;
4290 SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
4291 SDValue CompTargetNode, ISD::CondCode Cond,
4292 DAGCombinerInfo &DCI, const SDLoc &DL,
4293 SmallVectorImpl<SDNode *> &Created) const;
4294 SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4295 ISD::CondCode Cond, DAGCombinerInfo &DCI,
4296 const SDLoc &DL) const;
4299 /// Given an LLVM IR type and return type attributes, compute the return value
4300 /// EVTs and flags, and optionally also the offsets, if the return value is
4301 /// being lowered to memory.
4302 void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
4303 SmallVectorImpl<ISD::OutputArg> &Outs,
4304 const TargetLowering &TLI, const DataLayout &DL);
4306 } // end namespace llvm
4308 #endif // LLVM_CODEGEN_TARGETLOWERING_H