1 //===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines a wrapper around MCSchedModel that allows the interface to
10 // benefit from information currently only available in TargetInstrInfo.
11 // Ideally, the scheduling interface would be fully defined in the MC layer.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
16 #define LLVM_CODEGEN_TARGETSCHEDULE_H
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/TargetSubtargetInfo.h"
21 #include "llvm/Config/llvm-config.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/MC/MCSchedule.h"
28 class TargetInstrInfo;
30 /// Provide an instruction scheduling machine model to CodeGen passes.
31 class TargetSchedModel {
32 // For efficiency, hold a copy of the statically defined MCSchedModel for this
34 MCSchedModel SchedModel;
35 InstrItineraryData InstrItins;
36 const TargetSubtargetInfo *STI = nullptr;
37 const TargetInstrInfo *TII = nullptr;
39 SmallVector<unsigned, 16> ResourceFactors;
41 // Multiply to normalize microops to resource units.
42 unsigned MicroOpFactor = 0;
44 // Resource units per cycle. Latency normalization factor.
45 unsigned ResourceLCM = 0;
47 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
50 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
52 /// Initialize the machine model for instruction scheduling.
54 /// The machine model API keeps a copy of the top-level MCSchedModel table
55 /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
56 /// dynamic properties.
57 void init(const TargetSubtargetInfo *TSInfo);
59 /// Return the MCSchedClassDesc for this instruction.
60 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
62 /// TargetSubtargetInfo getter.
63 const TargetSubtargetInfo *getSubtargetInfo() const { return STI; }
65 /// TargetInstrInfo getter.
66 const TargetInstrInfo *getInstrInfo() const { return TII; }
68 /// Return true if this machine model includes an instruction-level
71 /// This is more detailed than the course grain IssueWidth and default
72 /// latency properties, but separate from the per-cycle itinerary data.
73 bool hasInstrSchedModel() const;
75 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
77 /// Return true if this machine model includes cycle-to-cycle itinerary
80 /// This models scheduling at each stage in the processor pipeline.
81 bool hasInstrItineraries() const;
83 const InstrItineraryData *getInstrItineraries() const {
84 if (hasInstrItineraries())
89 /// Return true if this machine model includes an instruction-level
90 /// scheduling model or cycle-to-cycle itinerary data.
91 bool hasInstrSchedModelOrItineraries() const {
92 return hasInstrSchedModel() || hasInstrItineraries();
95 /// Identify the processor corresponding to the current subtarget.
96 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
98 /// Maximum number of micro-ops that may be scheduled per cycle.
99 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
101 /// Return true if new group must begin.
102 bool mustBeginGroup(const MachineInstr *MI,
103 const MCSchedClassDesc *SC = nullptr) const;
104 /// Return true if current group must end.
105 bool mustEndGroup(const MachineInstr *MI,
106 const MCSchedClassDesc *SC = nullptr) const;
108 /// Return the number of issue slots required for this MI.
109 unsigned getNumMicroOps(const MachineInstr *MI,
110 const MCSchedClassDesc *SC = nullptr) const;
112 /// Get the number of kinds of resources for this target.
113 unsigned getNumProcResourceKinds() const {
114 return SchedModel.getNumProcResourceKinds();
117 /// Get a processor resource by ID for convenience.
118 const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
119 return SchedModel.getProcResource(PIdx);
122 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
123 const char *getResourceName(unsigned PIdx) const {
126 return SchedModel.getProcResource(PIdx)->Name;
130 using ProcResIter = const MCWriteProcResEntry *;
132 // Get an iterator into the processor resources consumed by this
134 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
135 // The subtarget holds a single resource table for all processors.
136 return STI->getWriteProcResBegin(SC);
138 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
139 return STI->getWriteProcResEnd(SC);
142 /// Multiply the number of units consumed for a resource by this factor
143 /// to normalize it relative to other resources.
144 unsigned getResourceFactor(unsigned ResIdx) const {
145 return ResourceFactors[ResIdx];
148 /// Multiply number of micro-ops by this factor to normalize it
149 /// relative to other resources.
150 unsigned getMicroOpFactor() const {
151 return MicroOpFactor;
154 /// Multiply cycle count by this factor to normalize it relative to
155 /// other resources. This is the number of resource units per cycle.
156 unsigned getLatencyFactor() const {
160 /// Number of micro-ops that may be buffered for OOO execution.
161 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
163 /// Number of resource units that may be buffered for OOO execution.
164 /// \return The buffer size in resource units or -1 for unlimited.
165 int getResourceBufferSize(unsigned PIdx) const {
166 return SchedModel.getProcResource(PIdx)->BufferSize;
169 /// Compute operand latency based on the available machine model.
171 /// Compute and return the latency of the given data dependent def and use
172 /// when the operand indices are already known. UseMI may be NULL for an
174 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
175 const MachineInstr *UseMI, unsigned UseOperIdx)
178 /// Compute the instruction latency based on the available machine
181 /// Compute and return the expected latency of this instruction independent of
182 /// a particular use. computeOperandLatency is the preferred API, but this is
183 /// occasionally useful to help estimate instruction cost.
185 /// If UseDefaultDefLatency is false and no new machine sched model is
186 /// present this method falls back to TII->getInstrLatency with an empty
187 /// instruction itinerary (this is so we preserve the previous behavior of the
188 /// if converter after moving it to TargetSchedModel).
189 unsigned computeInstrLatency(const MachineInstr *MI,
190 bool UseDefaultDefLatency = true) const;
191 unsigned computeInstrLatency(const MCInst &Inst) const;
192 unsigned computeInstrLatency(unsigned Opcode) const;
195 /// Output dependency latency of a pair of defs of the same register.
197 /// This is typically one cycle.
198 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
199 const MachineInstr *DepMI) const;
201 /// Compute the reciprocal throughput of the given instruction.
202 double computeReciprocalThroughput(const MachineInstr *MI) const;
203 double computeReciprocalThroughput(const MCInst &MI) const;
204 double computeReciprocalThroughput(unsigned Opcode) const;
207 } // end namespace llvm
209 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H