1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements a target parser to recognise hardware features such as
10 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_SUPPORT_TARGETPARSER_H
15 #define LLVM_SUPPORT_TARGETPARSER_H
17 // FIXME: vector is used because that's what clang uses for subtarget feature
18 // lists, but SmallVector would probably be better
19 #include "llvm/Support/RISCVISAInfo.h"
25 template <typename T> class SmallVectorImpl;
28 // Target specific information in their own namespaces.
29 // (ARM/AArch64/X86 are declared in ARM/AArch64/X86TargetParser.h)
30 // These should be generated from TableGen because the information is already
31 // there, and there is where new information about targets will be added.
32 // FIXME: To TableGen this we need to make some table generated files available
33 // even if the back-end is not compiled with LLVM, plus we need to create a new
34 // back-end to TableGen to create these clean tables.
37 /// GPU kinds supported by the AMDGPU target.
38 enum GPUKind : uint32_t {
39 // Not specified processor.
42 // R600-based processors.
60 GK_R600_FIRST = GK_R600,
61 GK_R600_LAST = GK_TURKS,
63 // AMDGCN-based processors.
101 GK_AMDGCN_FIRST = GK_GFX600,
102 GK_AMDGCN_LAST = GK_GFX1035,
105 /// Instruction set architecture version.
112 // This isn't comprehensive for now, just things that are needed from the
114 enum ArchFeatureKind : uint32_t {
117 // These features only exist for r600, and are implied true for amdgcn.
118 FEATURE_FMA = 1 << 1,
119 FEATURE_LDEXP = 1 << 2,
120 FEATURE_FP64 = 1 << 3,
123 FEATURE_FAST_FMA_F32 = 1 << 4,
124 FEATURE_FAST_DENORMAL_F32 = 1 << 5,
126 // Wavefront 32 is available.
127 FEATURE_WAVE32 = 1 << 6,
129 // Xnack is available.
130 FEATURE_XNACK = 1 << 7,
132 // Sram-ecc is available.
133 FEATURE_SRAMECC = 1 << 8,
136 StringRef getArchNameAMDGCN(GPUKind AK);
137 StringRef getArchNameR600(GPUKind AK);
138 StringRef getCanonicalArchName(const Triple &T, StringRef Arch);
139 GPUKind parseArchAMDGCN(StringRef CPU);
140 GPUKind parseArchR600(StringRef CPU);
141 unsigned getArchAttrAMDGCN(GPUKind AK);
142 unsigned getArchAttrR600(GPUKind AK);
144 void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values);
145 void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);
147 IsaVersion getIsaVersion(StringRef GPU);
149 } // namespace AMDGPU
153 enum CPUKind : unsigned {
154 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
155 #include "RISCVTargetParser.def"
158 enum FeatureKind : unsigned {
164 bool checkCPUKind(CPUKind Kind, bool IsRV64);
165 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
166 CPUKind parseCPUKind(StringRef CPU);
167 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
168 StringRef getMArchFromMcpu(StringRef CPU);
169 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
170 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
171 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
172 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
173 StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo);
178 struct ParsedBranchProtection {
181 bool BranchTargetEnforcement;
184 bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP,