1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces which should be
10 // implemented by each target which is using a TableGen based code generator.
12 //===----------------------------------------------------------------------===//
14 // Include all information about LLVM intrinsics.
15 include "llvm/IR/Intrinsics.td"
17 class Predicate; // Forward def
19 //===----------------------------------------------------------------------===//
20 // Register file description - These classes are used to fill in the target
21 // description classes.
23 class HwMode<string FS, list<Predicate> Ps> {
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
26 // when "feat1" is enabled and "feat2" is disabled at the same time.
27 // Any other features are not checked.
28 // When multiple modes are used, they should be mutually exclusive,
29 // otherwise the results are unpredictable.
32 // A list of predicates that turn on this HW mode.
33 list<Predicate> Predicates = Ps;
36 // A special mode recognized by tablegen. This mode is considered active
37 // when no other mode is active. For targets that do not use specific hw
38 // modes, this is the only mode.
39 def DefaultMode : HwMode<"", []>;
41 // A class used to associate objects with HW modes. It is only intended to
42 // be used as a base class, where the derived class should contain a member
43 // "Objects", which is a list of the same length as the list of modes.
44 // The n-th element on the Objects list will be associated with the n-th
45 // element on the Modes list.
46 class HwModeSelect<list<HwMode> Ms> {
47 list<HwMode> Modes = Ms;
50 // A common class that implements a counterpart of ValueType, which is
51 // dependent on a HW mode. This class inherits from ValueType itself,
52 // which makes it possible to use objects of this class where ValueType
53 // objects could be used. This is specifically applicable to selection
55 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
56 : HwModeSelect<Ms>, ValueType<0, 0> {
57 // The length of this list must be the same as the length of Ms.
58 list<ValueType> Objects = Ts;
61 // A class representing the register size, spill size and spill alignment
62 // in bits of a register.
63 class RegInfo<int RS, int SS, int SA> {
64 int RegSize = RS; // Register size in bits.
65 int SpillSize = SS; // Spill slot size in bits.
66 int SpillAlignment = SA; // Spill slot alignment in bits.
69 // The register size/alignment information, parameterized by a HW mode.
70 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
72 // The length of this list must be the same as the length of Ms.
73 list<RegInfo> Objects = Ts;
76 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
77 class SubRegIndex<int size, int offset = 0> {
78 string Namespace = "";
80 // Size - Size (in bits) of the sub-registers represented by this index.
83 // Offset - Offset of the first bit that is part of this sub-register index.
84 // Set it to -1 if the same index is used to represent sub-registers that can
85 // be at different offsets (for example when using an index to access an
86 // element in a register tuple).
89 // ComposedOf - A list of two SubRegIndex instances, [A, B].
90 // This indicates that this SubRegIndex is the result of composing A and B.
91 // See ComposedSubRegIndex.
92 list<SubRegIndex> ComposedOf = [];
94 // CoveringSubRegIndices - A list of two or more sub-register indexes that
95 // cover this sub-register.
97 // This field should normally be left blank as TableGen can infer it.
99 // TableGen automatically detects sub-registers that straddle the registers
100 // in the SubRegs field of a Register definition. For example:
102 // Q0 = dsub_0 -> D0, dsub_1 -> D1
103 // Q1 = dsub_0 -> D2, dsub_1 -> D3
104 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
105 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
107 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
108 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
109 // CoveringSubRegIndices = [dsub_1, dsub_2].
110 list<SubRegIndex> CoveringSubRegIndices = [];
113 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
114 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
115 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
116 : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1,
117 !eq(B.Offset, -1): -1,
118 true: !add(A.Offset, B.Offset))> {
120 let ComposedOf = [A, B];
123 // RegAltNameIndex - The alternate name set to use for register operands of
124 // this register class when printing.
125 class RegAltNameIndex {
126 string Namespace = "";
128 // A set to be used if the name for a register is not defined in this set.
129 // This allows creating name sets with only a few alternative names.
130 RegAltNameIndex FallbackRegAltNameIndex = ?;
132 def NoRegAltName : RegAltNameIndex;
134 // Register - You should define one instance of this class for each register
135 // in the target machine. String n will become the "name" of the register.
136 class Register<string n, list<string> altNames = []> {
137 string Namespace = "";
139 list<string> AltNames = altNames;
141 // Aliases - A list of registers that this register overlaps with. A read or
142 // modification of this register can potentially read or modify the aliased
144 list<Register> Aliases = [];
146 // SubRegs - A list of registers that are parts of this register. Note these
147 // are "immediate" sub-registers and the registers within the list do not
148 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
150 list<Register> SubRegs = [];
152 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
153 // to address it. Sub-sub-register indices are automatically inherited from
155 list<SubRegIndex> SubRegIndices = [];
157 // RegAltNameIndices - The alternate name indices which are valid for this
159 list<RegAltNameIndex> RegAltNameIndices = [];
161 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
162 // These values can be determined by locating the <target>.h file in the
163 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
164 // order of these names correspond to the enumeration used by gcc. A value of
165 // -1 indicates that the gcc number is undefined and -2 that register number
166 // is invalid for this mode/flavour.
167 list<int> DwarfNumbers = [];
169 // CostPerUse - Additional cost of instructions using this register compared
170 // to other registers in its class. The register allocator will try to
171 // minimize the number of instructions using a register with a CostPerUse.
172 // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where
173 // some registers require larger instruction encodings, by the RISC-V target,
174 // where some registers preclude using some C instructions. By making it a
175 // list, targets can have multiple cost models associated with each register
176 // and can choose one specific cost model per Machine Function by overriding
177 // TargetRegisterInfo::getRegisterCostTableIndex. Every target register will
178 // finally have an equal number of cost values which is the max of costPerUse
179 // values specified. Any mismatch in the cost values for a register will be
180 // filled with zeros. Restricted the cost type to uint8_t in the
181 // generated table. It will considerably reduce the table size.
182 list<int> CostPerUse = [0];
184 // CoveredBySubRegs - When this bit is set, the value of this register is
185 // completely determined by the value of its sub-registers. For example, the
186 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
187 // covered by its sub-register AX.
188 bit CoveredBySubRegs = false;
190 // HWEncoding - The target specific hardware encoding for this register.
191 bits<16> HWEncoding = 0;
193 bit isArtificial = false;
195 // isConstant - This register always holds a constant value (e.g. the zero
196 // register in architectures such as MIPS)
197 bit isConstant = false;
200 // RegisterWithSubRegs - This can be used to define instances of Register which
201 // need to specify sub-registers.
202 // List "subregs" specifies which registers are sub-registers to this one. This
203 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
204 // This allows the code generator to be careful not to put two values with
205 // overlapping live ranges into registers which alias.
206 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
207 let SubRegs = subregs;
210 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
211 // of Operand's that are legal as type qualifiers in DAG patterns. This should
212 // only ever be used for defining multiclasses that are polymorphic over both
213 // RegisterClass's and other Operand's.
215 string OperandNamespace = "MCOI";
216 string DecoderMethod = "";
219 // RegisterClass - Now that all of the registers are defined, and aliases
220 // between registers are defined, specify which registers belong to which
221 // register classes. This also defines the default allocation order of
222 // registers by register allocators.
224 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
225 dag regList, RegAltNameIndex idx = NoRegAltName>
227 string Namespace = namespace;
229 // The register size/alignment information, parameterized by a HW mode.
230 RegInfoByHwMode RegInfos;
232 // RegType - Specify the list ValueType of the registers in this register
233 // class. Note that all registers in a register class must have the same
234 // ValueTypes. This is a list because some targets permit storing different
235 // types in same register, for example vector values with 128-bit total size,
236 // but different count/size of items, like SSE on x86.
238 list<ValueType> RegTypes = regTypes;
240 // Size - Specify the spill size in bits of the registers. A default value of
241 // zero lets tablegen pick an appropriate size.
244 // Alignment - Specify the alignment required of the registers when they are
245 // stored or loaded to memory.
247 int Alignment = alignment;
249 // CopyCost - This value is used to specify the cost of copying a value
250 // between two registers in this register class. The default value is one
251 // meaning it takes a single instruction to perform the copying. A negative
252 // value means copying is extremely expensive or impossible.
255 // MemberList - Specify which registers are in this class. If the
256 // allocation_order_* method are not specified, this also defines the order of
257 // allocation used by the register allocator.
259 dag MemberList = regList;
261 // AltNameIndex - The alternate register name to use when printing operands
262 // of this register class. Every register in the register class must have
263 // a valid alternate name for the given index.
264 RegAltNameIndex altNameIndex = idx;
266 // isAllocatable - Specify that the register class can be used for virtual
267 // registers and register allocation. Some register classes are only used to
268 // model instruction operand constraints, and should have isAllocatable = 0.
269 bit isAllocatable = true;
271 // AltOrders - List of alternative allocation orders. The default order is
272 // MemberList itself, and that is good enough for most targets since the
273 // register allocators automatically remove reserved registers and move
274 // callee-saved registers to the end.
275 list<dag> AltOrders = [];
277 // AltOrderSelect - The body of a function that selects the allocation order
278 // to use in a given machine function. The code will be inserted in a
279 // function like this:
281 // static inline unsigned f(const MachineFunction &MF) { ... }
283 // The function should return 0 to select the default order defined by
284 // MemberList, 1 to select the first AltOrders entry and so on.
285 code AltOrderSelect = [{}];
287 // Specify allocation priority for register allocators using a greedy
288 // heuristic. Classes with higher priority values are assigned first. This is
289 // useful as it is sometimes beneficial to assign registers to highly
290 // constrained classes first. The value has to be in the range [0,31].
291 int AllocationPriority = 0;
293 // Force register class to use greedy's global heuristic for all
294 // registers in this class. This should more aggressively try to
295 // avoid spilling in pathological cases.
296 bit GlobalPriority = false;
298 // Generate register pressure set for this register class and any class
299 // synthesized from it. Set to 0 to inhibit unneeded pressure sets.
300 bit GeneratePressureSet = true;
302 // Weight override for register pressure calculation. This is the value
303 // TargetRegisterClass::getRegClassWeight() will return. The weight is in
304 // units of pressure for this register class. If unset tablegen will
305 // calculate a weight based on a number of register units in this register
306 // class registers. The weight is per register.
309 // The diagnostic type to present when referencing this operand in a match
310 // failure error message. If this is empty, the default Match_InvalidOperand
311 // diagnostic type will be used. If this is "<name>", a Match_<name> enum
312 // value will be generated and used for this operand type. The target
313 // assembly parser is responsible for converting this into a user-facing
314 // diagnostic message.
315 string DiagnosticType = "";
317 // A diagnostic message to emit when an invalid value is provided for this
318 // register class when it is being used an an assembly operand. If this is
319 // non-empty, an anonymous diagnostic type enum value will be generated, and
320 // the assembly matcher will provide a function to map from diagnostic types
321 // to message strings.
322 string DiagnosticString = "";
324 // Target-specific flags. This becomes the TSFlags field in TargetRegisterClass.
327 // If set then consider this register class to be the base class for registers in
328 // its MemberList. The base class for registers present in multiple base register
329 // classes will be resolved in the order defined by this value, with lower values
330 // taking precedence over higher ones. Ties are resolved by enumeration order.
331 int BaseClassOrder = ?;
334 // The memberList in a RegisterClass is a dag of set operations. TableGen
335 // evaluates these set operations and expand them into register lists. These
336 // are the most common operation, see test/TableGen/SetTheory.td for more
337 // examples of what is possible:
339 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
340 // register class, or a sub-expression. This is also the way to simply list
343 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
345 // (and GPR, CSR) - Set intersection. All registers from the first set that are
346 // also in the second set.
348 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
349 // numbered registers. Takes an optional 4th operand which is a stride to use
350 // when generating the sequence.
352 // (shl GPR, 4) - Remove the first N elements.
354 // (trunc GPR, 4) - Truncate after the first N elements.
356 // (rotl GPR, 1) - Rotate N places to the left.
358 // (rotr GPR, 1) - Rotate N places to the right.
360 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
362 // (interleave A, B, ...) - Interleave the elements from each argument list.
364 // All of these operators work on ordered sets, not lists. That means
365 // duplicates are removed from sub-expressions.
367 // Set operators. The rest is defined in TargetSelectionDAG.td.
372 // RegisterTuples - Automatically generate super-registers by forming tuples of
373 // sub-registers. This is useful for modeling register sequence constraints
374 // with pseudo-registers that are larger than the architectural registers.
376 // The sub-register lists are zipped together:
378 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
380 // Generates the same registers as:
382 // let SubRegIndices = [sube, subo] in {
383 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
384 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
387 // The generated pseudo-registers inherit super-classes and fields from their
388 // first sub-register. Most fields from the Register class are inferred, and
389 // the AsmName and Dwarf numbers are cleared.
391 // RegisterTuples instances can be used in other set operations to form
392 // register classes and so on. This is the only way of using the generated
395 // RegNames may be specified to supply asm names for the generated tuples.
396 // If used must have the same size as the list of produced registers.
397 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs,
398 list<string> RegNames = []> {
399 // SubRegs - N lists of registers to be zipped up. Super-registers are
400 // synthesized from the first element of each SubRegs list, the second
401 // element and so on.
402 list<dag> SubRegs = Regs;
404 // SubRegIndices - N SubRegIndex instances. This provides the names of the
405 // sub-registers in the synthesized super-registers.
406 list<SubRegIndex> SubRegIndices = Indices;
408 // List of asm names for the generated tuple registers.
409 list<string> RegAsmNames = RegNames;
412 // RegisterCategory - This class is a list of RegisterClasses that belong to a
413 // general cateogry --- e.g. "general purpose" or "fixed" registers. This is
414 // useful for identifying registers in a generic way instead of having
415 // information about a specific target's registers.
416 class RegisterCategory<list<RegisterClass> classes> {
417 // Classes - A list of register classes that fall within the category.
418 list<RegisterClass> Classes = classes;
421 //===----------------------------------------------------------------------===//
422 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
423 // to the register numbering used by gcc and gdb. These values are used by a
424 // debug information writer to describe where values may be located during
426 class DwarfRegNum<list<int> Numbers> {
427 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
428 // These values can be determined by locating the <target>.h file in the
429 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
430 // order of these names correspond to the enumeration used by gcc. A value of
431 // -1 indicates that the gcc number is undefined and -2 that register number
432 // is invalid for this mode/flavour.
433 list<int> DwarfNumbers = Numbers;
436 // DwarfRegAlias - This class declares that a given register uses the same dwarf
437 // numbers as another one. This is useful for making it clear that the two
438 // registers do have the same number. It also lets us build a mapping
439 // from dwarf register number to llvm register.
440 class DwarfRegAlias<Register reg> {
441 Register DwarfAlias = reg;
444 //===----------------------------------------------------------------------===//
445 // Pull in the common support for MCPredicate (portable scheduling predicates).
447 include "llvm/Target/TargetInstrPredicate.td"
449 //===----------------------------------------------------------------------===//
450 // Pull in the common support for scheduling
452 include "llvm/Target/TargetSchedule.td"
454 class InstructionEncoding {
455 // Size of encoded instruction.
458 // The "namespace" in which this instruction exists, on targets like ARM
459 // which multiple ISA namespaces exist.
460 string DecoderNamespace = "";
462 // List of predicates which will be turned into isel matching code.
463 list<Predicate> Predicates = [];
465 string DecoderMethod = "";
467 // Is the instruction decoder method able to completely determine if the
468 // given instruction is valid or not. If the TableGen definition of the
469 // instruction specifies bitpattern A??B where A and B are static bits, the
470 // hasCompleteDecoder flag says whether the decoder method fully handles the
471 // ?? space, i.e. if it is a final arbiter for the instruction validity.
472 // If not then the decoder attempts to continue decoding when the decoder
475 // This allows to handle situations where the encoding is not fully
476 // orthogonal. Example:
477 // * InstA with bitpattern 0b0000????,
478 // * InstB with bitpattern 0b000000?? but the associated decoder method
479 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
481 // The decoder tries to decode a bitpattern that matches both InstA and
482 // InstB bitpatterns first as InstB (because it is the most specific
483 // encoding). In the default case (hasCompleteDecoder = 1), when
484 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
485 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
486 // DecodeInstB() is not able to determine if all possible values of ?? are
487 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
488 // decode the bitpattern as InstA too.
489 bit hasCompleteDecoder = true;
492 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
493 // an EncodingByHwMode, its Inst and Size members are ignored and Ts are used
494 // to encode and decode based on HwMode.
495 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
497 // The length of this list must be the same as the length of Ms.
498 list<InstructionEncoding> Objects = Ts;
501 //===----------------------------------------------------------------------===//
502 // Instruction set description - These classes correspond to the C++ classes in
503 // the Target/TargetInstrInfo.h file.
505 class Instruction : InstructionEncoding {
506 string Namespace = "";
508 dag OutOperandList; // An dag containing the MI def operand list.
509 dag InOperandList; // An dag containing the MI use operand list.
510 string AsmString = ""; // The .s format to print the instruction with.
512 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
513 // the Inst member of this Instruction is ignored.
514 EncodingByHwMode EncodingInfos;
516 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
517 // otherwise, uninitialized.
520 // The follow state will eventually be inferred automatically from the
521 // instruction pattern.
523 list<Register> Uses = []; // Default to using no non-operand registers
524 list<Register> Defs = []; // Default to modifying no non-operand registers
526 // Predicates - List of predicates which will be turned into isel matching
528 list<Predicate> Predicates = [];
530 // Size - Size of encoded instruction, or zero if the size cannot be determined
534 // Code size, for instruction selection.
535 // FIXME: What does this actually mean?
538 // Added complexity passed onto matching pattern.
539 int AddedComplexity = 0;
541 // Indicates if this is a pre-isel opcode that should be
542 // legalized/regbankselected/selected.
543 bit isPreISelOpcode = false;
545 // These bits capture information about the high-level semantics of the
547 bit isReturn = false; // Is this instruction a return instruction?
548 bit isBranch = false; // Is this instruction a branch instruction?
549 bit isEHScopeReturn = false; // Does this instruction end an EH scope?
550 bit isIndirectBranch = false; // Is this instruction an indirect branch?
551 bit isCompare = false; // Is this instruction a comparison instruction?
552 bit isMoveImm = false; // Is this instruction a move immediate instruction?
553 bit isMoveReg = false; // Is this instruction a move register instruction?
554 bit isBitcast = false; // Is this instruction a bitcast instruction?
555 bit isSelect = false; // Is this instruction a select instruction?
556 bit isBarrier = false; // Can control flow fall through this instruction?
557 bit isCall = false; // Is this instruction a call instruction?
558 bit isAdd = false; // Is this instruction an add instruction?
559 bit isTrap = false; // Is this instruction a trap instruction?
560 bit canFoldAsLoad = false; // Can this be folded as a simple memory operand?
561 bit mayLoad = ?; // Is it possible for this inst to read memory?
562 bit mayStore = ?; // Is it possible for this inst to write memory?
563 bit mayRaiseFPException = false; // Can this raise a floating-point exception?
564 bit isConvertibleToThreeAddress = false; // Can this 2-addr instruction promote?
565 bit isCommutable = false; // Is this 3 operand instruction commutable?
566 bit isTerminator = false; // Is this part of the terminator for a basic block?
567 bit isReMaterializable = false; // Is this instruction re-materializable?
568 bit isPredicable = false; // 1 means this instruction is predicable
569 // even if it does not have any operand
570 // tablegen can identify as a predicate
571 bit isUnpredicable = false; // 1 means this instruction is not predicable
572 // even if it _does_ have a predicate operand
573 bit hasDelaySlot = false; // Does this instruction have an delay slot?
574 bit usesCustomInserter = false; // Pseudo instr needing special help.
575 bit hasPostISelHook = false; // To be *adjusted* after isel by target hook.
576 bit hasCtrlDep = false; // Does this instruction r/w ctrl-flow chains?
577 bit isNotDuplicable = false; // Is it unsafe to duplicate this instruction?
578 bit isConvergent = false; // Is this instruction convergent?
579 bit isAuthenticated = false; // Does this instruction authenticate a pointer?
580 bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction.
581 bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement?
582 bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement?
583 bit isRegSequence = false; // Is this instruction a kind of reg sequence?
584 // If so, make sure to override
585 // TargetInstrInfo::getRegSequenceLikeInputs.
586 bit isPseudo = false; // Is this instruction a pseudo-instruction?
587 // If so, won't have encoding information for
588 // the [MC]CodeEmitter stuff.
589 bit isMeta = false; // Is this instruction a meta-instruction?
590 // If so, won't produce any output in the form of
591 // executable instructions
592 bit isExtractSubreg = false; // Is this instruction a kind of extract subreg?
593 // If so, make sure to override
594 // TargetInstrInfo::getExtractSubregLikeInputs.
595 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg?
596 // If so, make sure to override
597 // TargetInstrInfo::getInsertSubregLikeInputs.
598 bit variadicOpsAreDefs = false; // Are variadic operands definitions?
600 // Does the instruction have side effects that are not captured by any
601 // operands of the instruction or other flags?
602 bit hasSideEffects = ?;
604 // Is this instruction a "real" instruction (with a distinct machine
605 // encoding), or is it a pseudo instruction used for codegen modeling
607 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
608 // instructions can (and often do) still have encoding information
609 // associated with them. Once we've migrated all of them over to true
610 // pseudo-instructions that are lowered to real instructions prior to
611 // the printer/emitter, we can remove this attribute and just use isPseudo.
613 // The intended use is:
614 // isPseudo: Does not have encoding information and should be expanded,
615 // at the latest, during lowering to MCInst.
617 // isCodeGenOnly: Does have encoding information and can go through to the
618 // CodeEmitter unchanged, but duplicates a canonical instruction
619 // definition's encoding and should be ignored when constructing the
620 // assembler match tables.
621 bit isCodeGenOnly = false;
623 // Is this instruction a pseudo instruction for use by the assembler parser.
624 bit isAsmParserOnly = false;
626 // This instruction is not expected to be queried for scheduling latencies
627 // and therefore needs no scheduling information even for a complete
629 bit hasNoSchedulingInfo = false;
631 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
633 // Scheduling information from TargetSchedule.td.
634 list<SchedReadWrite> SchedRW;
636 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
638 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
639 /// be encoded into the output machineinstr.
640 string DisableEncoding = "";
642 string PostEncoderMethod = "";
644 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
645 bits<64> TSFlags = 0;
647 ///@name Assembler Parser Support
650 string AsmMatchConverter = "";
652 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
653 /// two-operand matcher inst-alias for a three operand instruction.
654 /// For example, the arm instruction "add r3, r3, r5" can be written
655 /// as "add r3, r5". The constraint is of the same form as a tied-operand
656 /// constraint. For example, "$Rn = $Rd".
657 string TwoOperandAliasConstraint = "";
659 /// Assembler variant name to use for this instruction. If specified then
660 /// instruction will be presented only in MatchTable for this variant. If
661 /// not specified then assembler variants will be determined based on
663 string AsmVariantName = "";
667 /// UseNamedOperandTable - If set, the operand indices of this instruction
668 /// can be queried via the getNamedOperandIdx() function which is generated
670 bit UseNamedOperandTable = false;
672 /// Should generate helper functions that help you to map a logical operand's
673 /// index to the underlying MIOperand's index.
674 /// In most architectures logical operand indicies are equal to
675 /// MIOperand indicies, but for some CISC architectures, a logical operand
676 /// might be consist of multiple MIOperand (e.g. a logical operand that
677 /// uses complex address mode).
678 bit UseLogicalOperandMappings = false;
680 /// Should FastISel ignore this instruction. For certain ISAs, they have
681 /// instructions which map to the same ISD Opcode, value type operands and
682 /// instruction selection predicates. FastISel cannot handle such cases, but
683 /// SelectionDAG can.
684 bit FastISelShouldIgnore = false;
686 /// HasPositionOrder: Indicate tablegen to sort the instructions by record
687 /// ID, so that instruction that is defined earlier can be sorted earlier
688 /// in the assembly matching table.
689 bit HasPositionOrder = false;
692 /// Defines a Pat match between compressed and uncompressed instruction.
693 /// The relationship and helper function generation are handled by
694 /// CompressInstEmitter backend.
695 class CompressPat<dag input, dag output, list<Predicate> predicates = []> {
696 /// Uncompressed instruction description.
698 /// Compressed instruction description.
700 /// Predicates that must be true for this to match.
701 list<Predicate> Predicates = predicates;
702 /// Duplicate match when tied operand is just different.
703 bit isCompressOnly = false;
706 /// Defines an additional encoding that disassembles to the given instruction
707 /// Like Instruction, the Inst and SoftFail fields are omitted to allow targets
708 // to specify their size.
709 class AdditionalEncoding<Instruction I> : InstructionEncoding {
710 Instruction AliasOf = I;
713 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
714 /// Which instruction it expands to and how the operands map from the
716 class PseudoInstExpansion<dag Result> {
717 dag ResultInst = Result; // The instruction to generate.
721 /// Predicates - These are extra conditionals which are turned into instruction
722 /// selector matching code. Currently each predicate is just a string.
723 class Predicate<string cond> {
724 string CondString = cond;
726 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
727 /// matcher, this is true. Targets should set this by inheriting their
728 /// feature from the AssemblerPredicate class in addition to Predicate.
729 bit AssemblerMatcherPredicate = false;
731 /// AssemblerCondDag - Set of subtarget features being tested used
732 /// as alternative condition string used for assembler matcher. Must be used
733 /// with (all_of) to indicate that all features must be present, or (any_of)
734 /// to indicate that at least one must be. The required lack of presence of
735 /// a feature can be tested using a (not) node including the feature.
736 /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0".
737 /// "(all_of (not ModeThumb))" is translated to
738 /// "(Bits & ModeThumb) == 0".
739 /// "(all_of ModeThumb, FeatureThumb2)" is translated to
740 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
741 /// "(any_of ModeTumb, FeatureThumb2)" is translated to
742 /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0".
743 /// all_of and any_of cannot be combined in a single dag, instead multiple
744 /// predicates can be placed onto Instruction definitions.
745 dag AssemblerCondDag;
747 /// PredicateName - User-level name to use for the predicate. Mainly for use
748 /// in diagnostics such as missing feature errors in the asm matcher.
749 string PredicateName = "";
751 /// Setting this to '1' indicates that the predicate must be recomputed on
752 /// every function change. Most predicates can leave this at '0'.
754 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
755 bit RecomputePerFunction = false;
758 /// NoHonorSignDependentRounding - This predicate is true if support for
759 /// sign-dependent-rounding is not enabled.
760 def NoHonorSignDependentRounding
761 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
763 class Requires<list<Predicate> preds> {
764 list<Predicate> Predicates = preds;
767 /// ops definition - This is just a simple marker used to identify the operand
768 /// list for an instruction. outs and ins are identical both syntactically and
769 /// semantically; they are used to define def operands and use operands to
770 /// improve readability. This should be used like this:
771 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
776 /// variable_ops definition - Mark this instruction as taking a variable number
780 /// variable-length instruction encoding utilities.
781 /// The `ascend` operator should be used like this:
782 /// (ascend 0b0010, 0b1101)
783 /// Which represent a seqence of encoding fragments placing from LSB to MSB.
784 /// Thus, in this case the final encoding will be 0b1101_0010.
785 /// The arguments for `ascend` can either be `bits` or another DAG.
787 /// In addition, we can use `descend` to describe an encoding that places
788 /// its arguments (i.e. encoding fragments) from MSB to LSB. For instance:
789 /// (descend 0b0010, 0b1101)
790 /// This results in an encoding of 0b0010_1101.
792 /// The `operand` operator should be used like this:
793 /// (operand "$src", 4)
794 /// Which represents a 4-bit encoding for an instruction operand named `$src`.
796 /// Similar to `operand`, we can reference only part of the operand's encoding:
797 /// (slice "$src", 6, 8)
798 /// (slice "$src", 8, 6)
799 /// Both DAG represent bit 6 to 8 (total of 3 bits) in the encoding of operand
802 /// You can use `encoder` or `decoder` to specify a custom encoder or decoder
803 /// function for a specific `operand` or `slice` directive. For example:
804 /// (operand "$src", 4, (encoder "encodeMyImm"))
805 /// (slice "$src", 8, 6, (encoder "encodeMyReg"))
806 /// (operand "$src", 4, (encoder "encodeMyImm"), (decoder "decodeMyImm"))
807 /// The ordering of `encoder` and `decoder` in the same `operand` or `slice`
809 /// Note that currently we cannot assign different decoders in the same
810 /// (instruction) operand.
814 /// PointerLikeRegClass - Values that are designed to have pointer width are
815 /// derived from this. TableGen treats the register class as having a symbolic
816 /// type that it doesn't know, and resolves the actual regclass to use by using
817 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
818 class PointerLikeRegClass<int Kind> {
819 int RegClassKind = Kind;
823 /// ptr_rc definition - Mark this operand as being a pointer value whose
824 /// register class is resolved dynamically via a callback to TargetInstrInfo.
825 /// FIXME: We should probably change this to a class which contain a list of
826 /// flags. But currently we have but one flag.
827 def ptr_rc : PointerLikeRegClass<0>;
829 /// unknown definition - Mark this operand as being of unknown type, causing
830 /// it to be resolved by inference in the context it is used.
832 def unknown : unknown_class;
834 /// AsmOperandClass - Representation for the kinds of operands which the target
835 /// specific parser can create and the assembly matcher may need to distinguish.
837 /// Operand classes are used to define the order in which instructions are
838 /// matched, to ensure that the instruction which gets matched for any
839 /// particular list of operands is deterministic.
841 /// The target specific parser must be able to classify a parsed operand into a
842 /// unique class which does not partially overlap with any other classes. It can
843 /// match a subset of some other class, in which case the super class field
844 /// should be defined.
845 class AsmOperandClass {
846 /// The name to use for this class, which should be usable as an enum value.
849 /// The super classes of this operand.
850 list<AsmOperandClass> SuperClasses = [];
852 /// The name of the method on the target specific operand to call to test
853 /// whether the operand is an instance of this class. If not set, this will
854 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
855 /// signature should be:
856 /// bool isFoo() const;
857 string PredicateMethod = ?;
859 /// The name of the method on the target specific operand to call to add the
860 /// target specific operand to an MCInst. If not set, this will default to
861 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
862 /// signature should be:
863 /// void addFooOperands(MCInst &Inst, unsigned N) const;
864 string RenderMethod = ?;
866 /// The name of the method on the target specific operand to call to custom
867 /// handle the operand parsing. This is useful when the operands do not relate
868 /// to immediates or registers and are very instruction specific (as flags to
869 /// set in a processor register, coprocessor number, ...).
870 string ParserMethod = ?;
872 // The diagnostic type to present when referencing this operand in a
873 // match failure error message. By default, use a generic "invalid operand"
874 // diagnostic. The target AsmParser maps these codes to text.
875 string DiagnosticType = "";
877 /// A diagnostic message to emit when an invalid value is provided for this
879 string DiagnosticString = "";
881 /// Set to 1 if this operand is optional and not always required. Typically,
882 /// the AsmParser will emit an error when it finishes parsing an
883 /// instruction if it hasn't matched all the operands yet. However, this
884 /// error will be suppressed if all of the remaining unmatched operands are
885 /// marked as IsOptional.
887 /// Optional arguments must be at the end of the operand list.
888 bit IsOptional = false;
890 /// The name of the method on the target specific asm parser that returns the
891 /// default operand for this optional operand. This method is only used if
892 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
893 /// where Foo is the AsmOperandClass name. The method signature should be:
894 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
895 string DefaultMethod = ?;
898 def ImmAsmOperand : AsmOperandClass {
902 /// Operand Types - These provide the built-in operand types that may be used
903 /// by a target. Targets can optionally provide their own operand types as
904 /// needed, though this should not be needed for RISC targets.
905 class Operand<ValueType ty> : DAGOperand {
907 string PrintMethod = "printOperand";
908 string EncoderMethod = "";
909 bit hasCompleteDecoder = true;
910 string OperandType = "OPERAND_UNKNOWN";
911 dag MIOperandInfo = (ops);
913 // MCOperandPredicate - Optionally, a code fragment operating on
914 // const MCOperand &MCOp, and returning a bool, to indicate if
915 // the value of MCOp is valid for the specific subclass of Operand
916 code MCOperandPredicate;
918 // ParserMatchClass - The "match class" that operands of this type fit
919 // in. Match classes are used to define the order in which instructions are
920 // match, to ensure that which instructions gets matched is deterministic.
922 // The target specific parser must be able to classify an parsed operand into
923 // a unique class, which does not partially overlap with any other classes. It
924 // can match a subset of some other class, in which case the AsmOperandClass
925 // should declare the other operand as one of its super classes.
926 AsmOperandClass ParserMatchClass = ImmAsmOperand;
929 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
931 // RegClass - The register class of the operand.
932 RegisterClass RegClass = regclass;
933 // PrintMethod - The target method to call to print register operands of
934 // this type. The method normally will just use an alt-name index to look
935 // up the name to print. Default to the generic printOperand().
936 string PrintMethod = pm;
938 // EncoderMethod - The target method name to call to encode this register
940 string EncoderMethod = "";
942 // ParserMatchClass - The "match class" that operands of this type fit
943 // in. Match classes are used to define the order in which instructions are
944 // match, to ensure that which instructions gets matched is deterministic.
946 // The target specific parser must be able to classify an parsed operand into
947 // a unique class, which does not partially overlap with any other classes. It
948 // can match a subset of some other class, in which case the AsmOperandClass
949 // should declare the other operand as one of its super classes.
950 AsmOperandClass ParserMatchClass;
952 string OperandType = "OPERAND_REGISTER";
954 // When referenced in the result of a CodeGen pattern, GlobalISel will
955 // normally copy the matched operand to the result. When this is set, it will
956 // emit a special copy that will replace zero-immediates with the specified
958 Register GIZeroRegister = ?;
961 let OperandType = "OPERAND_IMMEDIATE" in {
962 def i1imm : Operand<i1>;
963 def i8imm : Operand<i8>;
964 def i16imm : Operand<i16>;
965 def i32imm : Operand<i32>;
966 def i64imm : Operand<i64>;
968 def f32imm : Operand<f32>;
969 def f64imm : Operand<f64>;
972 // Register operands for generic instructions don't have an MVT, but do have
973 // constraints linking the operands (e.g. all operands of a G_ADD must
974 // have the same LLT).
975 class TypedOperand<string Ty> : Operand<untyped> {
976 let OperandType = Ty;
977 bit IsPointer = false;
978 bit IsImmediate = false;
981 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
982 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
983 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
984 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
985 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
986 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
988 let IsPointer = true in {
989 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
990 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
991 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
992 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">;
993 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">;
994 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">;
997 // untyped_imm is for operands where isImm() will be true. It currently has no
998 // special behaviour and is only used for clarity.
999 def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> {
1000 let IsImmediate = true;
1003 /// zero_reg definition - Special node to stand for the zero register.
1007 /// undef_tied_input - Special node to indicate an input register tied
1008 /// to an output which defaults to IMPLICIT_DEF.
1009 def undef_tied_input;
1011 /// All operands which the MC layer classifies as predicates should inherit from
1012 /// this class in some manner. This is already handled for the most commonly
1013 /// used PredicateOperand, but may be useful in other circumstances.
1016 /// OperandWithDefaultOps - This Operand class can be used as the parent class
1017 /// for an Operand that needs to be initialized with a default value if
1018 /// no value is supplied in a pattern. This class can be used to simplify the
1019 /// pattern definitions for instructions that have target specific flags
1020 /// encoded as immediate operands.
1021 class OperandWithDefaultOps<ValueType ty, dag defaultops>
1023 dag DefaultOps = defaultops;
1026 /// PredicateOperand - This can be used to define a predicate operand for an
1027 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
1028 /// AlwaysVal specifies the value of this predicate when set to "always
1030 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
1031 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
1032 let MIOperandInfo = OpTypes;
1035 /// OptionalDefOperand - This is used to define a optional definition operand
1036 /// for an instruction. DefaultOps is the register the operand represents if
1037 /// none is supplied, e.g. zero_reg.
1038 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
1039 : OperandWithDefaultOps<ty, defaultops> {
1040 let MIOperandInfo = OpTypes;
1044 // InstrInfo - This class should only be instantiated once to provide parameters
1045 // which are global to the target machine.
1048 // Target can specify its instructions in either big or little-endian formats.
1049 // For instance, while both Sparc and PowerPC are big-endian platforms, the
1050 // Sparc manual specifies its instructions in the format [31..0] (big), while
1051 // PowerPC specifies them using the format [0..31] (little).
1052 bit isLittleEndianEncoding = false;
1054 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
1055 // by default, and TableGen will infer their value from the instruction
1056 // pattern when possible.
1058 // Normally, TableGen will issue an error if it can't infer the value of a
1059 // property that hasn't been set explicitly. When guessInstructionProperties
1060 // is set, it will guess a safe value instead.
1062 // This option is a temporary migration help. It will go away.
1063 bit guessInstructionProperties = true;
1066 // Standard Pseudo Instructions.
1067 // This list must match TargetOpcodes.def.
1068 // Only these instructions are allowed in the TargetOpcode namespace.
1069 // Ensure mayLoad and mayStore have a default value, so as not to break
1070 // targets that set guessInstructionProperties=0. Any local definition of
1071 // mayLoad/mayStore takes precedence over these default values.
1072 class StandardPseudoInstruction : Instruction {
1073 let mayLoad = false;
1074 let mayStore = false;
1075 let isCodeGenOnly = true;
1076 let isPseudo = true;
1077 let hasNoSchedulingInfo = true;
1078 let Namespace = "TargetOpcode";
1080 def PHI : StandardPseudoInstruction {
1081 let OutOperandList = (outs unknown:$dst);
1082 let InOperandList = (ins variable_ops);
1083 let AsmString = "PHINODE";
1084 let hasSideEffects = false;
1086 def INLINEASM : StandardPseudoInstruction {
1087 let OutOperandList = (outs);
1088 let InOperandList = (ins variable_ops);
1090 let hasSideEffects = false; // Note side effect is encoded in an operand.
1092 def INLINEASM_BR : StandardPseudoInstruction {
1093 let OutOperandList = (outs);
1094 let InOperandList = (ins variable_ops);
1096 // Unlike INLINEASM, this is always treated as having side-effects.
1097 let hasSideEffects = true;
1098 // Despite potentially branching, this instruction is intentionally _not_
1099 // marked as a terminator or a branch.
1101 def CFI_INSTRUCTION : StandardPseudoInstruction {
1102 let OutOperandList = (outs);
1103 let InOperandList = (ins i32imm:$id);
1105 let hasCtrlDep = true;
1106 let hasSideEffects = false;
1107 let isNotDuplicable = true;
1110 def EH_LABEL : StandardPseudoInstruction {
1111 let OutOperandList = (outs);
1112 let InOperandList = (ins i32imm:$id);
1114 let hasCtrlDep = true;
1115 let hasSideEffects = false;
1116 let isNotDuplicable = true;
1119 def GC_LABEL : StandardPseudoInstruction {
1120 let OutOperandList = (outs);
1121 let InOperandList = (ins i32imm:$id);
1123 let hasCtrlDep = true;
1124 let hasSideEffects = false;
1125 let isNotDuplicable = true;
1128 def ANNOTATION_LABEL : StandardPseudoInstruction {
1129 let OutOperandList = (outs);
1130 let InOperandList = (ins i32imm:$id);
1132 let hasCtrlDep = true;
1133 let hasSideEffects = false;
1134 let isNotDuplicable = true;
1136 def KILL : StandardPseudoInstruction {
1137 let OutOperandList = (outs);
1138 let InOperandList = (ins variable_ops);
1140 let hasSideEffects = false;
1143 def EXTRACT_SUBREG : StandardPseudoInstruction {
1144 let OutOperandList = (outs unknown:$dst);
1145 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
1147 let hasSideEffects = false;
1149 def INSERT_SUBREG : StandardPseudoInstruction {
1150 let OutOperandList = (outs unknown:$dst);
1151 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
1153 let hasSideEffects = false;
1154 let Constraints = "$supersrc = $dst";
1156 def IMPLICIT_DEF : StandardPseudoInstruction {
1157 let OutOperandList = (outs unknown:$dst);
1158 let InOperandList = (ins);
1160 let hasSideEffects = false;
1161 let isReMaterializable = true;
1162 let isAsCheapAsAMove = true;
1165 def SUBREG_TO_REG : StandardPseudoInstruction {
1166 let OutOperandList = (outs unknown:$dst);
1167 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
1169 let hasSideEffects = false;
1171 def COPY_TO_REGCLASS : StandardPseudoInstruction {
1172 let OutOperandList = (outs unknown:$dst);
1173 let InOperandList = (ins unknown:$src, i32imm:$regclass);
1175 let hasSideEffects = false;
1176 let isAsCheapAsAMove = true;
1178 def DBG_VALUE : StandardPseudoInstruction {
1179 let OutOperandList = (outs);
1180 let InOperandList = (ins variable_ops);
1181 let AsmString = "DBG_VALUE";
1182 let hasSideEffects = false;
1185 def DBG_VALUE_LIST : StandardPseudoInstruction {
1186 let OutOperandList = (outs);
1187 let InOperandList = (ins variable_ops);
1188 let AsmString = "DBG_VALUE_LIST";
1189 let hasSideEffects = 0;
1192 def DBG_INSTR_REF : StandardPseudoInstruction {
1193 let OutOperandList = (outs);
1194 let InOperandList = (ins variable_ops);
1195 let AsmString = "DBG_INSTR_REF";
1196 let hasSideEffects = false;
1199 def DBG_PHI : StandardPseudoInstruction {
1200 let OutOperandList = (outs);
1201 let InOperandList = (ins variable_ops);
1202 let AsmString = "DBG_PHI";
1203 let hasSideEffects = 0;
1206 def DBG_LABEL : StandardPseudoInstruction {
1207 let OutOperandList = (outs);
1208 let InOperandList = (ins unknown:$label);
1209 let AsmString = "DBG_LABEL";
1210 let hasSideEffects = false;
1213 def REG_SEQUENCE : StandardPseudoInstruction {
1214 let OutOperandList = (outs unknown:$dst);
1215 let InOperandList = (ins unknown:$supersrc, variable_ops);
1217 let hasSideEffects = false;
1218 let isAsCheapAsAMove = true;
1220 def COPY : StandardPseudoInstruction {
1221 let OutOperandList = (outs unknown:$dst);
1222 let InOperandList = (ins unknown:$src);
1224 let hasSideEffects = false;
1225 let isAsCheapAsAMove = true;
1226 let hasNoSchedulingInfo = false;
1228 def BUNDLE : StandardPseudoInstruction {
1229 let OutOperandList = (outs);
1230 let InOperandList = (ins variable_ops);
1231 let AsmString = "BUNDLE";
1232 let hasSideEffects = false;
1234 def LIFETIME_START : StandardPseudoInstruction {
1235 let OutOperandList = (outs);
1236 let InOperandList = (ins i32imm:$id);
1237 let AsmString = "LIFETIME_START";
1238 let hasSideEffects = false;
1241 def LIFETIME_END : StandardPseudoInstruction {
1242 let OutOperandList = (outs);
1243 let InOperandList = (ins i32imm:$id);
1244 let AsmString = "LIFETIME_END";
1245 let hasSideEffects = false;
1248 def PSEUDO_PROBE : StandardPseudoInstruction {
1249 let OutOperandList = (outs);
1250 let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr);
1251 let AsmString = "PSEUDO_PROBE";
1252 let hasSideEffects = 1;
1255 def ARITH_FENCE : StandardPseudoInstruction {
1256 let OutOperandList = (outs unknown:$dst);
1257 let InOperandList = (ins unknown:$src);
1259 let hasSideEffects = false;
1260 let Constraints = "$src = $dst";
1264 def STACKMAP : StandardPseudoInstruction {
1265 let OutOperandList = (outs);
1266 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
1267 let hasSideEffects = true;
1270 let usesCustomInserter = true;
1272 def PATCHPOINT : StandardPseudoInstruction {
1273 let OutOperandList = (outs unknown:$dst);
1274 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
1275 i32imm:$nargs, i32imm:$cc, variable_ops);
1276 let hasSideEffects = true;
1279 let usesCustomInserter = true;
1281 def STATEPOINT : StandardPseudoInstruction {
1282 let OutOperandList = (outs variable_ops);
1283 let InOperandList = (ins variable_ops);
1284 let usesCustomInserter = true;
1286 let mayStore = true;
1287 let hasSideEffects = true;
1290 def LOAD_STACK_GUARD : StandardPseudoInstruction {
1291 let OutOperandList = (outs ptr_rc:$dst);
1292 let InOperandList = (ins);
1294 bit isReMaterializable = true;
1295 let hasSideEffects = false;
1296 bit isPseudo = true;
1298 def PREALLOCATED_SETUP : StandardPseudoInstruction {
1299 let OutOperandList = (outs);
1300 let InOperandList = (ins i32imm:$a);
1301 let usesCustomInserter = true;
1302 let hasSideEffects = true;
1304 def PREALLOCATED_ARG : StandardPseudoInstruction {
1305 let OutOperandList = (outs ptr_rc:$loc);
1306 let InOperandList = (ins i32imm:$a, i32imm:$b);
1307 let usesCustomInserter = true;
1308 let hasSideEffects = true;
1310 def LOCAL_ESCAPE : StandardPseudoInstruction {
1311 // This instruction is really just a label. It has to be part of the chain so
1312 // that it doesn't get dropped from the DAG, but it produces nothing and has
1314 let OutOperandList = (outs);
1315 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
1316 let hasSideEffects = false;
1317 let hasCtrlDep = true;
1319 def FAULTING_OP : StandardPseudoInstruction {
1320 let OutOperandList = (outs unknown:$dst);
1321 let InOperandList = (ins variable_ops);
1322 let usesCustomInserter = true;
1323 let hasSideEffects = true;
1325 let mayStore = true;
1326 let isTerminator = true;
1327 let isBranch = true;
1329 def PATCHABLE_OP : StandardPseudoInstruction {
1330 let OutOperandList = (outs);
1331 let InOperandList = (ins variable_ops);
1332 let usesCustomInserter = true;
1334 let mayStore = true;
1335 let hasSideEffects = true;
1337 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
1338 let OutOperandList = (outs);
1339 let InOperandList = (ins);
1340 let AsmString = "# XRay Function Enter.";
1341 let usesCustomInserter = true;
1342 let hasSideEffects = true;
1344 def PATCHABLE_RET : StandardPseudoInstruction {
1345 let OutOperandList = (outs);
1346 let InOperandList = (ins variable_ops);
1347 let AsmString = "# XRay Function Patchable RET.";
1348 let usesCustomInserter = true;
1349 let hasSideEffects = true;
1350 let isTerminator = true;
1351 let isReturn = true;
1353 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
1354 let OutOperandList = (outs);
1355 let InOperandList = (ins);
1356 let AsmString = "# XRay Function Exit.";
1357 let usesCustomInserter = true;
1358 let hasSideEffects = true;
1359 let isReturn = false; // Original return instruction will follow
1361 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
1362 let OutOperandList = (outs);
1363 let InOperandList = (ins variable_ops);
1364 let AsmString = "# XRay Tail Call Exit.";
1365 let usesCustomInserter = true;
1366 let hasSideEffects = true;
1367 let isReturn = true;
1369 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
1370 let OutOperandList = (outs);
1371 let InOperandList = (ins ptr_rc:$event, unknown:$size);
1372 let AsmString = "# XRay Custom Event Log.";
1373 let usesCustomInserter = true;
1376 let mayStore = true;
1377 let hasSideEffects = true;
1379 def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
1380 let OutOperandList = (outs);
1381 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size);
1382 let AsmString = "# XRay Typed Event Log.";
1383 let usesCustomInserter = true;
1386 let mayStore = true;
1387 let hasSideEffects = true;
1389 def FENTRY_CALL : StandardPseudoInstruction {
1390 let OutOperandList = (outs);
1391 let InOperandList = (ins);
1392 let AsmString = "# FEntry call";
1393 let usesCustomInserter = true;
1396 let mayStore = true;
1397 let hasSideEffects = true;
1399 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
1400 let OutOperandList = (outs);
1401 let InOperandList = (ins variable_ops);
1403 let hasSideEffects = true;
1405 def MEMBARRIER : StandardPseudoInstruction {
1406 let OutOperandList = (outs);
1407 let InOperandList = (ins);
1409 let hasSideEffects = true;
1414 // Generic opcodes used in GlobalISel.
1415 include "llvm/Target/GenericOpcodes.td"
1417 //===----------------------------------------------------------------------===//
1418 // AsmParser - This class can be implemented by targets that wish to implement
1421 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1422 // syntax on X86 for example).
1425 // AsmParserClassName - This specifies the suffix to use for the asmparser
1426 // class. Generated AsmParser classes are always prefixed with the target
1428 string AsmParserClassName = "AsmParser";
1430 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1431 // function of the AsmParser class to call on every matched instruction.
1432 // This can be used to perform target specific instruction post-processing.
1433 string AsmParserInstCleanup = "";
1435 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1436 // written register name matcher
1437 bit ShouldEmitMatchRegisterName = true;
1439 // Set to true if the target needs a generated 'alternative register name'
1442 // This generates a function which can be used to lookup registers from
1443 // their aliases. This function will fail when called on targets where
1444 // several registers share the same alias (i.e. not a 1:1 mapping).
1445 bit ShouldEmitMatchRegisterAltName = false;
1447 // Set to true if MatchRegisterName and MatchRegisterAltName functions
1448 // should be generated even if there are duplicate register names. The
1449 // target is responsible for coercing aliased registers as necessary
1450 // (e.g. in validateTargetOperandClass), and there are no guarantees about
1451 // which numeric register identifier will be returned in the case of
1452 // multiple matches.
1453 bit AllowDuplicateRegisterNames = false;
1455 // HasMnemonicFirst - Set to false if target instructions don't always
1456 // start with a mnemonic as the first token.
1457 bit HasMnemonicFirst = true;
1459 // ReportMultipleNearMisses -
1460 // When 0, the assembly matcher reports an error for one encoding or operand
1461 // that did not match the parsed instruction.
1462 // When 1, the assembly matcher returns a list of encodings that were close
1463 // to matching the parsed instruction, so to allow more detailed error
1465 bit ReportMultipleNearMisses = false;
1467 // OperandParserMethod - If non-empty, this is the name of a custom
1468 // member function of the AsmParser class to call for every instruction
1469 // operand to be parsed.
1470 string OperandParserMethod = "";
1472 // CallCustomParserForAllOperands - Set to true if the custom parser
1473 // method shall be called for all operands as opposed to only those
1474 // that have their own specified custom parsers.
1475 bit CallCustomParserForAllOperands = false;
1477 def DefaultAsmParser : AsmParser;
1479 //===----------------------------------------------------------------------===//
1480 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1481 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1482 // implemented by targets to describe such variants.
1484 class AsmParserVariant {
1485 // Variant - AsmParsers can be of multiple different variants. Variants are
1486 // used to support targets that need to parse multiple formats for the
1487 // assembly language.
1490 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1493 // CommentDelimiter - If given, the delimiter string used to recognize
1494 // comments which are hard coded in the .td assembler strings for individual
1496 string CommentDelimiter = "";
1498 // RegisterPrefix - If given, the token prefix which indicates a register
1499 // token. This is used by the matcher to automatically recognize hard coded
1500 // register tokens as constrained registers, instead of tokens, for the
1501 // purposes of matching.
1502 string RegisterPrefix = "";
1504 // TokenizingCharacters - Characters that are standalone tokens
1505 string TokenizingCharacters = "[]*!";
1507 // SeparatorCharacters - Characters that are not tokens
1508 string SeparatorCharacters = " \t,";
1510 // BreakCharacters - Characters that start new identifiers
1511 string BreakCharacters = "";
1513 def DefaultAsmParserVariant : AsmParserVariant;
1515 // Operators for combining SubtargetFeatures in AssemblerPredicates
1519 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1520 /// matches instructions and aliases.
1521 class AssemblerPredicate<dag cond, string name = ""> {
1522 bit AssemblerMatcherPredicate = true;
1523 dag AssemblerCondDag = cond;
1524 string PredicateName = name;
1527 /// TokenAlias - This class allows targets to define assembler token
1528 /// operand aliases. That is, a token literal operand which is equivalent
1529 /// to another, canonical, token literal. For example, ARM allows:
1530 /// vmov.u32 s4, #0 -> vmov.i32, #0
1531 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1532 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1533 /// def : TokenAlias<".u32", ".i32">;
1535 /// This works by marking the match class of 'From' as a subclass of the
1536 /// match class of 'To'.
1537 class TokenAlias<string From, string To> {
1538 string FromToken = From;
1539 string ToToken = To;
1542 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1543 /// aliases. This should be used when all forms of one mnemonic are accepted
1544 /// with a different mnemonic. For example, X86 allows:
1545 /// sal %al, 1 -> shl %al, 1
1546 /// sal %ax, %cl -> shl %ax, %cl
1547 /// sal %eax, %cl -> shl %eax, %cl
1548 /// etc. Though "sal" is accepted with many forms, all of them are directly
1549 /// translated to a shl, so it can be handled with (in the case of X86, it
1550 /// actually has one for each suffix as well):
1551 /// def : MnemonicAlias<"sal", "shl">;
1553 /// Mnemonic aliases are mapped before any other translation in the match phase,
1554 /// and do allow Requires predicates, e.g.:
1556 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1557 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1559 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1561 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1563 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1564 /// applied unconditionally.
1565 class MnemonicAlias<string From, string To, string VariantName = ""> {
1566 string FromMnemonic = From;
1567 string ToMnemonic = To;
1568 string AsmVariantName = VariantName;
1570 // Predicates - Predicates that must be true for this remapping to happen.
1571 list<Predicate> Predicates = [];
1574 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1575 /// match an instruction that has a different (more canonical) assembly
1577 class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
1578 string AsmString = Asm; // The .s format to match the instruction with.
1579 dag ResultInst = Result; // The MCInst to generate.
1581 // This determines which order the InstPrinter detects aliases for
1582 // printing. A larger value makes the alias more likely to be
1583 // emitted. The Instruction's own definition is notionally 0.5, so 0
1584 // disables printing and 1 enables it if there are no conflicting aliases.
1585 int EmitPriority = Emit;
1587 // Predicates - Predicates that must be true for this to match.
1588 list<Predicate> Predicates = [];
1590 // If the instruction specified in Result has defined an AsmMatchConverter
1591 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1592 // function when converting the OperandVector into an MCInst instead of the
1593 // function that is generated by the dag Result.
1594 // Setting this to 0 will cause the alias to ignore the Result instruction's
1595 // defined AsmMatchConverter and instead use the function generated by the
1597 bit UseInstAsmMatchConverter = true;
1599 // Assembler variant name to use for this alias. If not specified then
1600 // assembler variants will be determined based on AsmString
1601 string AsmVariantName = VariantName;
1604 //===----------------------------------------------------------------------===//
1605 // AsmWriter - This class can be implemented by targets that need to customize
1606 // the format of the .s file writer.
1608 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1609 // on X86 for example).
1612 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1613 // class. Generated AsmWriter classes are always prefixed with the target
1615 string AsmWriterClassName = "InstPrinter";
1617 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1618 // the various print methods.
1619 // FIXME: Remove after all ports are updated.
1620 int PassSubtarget = 0;
1622 // Variant - AsmWriters can be of multiple different variants. Variants are
1623 // used to support targets that need to emit assembly code in ways that are
1624 // mostly the same for different targets, but have minor differences in
1625 // syntax. If the asmstring contains {|} characters in them, this integer
1626 // will specify which alternative to use. For example "{x|y|z}" with Variant
1627 // == 1, will expand to "y".
1630 def DefaultAsmWriter : AsmWriter;
1633 //===----------------------------------------------------------------------===//
1634 // Target - This class contains the "global" target information
1637 // InstructionSet - Instruction set description for this target.
1638 InstrInfo InstructionSet;
1640 // AssemblyParsers - The AsmParser instances available for this target.
1641 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1643 /// AssemblyParserVariants - The AsmParserVariant instances available for
1645 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1647 // AssemblyWriters - The AsmWriter instances available for this target.
1648 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1650 // AllowRegisterRenaming - Controls whether this target allows
1651 // post-register-allocation renaming of registers. This is done by
1652 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
1653 // for all opcodes if this flag is set to 0.
1654 int AllowRegisterRenaming = 0;
1657 //===----------------------------------------------------------------------===//
1658 // SubtargetFeature - A characteristic of the chip set.
1660 class SubtargetFeature<string n, string f, string v, string d,
1661 list<SubtargetFeature> i = []> {
1662 // Name - Feature name. Used by command line (-mattr=) to determine the
1663 // appropriate target chip.
1667 // FieldName - Field in XXXSubtarget to be set by feature.
1669 string FieldName = f;
1671 // Value - Value the XXXSubtarget field to be set to by feature.
1673 // A value of "true" or "false" implies the field is a bool. Otherwise,
1674 // it is assumed to be an integer. the integer value may be the name of an
1675 // enum constant. If multiple features use the same integer field, the
1676 // field will be set to the maximum value of all enabled features that
1681 // Desc - Feature description. Used by command line (-mattr=) to display help
1686 // Implies - Features that this feature implies are present. If one of those
1687 // features isn't set, then this one shouldn't be set either.
1689 list<SubtargetFeature> Implies = i;
1692 /// Specifies a Subtarget feature that this instruction is deprecated on.
1693 class Deprecated<SubtargetFeature dep> {
1694 SubtargetFeature DeprecatedFeatureMask = dep;
1697 /// A custom predicate used to determine if an instruction is
1698 /// deprecated or not.
1699 class ComplexDeprecationPredicate<string dep> {
1700 string ComplexDeprecationPredicate = dep;
1703 //===----------------------------------------------------------------------===//
1704 // Processor chip sets - These values represent each of the chip sets supported
1705 // by the scheduler. Each Processor definition requires corresponding
1706 // instruction itineraries.
1708 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
1709 list<SubtargetFeature> tunef = []> {
1710 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1711 // appropriate target chip.
1715 // SchedModel - The machine model for scheduling and instruction cost.
1717 SchedMachineModel SchedModel = NoSchedModel;
1719 // ProcItin - The scheduling information for the target processor.
1721 ProcessorItineraries ProcItin = pi;
1723 // Features - list of
1724 list<SubtargetFeature> Features = f;
1726 // TuneFeatures - list of features for tuning for this CPU. If the target
1727 // supports -mtune, this should contain the list of features used to make
1728 // microarchitectural optimization decisions for a given processor. While
1729 // Features should contain the architectural features for the processor.
1730 list<SubtargetFeature> TuneFeatures = tunef;
1733 // ProcessorModel allows subtargets to specify the more general
1734 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1735 // gradually move to this newer form.
1737 // Although this class always passes NoItineraries to the Processor
1738 // class, the SchedMachineModel may still define valid Itineraries.
1739 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f,
1740 list<SubtargetFeature> tunef = []>
1741 : Processor<n, NoItineraries, f, tunef> {
1745 //===----------------------------------------------------------------------===//
1746 // InstrMapping - This class is used to create mapping tables to relate
1747 // instructions with each other based on the values specified in RowFields,
1748 // ColFields, KeyCol and ValueCols.
1750 class InstrMapping {
1751 // FilterClass - Used to limit search space only to the instructions that
1752 // define the relationship modeled by this InstrMapping record.
1755 // RowFields - List of fields/attributes that should be same for all the
1756 // instructions in a row of the relation table. Think of this as a set of
1757 // properties shared by all the instructions related by this relationship
1758 // model and is used to categorize instructions into subgroups. For instance,
1759 // if we want to define a relation that maps 'Add' instruction to its
1760 // predicated forms, we can define RowFields like this:
1762 // let RowFields = BaseOp
1763 // All add instruction predicated/non-predicated will have to set their BaseOp
1764 // to the same value.
1766 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1767 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1768 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1769 list<string> RowFields = [];
1771 // List of fields/attributes that are same for all the instructions
1772 // in a column of the relation table.
1773 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1774 // based on the 'predSense' values. All the instruction in a specific
1775 // column have the same value and it is fixed for the column according
1776 // to the values set in 'ValueCols'.
1777 list<string> ColFields = [];
1779 // Values for the fields/attributes listed in 'ColFields'.
1780 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1781 // that models this relation) should be non-predicated.
1782 // In the example above, 'Add' is the key instruction.
1783 list<string> KeyCol = [];
1785 // List of values for the fields/attributes listed in 'ColFields', one for
1786 // each column in the relation table.
1788 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1789 // table. First column requires all the instructions to have predSense
1790 // set to 'true' and second column requires it to be 'false'.
1791 list<list<string> > ValueCols = [];
1794 //===----------------------------------------------------------------------===//
1795 // Pull in the common support for calling conventions.
1797 include "llvm/Target/TargetCallingConv.td"
1799 //===----------------------------------------------------------------------===//
1800 // Pull in the common support for DAG isel generation.
1802 include "llvm/Target/TargetSelectionDAG.td"
1804 //===----------------------------------------------------------------------===//
1805 // Pull in the common support for Global ISel register bank info generation.
1807 include "llvm/Target/GlobalISel/RegisterBank.td"
1809 //===----------------------------------------------------------------------===//
1810 // Pull in the common support for DAG isel generation.
1812 include "llvm/Target/GlobalISel/Target.td"
1814 //===----------------------------------------------------------------------===//
1815 // Pull in the common support for the Global ISel DAG-based selector generation.
1817 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
1819 //===----------------------------------------------------------------------===//
1820 // Pull in the common support for Pfm Counters generation.
1822 include "llvm/Target/TargetPfmCounters.td"