1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces which should be
10 // implemented by each target which is using a TableGen based code generator.
12 //===----------------------------------------------------------------------===//
14 // Include all information about LLVM intrinsics.
15 include "llvm/IR/Intrinsics.td"
17 //===----------------------------------------------------------------------===//
18 // Register file description - These classes are used to fill in the target
19 // description classes.
21 class RegisterClass; // Forward def
23 class HwMode<string FS> {
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
26 // when "feat1" is enabled and "feat2" is disabled at the same time.
27 // Any other features are not checked.
28 // When multiple modes are used, they should be mutually exclusive,
29 // otherwise the results are unpredictable.
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
36 def DefaultMode : HwMode<"">;
38 // A class used to associate objects with HW modes. It is only intended to
39 // be used as a base class, where the derived class should contain a member
40 // "Objects", which is a list of the same length as the list of modes.
41 // The n-th element on the Objects list will be associated with the n-th
42 // element on the Modes list.
43 class HwModeSelect<list<HwMode> Ms> {
44 list<HwMode> Modes = Ms;
47 // A common class that implements a counterpart of ValueType, which is
48 // dependent on a HW mode. This class inherits from ValueType itself,
49 // which makes it possible to use objects of this class where ValueType
50 // objects could be used. This is specifically applicable to selection
52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
53 : HwModeSelect<Ms>, ValueType<0, 0> {
54 // The length of this list must be the same as the length of Ms.
55 list<ValueType> Objects = Ts;
58 // A class representing the register size, spill size and spill alignment
59 // in bits of a register.
60 class RegInfo<int RS, int SS, int SA> {
61 int RegSize = RS; // Register size in bits.
62 int SpillSize = SS; // Spill slot size in bits.
63 int SpillAlignment = SA; // Spill slot alignment in bits.
66 // The register size/alignment information, parameterized by a HW mode.
67 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
69 // The length of this list must be the same as the length of Ms.
70 list<RegInfo> Objects = Ts;
73 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
74 class SubRegIndex<int size, int offset = 0> {
75 string Namespace = "";
77 // Size - Size (in bits) of the sub-registers represented by this index.
80 // Offset - Offset of the first bit that is part of this sub-register index.
81 // Set it to -1 if the same index is used to represent sub-registers that can
82 // be at different offsets (for example when using an index to access an
83 // element in a register tuple).
86 // ComposedOf - A list of two SubRegIndex instances, [A, B].
87 // This indicates that this SubRegIndex is the result of composing A and B.
88 // See ComposedSubRegIndex.
89 list<SubRegIndex> ComposedOf = [];
91 // CoveringSubRegIndices - A list of two or more sub-register indexes that
92 // cover this sub-register.
94 // This field should normally be left blank as TableGen can infer it.
96 // TableGen automatically detects sub-registers that straddle the registers
97 // in the SubRegs field of a Register definition. For example:
99 // Q0 = dsub_0 -> D0, dsub_1 -> D1
100 // Q1 = dsub_0 -> D2, dsub_1 -> D3
101 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
102 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
104 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
105 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
106 // CoveringSubRegIndices = [dsub_1, dsub_2].
107 list<SubRegIndex> CoveringSubRegIndices = [];
110 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
111 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
112 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
113 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
114 !if(!eq(B.Offset, -1), -1,
115 !add(A.Offset, B.Offset)))> {
117 let ComposedOf = [A, B];
120 // RegAltNameIndex - The alternate name set to use for register operands of
121 // this register class when printing.
122 class RegAltNameIndex {
123 string Namespace = "";
125 // A set to be used if the name for a register is not defined in this set.
126 // This allows creating name sets with only a few alternative names.
127 RegAltNameIndex FallbackRegAltNameIndex = ?;
129 def NoRegAltName : RegAltNameIndex;
131 // Register - You should define one instance of this class for each register
132 // in the target machine. String n will become the "name" of the register.
133 class Register<string n, list<string> altNames = []> {
134 string Namespace = "";
136 list<string> AltNames = altNames;
138 // Aliases - A list of registers that this register overlaps with. A read or
139 // modification of this register can potentially read or modify the aliased
141 list<Register> Aliases = [];
143 // SubRegs - A list of registers that are parts of this register. Note these
144 // are "immediate" sub-registers and the registers within the list do not
145 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
147 list<Register> SubRegs = [];
149 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
150 // to address it. Sub-sub-register indices are automatically inherited from
152 list<SubRegIndex> SubRegIndices = [];
154 // RegAltNameIndices - The alternate name indices which are valid for this
156 list<RegAltNameIndex> RegAltNameIndices = [];
158 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
159 // These values can be determined by locating the <target>.h file in the
160 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
161 // order of these names correspond to the enumeration used by gcc. A value of
162 // -1 indicates that the gcc number is undefined and -2 that register number
163 // is invalid for this mode/flavour.
164 list<int> DwarfNumbers = [];
166 // CostPerUse - Additional cost of instructions using this register compared
167 // to other registers in its class. The register allocator will try to
168 // minimize the number of instructions using a register with a CostPerUse.
169 // This is used by the x86-64 and ARM Thumb targets where some registers
170 // require larger instruction encodings.
173 // CoveredBySubRegs - When this bit is set, the value of this register is
174 // completely determined by the value of its sub-registers. For example, the
175 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
176 // covered by its sub-register AX.
177 bit CoveredBySubRegs = 0;
179 // HWEncoding - The target specific hardware encoding for this register.
180 bits<16> HWEncoding = 0;
182 bit isArtificial = 0;
185 // RegisterWithSubRegs - This can be used to define instances of Register which
186 // need to specify sub-registers.
187 // List "subregs" specifies which registers are sub-registers to this one. This
188 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
189 // This allows the code generator to be careful not to put two values with
190 // overlapping live ranges into registers which alias.
191 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
192 let SubRegs = subregs;
195 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
196 // of Operand's that are legal as type qualifiers in DAG patterns. This should
197 // only ever be used for defining multiclasses that are polymorphic over both
198 // RegisterClass's and other Operand's.
200 string OperandNamespace = "MCOI";
201 string DecoderMethod = "";
204 // RegisterClass - Now that all of the registers are defined, and aliases
205 // between registers are defined, specify which registers belong to which
206 // register classes. This also defines the default allocation order of
207 // registers by register allocators.
209 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
210 dag regList, RegAltNameIndex idx = NoRegAltName>
212 string Namespace = namespace;
214 // The register size/alignment information, parameterized by a HW mode.
215 RegInfoByHwMode RegInfos;
217 // RegType - Specify the list ValueType of the registers in this register
218 // class. Note that all registers in a register class must have the same
219 // ValueTypes. This is a list because some targets permit storing different
220 // types in same register, for example vector values with 128-bit total size,
221 // but different count/size of items, like SSE on x86.
223 list<ValueType> RegTypes = regTypes;
225 // Size - Specify the spill size in bits of the registers. A default value of
226 // zero lets tablgen pick an appropriate size.
229 // Alignment - Specify the alignment required of the registers when they are
230 // stored or loaded to memory.
232 int Alignment = alignment;
234 // CopyCost - This value is used to specify the cost of copying a value
235 // between two registers in this register class. The default value is one
236 // meaning it takes a single instruction to perform the copying. A negative
237 // value means copying is extremely expensive or impossible.
240 // MemberList - Specify which registers are in this class. If the
241 // allocation_order_* method are not specified, this also defines the order of
242 // allocation used by the register allocator.
244 dag MemberList = regList;
246 // AltNameIndex - The alternate register name to use when printing operands
247 // of this register class. Every register in the register class must have
248 // a valid alternate name for the given index.
249 RegAltNameIndex altNameIndex = idx;
251 // isAllocatable - Specify that the register class can be used for virtual
252 // registers and register allocation. Some register classes are only used to
253 // model instruction operand constraints, and should have isAllocatable = 0.
254 bit isAllocatable = 1;
256 // AltOrders - List of alternative allocation orders. The default order is
257 // MemberList itself, and that is good enough for most targets since the
258 // register allocators automatically remove reserved registers and move
259 // callee-saved registers to the end.
260 list<dag> AltOrders = [];
262 // AltOrderSelect - The body of a function that selects the allocation order
263 // to use in a given machine function. The code will be inserted in a
264 // function like this:
266 // static inline unsigned f(const MachineFunction &MF) { ... }
268 // The function should return 0 to select the default order defined by
269 // MemberList, 1 to select the first AltOrders entry and so on.
270 code AltOrderSelect = [{}];
272 // Specify allocation priority for register allocators using a greedy
273 // heuristic. Classes with higher priority values are assigned first. This is
274 // useful as it is sometimes beneficial to assign registers to highly
275 // constrained classes first. The value has to be in the range [0,63].
276 int AllocationPriority = 0;
278 // The diagnostic type to present when referencing this operand in a match
279 // failure error message. If this is empty, the default Match_InvalidOperand
280 // diagnostic type will be used. If this is "<name>", a Match_<name> enum
281 // value will be generated and used for this operand type. The target
282 // assembly parser is responsible for converting this into a user-facing
283 // diagnostic message.
284 string DiagnosticType = "";
286 // A diagnostic message to emit when an invalid value is provided for this
287 // register class when it is being used an an assembly operand. If this is
288 // non-empty, an anonymous diagnostic type enum value will be generated, and
289 // the assembly matcher will provide a function to map from diagnostic types
290 // to message strings.
291 string DiagnosticString = "";
294 // The memberList in a RegisterClass is a dag of set operations. TableGen
295 // evaluates these set operations and expand them into register lists. These
296 // are the most common operation, see test/TableGen/SetTheory.td for more
297 // examples of what is possible:
299 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
300 // register class, or a sub-expression. This is also the way to simply list
303 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
305 // (and GPR, CSR) - Set intersection. All registers from the first set that are
306 // also in the second set.
308 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
309 // numbered registers. Takes an optional 4th operand which is a stride to use
310 // when generating the sequence.
312 // (shl GPR, 4) - Remove the first N elements.
314 // (trunc GPR, 4) - Truncate after the first N elements.
316 // (rotl GPR, 1) - Rotate N places to the left.
318 // (rotr GPR, 1) - Rotate N places to the right.
320 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
322 // (interleave A, B, ...) - Interleave the elements from each argument list.
324 // All of these operators work on ordered sets, not lists. That means
325 // duplicates are removed from sub-expressions.
327 // Set operators. The rest is defined in TargetSelectionDAG.td.
332 // RegisterTuples - Automatically generate super-registers by forming tuples of
333 // sub-registers. This is useful for modeling register sequence constraints
334 // with pseudo-registers that are larger than the architectural registers.
336 // The sub-register lists are zipped together:
338 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
340 // Generates the same registers as:
342 // let SubRegIndices = [sube, subo] in {
343 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
344 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
347 // The generated pseudo-registers inherit super-classes and fields from their
348 // first sub-register. Most fields from the Register class are inferred, and
349 // the AsmName and Dwarf numbers are cleared.
351 // RegisterTuples instances can be used in other set operations to form
352 // register classes and so on. This is the only way of using the generated
354 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
355 // SubRegs - N lists of registers to be zipped up. Super-registers are
356 // synthesized from the first element of each SubRegs list, the second
357 // element and so on.
358 list<dag> SubRegs = Regs;
360 // SubRegIndices - N SubRegIndex instances. This provides the names of the
361 // sub-registers in the synthesized super-registers.
362 list<SubRegIndex> SubRegIndices = Indices;
366 //===----------------------------------------------------------------------===//
367 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
368 // to the register numbering used by gcc and gdb. These values are used by a
369 // debug information writer to describe where values may be located during
371 class DwarfRegNum<list<int> Numbers> {
372 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
373 // These values can be determined by locating the <target>.h file in the
374 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
375 // order of these names correspond to the enumeration used by gcc. A value of
376 // -1 indicates that the gcc number is undefined and -2 that register number
377 // is invalid for this mode/flavour.
378 list<int> DwarfNumbers = Numbers;
381 // DwarfRegAlias - This class declares that a given register uses the same dwarf
382 // numbers as another one. This is useful for making it clear that the two
383 // registers do have the same number. It also lets us build a mapping
384 // from dwarf register number to llvm register.
385 class DwarfRegAlias<Register reg> {
386 Register DwarfAlias = reg;
389 //===----------------------------------------------------------------------===//
390 // Pull in the common support for MCPredicate (portable scheduling predicates).
392 include "llvm/Target/TargetInstrPredicate.td"
394 //===----------------------------------------------------------------------===//
395 // Pull in the common support for scheduling
397 include "llvm/Target/TargetSchedule.td"
399 class Predicate; // Forward def
401 class InstructionEncoding {
402 // Size of encoded instruction.
405 // The "namespace" in which this instruction exists, on targets like ARM
406 // which multiple ISA namespaces exist.
407 string DecoderNamespace = "";
409 // List of predicates which will be turned into isel matching code.
410 list<Predicate> Predicates = [];
412 string DecoderMethod = "";
414 // Is the instruction decoder method able to completely determine if the
415 // given instruction is valid or not. If the TableGen definition of the
416 // instruction specifies bitpattern A??B where A and B are static bits, the
417 // hasCompleteDecoder flag says whether the decoder method fully handles the
418 // ?? space, i.e. if it is a final arbiter for the instruction validity.
419 // If not then the decoder attempts to continue decoding when the decoder
422 // This allows to handle situations where the encoding is not fully
423 // orthogonal. Example:
424 // * InstA with bitpattern 0b0000????,
425 // * InstB with bitpattern 0b000000?? but the associated decoder method
426 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
428 // The decoder tries to decode a bitpattern that matches both InstA and
429 // InstB bitpatterns first as InstB (because it is the most specific
430 // encoding). In the default case (hasCompleteDecoder = 1), when
431 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
432 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
433 // DecodeInstB() is not able to determine if all possible values of ?? are
434 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
435 // decode the bitpattern as InstA too.
436 bit hasCompleteDecoder = 1;
439 //===----------------------------------------------------------------------===//
440 // Instruction set description - These classes correspond to the C++ classes in
441 // the Target/TargetInstrInfo.h file.
443 class Instruction : InstructionEncoding {
444 string Namespace = "";
446 dag OutOperandList; // An dag containing the MI def operand list.
447 dag InOperandList; // An dag containing the MI use operand list.
448 string AsmString = ""; // The .s format to print the instruction with.
450 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
451 // otherwise, uninitialized.
454 // The follow state will eventually be inferred automatically from the
455 // instruction pattern.
457 list<Register> Uses = []; // Default to using no non-operand registers
458 list<Register> Defs = []; // Default to modifying no non-operand registers
460 // Predicates - List of predicates which will be turned into isel matching
462 list<Predicate> Predicates = [];
464 // Size - Size of encoded instruction, or zero if the size cannot be determined
468 // Code size, for instruction selection.
469 // FIXME: What does this actually mean?
472 // Added complexity passed onto matching pattern.
473 int AddedComplexity = 0;
475 // These bits capture information about the high-level semantics of the
477 bit isReturn = 0; // Is this instruction a return instruction?
478 bit isBranch = 0; // Is this instruction a branch instruction?
479 bit isEHScopeReturn = 0; // Does this instruction end an EH scope?
480 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
481 bit isCompare = 0; // Is this instruction a comparison instruction?
482 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
483 bit isMoveReg = 0; // Is this instruction a move register instruction?
484 bit isBitcast = 0; // Is this instruction a bitcast instruction?
485 bit isSelect = 0; // Is this instruction a select instruction?
486 bit isBarrier = 0; // Can control flow fall through this instruction?
487 bit isCall = 0; // Is this instruction a call instruction?
488 bit isAdd = 0; // Is this instruction an add instruction?
489 bit isTrap = 0; // Is this instruction a trap instruction?
490 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
491 bit mayLoad = ?; // Is it possible for this inst to read memory?
492 bit mayStore = ?; // Is it possible for this inst to write memory?
493 bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
494 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
495 bit isCommutable = 0; // Is this 3 operand instruction commutable?
496 bit isTerminator = 0; // Is this part of the terminator for a basic block?
497 bit isReMaterializable = 0; // Is this instruction re-materializable?
498 bit isPredicable = 0; // 1 means this instruction is predicable
499 // even if it does not have any operand
500 // tablegen can identify as a predicate
501 bit isUnpredicable = 0; // 1 means this instruction is not predicable
502 // even if it _does_ have a predicate operand
503 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
504 bit usesCustomInserter = 0; // Pseudo instr needing special help.
505 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
506 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
507 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
508 bit isConvergent = 0; // Is this instruction convergent?
509 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
510 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
511 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
512 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
513 // If so, make sure to override
514 // TargetInstrInfo::getRegSequenceLikeInputs.
515 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
516 // If so, won't have encoding information for
517 // the [MC]CodeEmitter stuff.
518 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
519 // If so, make sure to override
520 // TargetInstrInfo::getExtractSubregLikeInputs.
521 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
522 // If so, make sure to override
523 // TargetInstrInfo::getInsertSubregLikeInputs.
524 bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
526 // Does the instruction have side effects that are not captured by any
527 // operands of the instruction or other flags?
528 bit hasSideEffects = ?;
530 // Is this instruction a "real" instruction (with a distinct machine
531 // encoding), or is it a pseudo instruction used for codegen modeling
533 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
534 // instructions can (and often do) still have encoding information
535 // associated with them. Once we've migrated all of them over to true
536 // pseudo-instructions that are lowered to real instructions prior to
537 // the printer/emitter, we can remove this attribute and just use isPseudo.
539 // The intended use is:
540 // isPseudo: Does not have encoding information and should be expanded,
541 // at the latest, during lowering to MCInst.
543 // isCodeGenOnly: Does have encoding information and can go through to the
544 // CodeEmitter unchanged, but duplicates a canonical instruction
545 // definition's encoding and should be ignored when constructing the
546 // assembler match tables.
547 bit isCodeGenOnly = 0;
549 // Is this instruction a pseudo instruction for use by the assembler parser.
550 bit isAsmParserOnly = 0;
552 // This instruction is not expected to be queried for scheduling latencies
553 // and therefore needs no scheduling information even for a complete
555 bit hasNoSchedulingInfo = 0;
557 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
559 // Scheduling information from TargetSchedule.td.
560 list<SchedReadWrite> SchedRW;
562 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
564 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
565 /// be encoded into the output machineinstr.
566 string DisableEncoding = "";
568 string PostEncoderMethod = "";
570 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
571 bits<64> TSFlags = 0;
573 ///@name Assembler Parser Support
576 string AsmMatchConverter = "";
578 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
579 /// two-operand matcher inst-alias for a three operand instruction.
580 /// For example, the arm instruction "add r3, r3, r5" can be written
581 /// as "add r3, r5". The constraint is of the same form as a tied-operand
582 /// constraint. For example, "$Rn = $Rd".
583 string TwoOperandAliasConstraint = "";
585 /// Assembler variant name to use for this instruction. If specified then
586 /// instruction will be presented only in MatchTable for this variant. If
587 /// not specified then assembler variants will be determined based on
589 string AsmVariantName = "";
593 /// UseNamedOperandTable - If set, the operand indices of this instruction
594 /// can be queried via the getNamedOperandIdx() function which is generated
596 bit UseNamedOperandTable = 0;
598 /// Should FastISel ignore this instruction. For certain ISAs, they have
599 /// instructions which map to the same ISD Opcode, value type operands and
600 /// instruction selection predicates. FastISel cannot handle such cases, but
601 /// SelectionDAG can.
602 bit FastISelShouldIgnore = 0;
605 /// Defines an additional encoding that disassembles to the given instruction
606 /// Like Instruction, the Inst and SoftFail fields are omitted to allow targets
607 // to specify their size.
608 class AdditionalEncoding<Instruction I> : InstructionEncoding {
609 Instruction AliasOf = I;
612 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
613 /// Which instruction it expands to and how the operands map from the
615 class PseudoInstExpansion<dag Result> {
616 dag ResultInst = Result; // The instruction to generate.
620 /// Predicates - These are extra conditionals which are turned into instruction
621 /// selector matching code. Currently each predicate is just a string.
622 class Predicate<string cond> {
623 string CondString = cond;
625 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
626 /// matcher, this is true. Targets should set this by inheriting their
627 /// feature from the AssemblerPredicate class in addition to Predicate.
628 bit AssemblerMatcherPredicate = 0;
630 /// AssemblerCondString - Name of the subtarget feature being tested used
631 /// as alternative condition string used for assembler matcher.
632 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
633 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
634 /// It can also list multiple features separated by ",".
635 /// e.g. "ModeThumb,FeatureThumb2" is translated to
636 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
637 string AssemblerCondString = "";
639 /// PredicateName - User-level name to use for the predicate. Mainly for use
640 /// in diagnostics such as missing feature errors in the asm matcher.
641 string PredicateName = "";
643 /// Setting this to '1' indicates that the predicate must be recomputed on
644 /// every function change. Most predicates can leave this at '0'.
646 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
647 bit RecomputePerFunction = 0;
650 /// NoHonorSignDependentRounding - This predicate is true if support for
651 /// sign-dependent-rounding is not enabled.
652 def NoHonorSignDependentRounding
653 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
655 class Requires<list<Predicate> preds> {
656 list<Predicate> Predicates = preds;
659 /// ops definition - This is just a simple marker used to identify the operand
660 /// list for an instruction. outs and ins are identical both syntactically and
661 /// semantically; they are used to define def operands and use operands to
662 /// improve readibility. This should be used like this:
663 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
668 /// variable_ops definition - Mark this instruction as taking a variable number
673 /// PointerLikeRegClass - Values that are designed to have pointer width are
674 /// derived from this. TableGen treats the register class as having a symbolic
675 /// type that it doesn't know, and resolves the actual regclass to use by using
676 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
677 class PointerLikeRegClass<int Kind> {
678 int RegClassKind = Kind;
682 /// ptr_rc definition - Mark this operand as being a pointer value whose
683 /// register class is resolved dynamically via a callback to TargetInstrInfo.
684 /// FIXME: We should probably change this to a class which contain a list of
685 /// flags. But currently we have but one flag.
686 def ptr_rc : PointerLikeRegClass<0>;
688 /// unknown definition - Mark this operand as being of unknown type, causing
689 /// it to be resolved by inference in the context it is used.
691 def unknown : unknown_class;
693 /// AsmOperandClass - Representation for the kinds of operands which the target
694 /// specific parser can create and the assembly matcher may need to distinguish.
696 /// Operand classes are used to define the order in which instructions are
697 /// matched, to ensure that the instruction which gets matched for any
698 /// particular list of operands is deterministic.
700 /// The target specific parser must be able to classify a parsed operand into a
701 /// unique class which does not partially overlap with any other classes. It can
702 /// match a subset of some other class, in which case the super class field
703 /// should be defined.
704 class AsmOperandClass {
705 /// The name to use for this class, which should be usable as an enum value.
708 /// The super classes of this operand.
709 list<AsmOperandClass> SuperClasses = [];
711 /// The name of the method on the target specific operand to call to test
712 /// whether the operand is an instance of this class. If not set, this will
713 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
714 /// signature should be:
715 /// bool isFoo() const;
716 string PredicateMethod = ?;
718 /// The name of the method on the target specific operand to call to add the
719 /// target specific operand to an MCInst. If not set, this will default to
720 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
721 /// signature should be:
722 /// void addFooOperands(MCInst &Inst, unsigned N) const;
723 string RenderMethod = ?;
725 /// The name of the method on the target specific operand to call to custom
726 /// handle the operand parsing. This is useful when the operands do not relate
727 /// to immediates or registers and are very instruction specific (as flags to
728 /// set in a processor register, coprocessor number, ...).
729 string ParserMethod = ?;
731 // The diagnostic type to present when referencing this operand in a
732 // match failure error message. By default, use a generic "invalid operand"
733 // diagnostic. The target AsmParser maps these codes to text.
734 string DiagnosticType = "";
736 /// A diagnostic message to emit when an invalid value is provided for this
738 string DiagnosticString = "";
740 /// Set to 1 if this operand is optional and not always required. Typically,
741 /// the AsmParser will emit an error when it finishes parsing an
742 /// instruction if it hasn't matched all the operands yet. However, this
743 /// error will be suppressed if all of the remaining unmatched operands are
744 /// marked as IsOptional.
746 /// Optional arguments must be at the end of the operand list.
749 /// The name of the method on the target specific asm parser that returns the
750 /// default operand for this optional operand. This method is only used if
751 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
752 /// where Foo is the AsmOperandClass name. The method signature should be:
753 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
754 string DefaultMethod = ?;
757 def ImmAsmOperand : AsmOperandClass {
761 /// Operand Types - These provide the built-in operand types that may be used
762 /// by a target. Targets can optionally provide their own operand types as
763 /// needed, though this should not be needed for RISC targets.
764 class Operand<ValueType ty> : DAGOperand {
766 string PrintMethod = "printOperand";
767 string EncoderMethod = "";
768 bit hasCompleteDecoder = 1;
769 string OperandType = "OPERAND_UNKNOWN";
770 dag MIOperandInfo = (ops);
772 // MCOperandPredicate - Optionally, a code fragment operating on
773 // const MCOperand &MCOp, and returning a bool, to indicate if
774 // the value of MCOp is valid for the specific subclass of Operand
775 code MCOperandPredicate;
777 // ParserMatchClass - The "match class" that operands of this type fit
778 // in. Match classes are used to define the order in which instructions are
779 // match, to ensure that which instructions gets matched is deterministic.
781 // The target specific parser must be able to classify an parsed operand into
782 // a unique class, which does not partially overlap with any other classes. It
783 // can match a subset of some other class, in which case the AsmOperandClass
784 // should declare the other operand as one of its super classes.
785 AsmOperandClass ParserMatchClass = ImmAsmOperand;
788 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
790 // RegClass - The register class of the operand.
791 RegisterClass RegClass = regclass;
792 // PrintMethod - The target method to call to print register operands of
793 // this type. The method normally will just use an alt-name index to look
794 // up the name to print. Default to the generic printOperand().
795 string PrintMethod = pm;
797 // EncoderMethod - The target method name to call to encode this register
799 string EncoderMethod = "";
801 // ParserMatchClass - The "match class" that operands of this type fit
802 // in. Match classes are used to define the order in which instructions are
803 // match, to ensure that which instructions gets matched is deterministic.
805 // The target specific parser must be able to classify an parsed operand into
806 // a unique class, which does not partially overlap with any other classes. It
807 // can match a subset of some other class, in which case the AsmOperandClass
808 // should declare the other operand as one of its super classes.
809 AsmOperandClass ParserMatchClass;
811 string OperandType = "OPERAND_REGISTER";
813 // When referenced in the result of a CodeGen pattern, GlobalISel will
814 // normally copy the matched operand to the result. When this is set, it will
815 // emit a special copy that will replace zero-immediates with the specified
817 Register GIZeroRegister = ?;
820 let OperandType = "OPERAND_IMMEDIATE" in {
821 def i1imm : Operand<i1>;
822 def i8imm : Operand<i8>;
823 def i16imm : Operand<i16>;
824 def i32imm : Operand<i32>;
825 def i64imm : Operand<i64>;
827 def f32imm : Operand<f32>;
828 def f64imm : Operand<f64>;
831 // Register operands for generic instructions don't have an MVT, but do have
832 // constraints linking the operands (e.g. all operands of a G_ADD must
833 // have the same LLT).
834 class TypedOperand<string Ty> : Operand<untyped> {
835 let OperandType = Ty;
839 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
840 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
841 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
842 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
843 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
844 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
846 let IsPointer = 1 in {
847 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
848 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
849 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
850 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">;
851 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">;
852 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">;
855 /// zero_reg definition - Special node to stand for the zero register.
859 /// All operands which the MC layer classifies as predicates should inherit from
860 /// this class in some manner. This is already handled for the most commonly
861 /// used PredicateOperand, but may be useful in other circumstances.
864 /// OperandWithDefaultOps - This Operand class can be used as the parent class
865 /// for an Operand that needs to be initialized with a default value if
866 /// no value is supplied in a pattern. This class can be used to simplify the
867 /// pattern definitions for instructions that have target specific flags
868 /// encoded as immediate operands.
869 class OperandWithDefaultOps<ValueType ty, dag defaultops>
871 dag DefaultOps = defaultops;
874 /// PredicateOperand - This can be used to define a predicate operand for an
875 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
876 /// AlwaysVal specifies the value of this predicate when set to "always
878 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
879 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
880 let MIOperandInfo = OpTypes;
883 /// OptionalDefOperand - This is used to define a optional definition operand
884 /// for an instruction. DefaultOps is the register the operand represents if
885 /// none is supplied, e.g. zero_reg.
886 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
887 : OperandWithDefaultOps<ty, defaultops> {
888 let MIOperandInfo = OpTypes;
892 // InstrInfo - This class should only be instantiated once to provide parameters
893 // which are global to the target machine.
896 // Target can specify its instructions in either big or little-endian formats.
897 // For instance, while both Sparc and PowerPC are big-endian platforms, the
898 // Sparc manual specifies its instructions in the format [31..0] (big), while
899 // PowerPC specifies them using the format [0..31] (little).
900 bit isLittleEndianEncoding = 0;
902 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
903 // by default, and TableGen will infer their value from the instruction
904 // pattern when possible.
906 // Normally, TableGen will issue an error it it can't infer the value of a
907 // property that hasn't been set explicitly. When guessInstructionProperties
908 // is set, it will guess a safe value instead.
910 // This option is a temporary migration help. It will go away.
911 bit guessInstructionProperties = 1;
913 // TableGen's instruction encoder generator has support for matching operands
914 // to bit-field variables both by name and by position. While matching by
915 // name is preferred, this is currently not possible for complex operands,
916 // and some targets still reply on the positional encoding rules. When
917 // generating a decoder for such targets, the positional encoding rules must
918 // be used by the decoder generator as well.
920 // This option is temporary; it will go away once the TableGen decoder
921 // generator has better support for complex operands and targets have
922 // migrated away from using positionally encoded operands.
923 bit decodePositionallyEncodedOperands = 0;
925 // When set, this indicates that there will be no overlap between those
926 // operands that are matched by ordering (positional operands) and those
929 // This option is temporary; it will go away once the TableGen decoder
930 // generator has better support for complex operands and targets have
931 // migrated away from using positionally encoded operands.
932 bit noNamedPositionallyEncodedOperands = 0;
935 // Standard Pseudo Instructions.
936 // This list must match TargetOpcodes.def.
937 // Only these instructions are allowed in the TargetOpcode namespace.
938 // Ensure mayLoad and mayStore have a default value, so as not to break
939 // targets that set guessInstructionProperties=0. Any local definition of
940 // mayLoad/mayStore takes precedence over these default values.
941 class StandardPseudoInstruction : Instruction {
944 let isCodeGenOnly = 1;
946 let hasNoSchedulingInfo = 1;
947 let Namespace = "TargetOpcode";
949 def PHI : StandardPseudoInstruction {
950 let OutOperandList = (outs unknown:$dst);
951 let InOperandList = (ins variable_ops);
952 let AsmString = "PHINODE";
953 let hasSideEffects = 0;
955 def INLINEASM : StandardPseudoInstruction {
956 let OutOperandList = (outs);
957 let InOperandList = (ins variable_ops);
959 let hasSideEffects = 0; // Note side effect is encoded in an operand.
961 def INLINEASM_BR : StandardPseudoInstruction {
962 let OutOperandList = (outs);
963 let InOperandList = (ins variable_ops);
965 let hasSideEffects = 0; // Note side effect is encoded in an operand.
966 let isTerminator = 1;
968 let isIndirectBranch = 1;
970 def CFI_INSTRUCTION : StandardPseudoInstruction {
971 let OutOperandList = (outs);
972 let InOperandList = (ins i32imm:$id);
975 let hasSideEffects = 0;
976 let isNotDuplicable = 1;
978 def EH_LABEL : StandardPseudoInstruction {
979 let OutOperandList = (outs);
980 let InOperandList = (ins i32imm:$id);
983 let hasSideEffects = 0;
984 let isNotDuplicable = 1;
986 def GC_LABEL : StandardPseudoInstruction {
987 let OutOperandList = (outs);
988 let InOperandList = (ins i32imm:$id);
991 let hasSideEffects = 0;
992 let isNotDuplicable = 1;
994 def ANNOTATION_LABEL : StandardPseudoInstruction {
995 let OutOperandList = (outs);
996 let InOperandList = (ins i32imm:$id);
999 let hasSideEffects = 0;
1000 let isNotDuplicable = 1;
1002 def KILL : StandardPseudoInstruction {
1003 let OutOperandList = (outs);
1004 let InOperandList = (ins variable_ops);
1006 let hasSideEffects = 0;
1008 def EXTRACT_SUBREG : StandardPseudoInstruction {
1009 let OutOperandList = (outs unknown:$dst);
1010 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
1012 let hasSideEffects = 0;
1014 def INSERT_SUBREG : StandardPseudoInstruction {
1015 let OutOperandList = (outs unknown:$dst);
1016 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
1018 let hasSideEffects = 0;
1019 let Constraints = "$supersrc = $dst";
1021 def IMPLICIT_DEF : StandardPseudoInstruction {
1022 let OutOperandList = (outs unknown:$dst);
1023 let InOperandList = (ins);
1025 let hasSideEffects = 0;
1026 let isReMaterializable = 1;
1027 let isAsCheapAsAMove = 1;
1029 def SUBREG_TO_REG : StandardPseudoInstruction {
1030 let OutOperandList = (outs unknown:$dst);
1031 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
1033 let hasSideEffects = 0;
1035 def COPY_TO_REGCLASS : StandardPseudoInstruction {
1036 let OutOperandList = (outs unknown:$dst);
1037 let InOperandList = (ins unknown:$src, i32imm:$regclass);
1039 let hasSideEffects = 0;
1040 let isAsCheapAsAMove = 1;
1042 def DBG_VALUE : StandardPseudoInstruction {
1043 let OutOperandList = (outs);
1044 let InOperandList = (ins variable_ops);
1045 let AsmString = "DBG_VALUE";
1046 let hasSideEffects = 0;
1048 def DBG_LABEL : StandardPseudoInstruction {
1049 let OutOperandList = (outs);
1050 let InOperandList = (ins unknown:$label);
1051 let AsmString = "DBG_LABEL";
1052 let hasSideEffects = 0;
1054 def REG_SEQUENCE : StandardPseudoInstruction {
1055 let OutOperandList = (outs unknown:$dst);
1056 let InOperandList = (ins unknown:$supersrc, variable_ops);
1058 let hasSideEffects = 0;
1059 let isAsCheapAsAMove = 1;
1061 def COPY : StandardPseudoInstruction {
1062 let OutOperandList = (outs unknown:$dst);
1063 let InOperandList = (ins unknown:$src);
1065 let hasSideEffects = 0;
1066 let isAsCheapAsAMove = 1;
1067 let hasNoSchedulingInfo = 0;
1069 def BUNDLE : StandardPseudoInstruction {
1070 let OutOperandList = (outs);
1071 let InOperandList = (ins variable_ops);
1072 let AsmString = "BUNDLE";
1073 let hasSideEffects = 0;
1075 def LIFETIME_START : StandardPseudoInstruction {
1076 let OutOperandList = (outs);
1077 let InOperandList = (ins i32imm:$id);
1078 let AsmString = "LIFETIME_START";
1079 let hasSideEffects = 0;
1081 def LIFETIME_END : StandardPseudoInstruction {
1082 let OutOperandList = (outs);
1083 let InOperandList = (ins i32imm:$id);
1084 let AsmString = "LIFETIME_END";
1085 let hasSideEffects = 0;
1087 def STACKMAP : StandardPseudoInstruction {
1088 let OutOperandList = (outs);
1089 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
1090 let hasSideEffects = 1;
1093 let usesCustomInserter = 1;
1095 def PATCHPOINT : StandardPseudoInstruction {
1096 let OutOperandList = (outs unknown:$dst);
1097 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
1098 i32imm:$nargs, i32imm:$cc, variable_ops);
1099 let hasSideEffects = 1;
1102 let usesCustomInserter = 1;
1104 def STATEPOINT : StandardPseudoInstruction {
1105 let OutOperandList = (outs);
1106 let InOperandList = (ins variable_ops);
1107 let usesCustomInserter = 1;
1110 let hasSideEffects = 1;
1113 def LOAD_STACK_GUARD : StandardPseudoInstruction {
1114 let OutOperandList = (outs ptr_rc:$dst);
1115 let InOperandList = (ins);
1117 bit isReMaterializable = 1;
1118 let hasSideEffects = 0;
1121 def LOCAL_ESCAPE : StandardPseudoInstruction {
1122 // This instruction is really just a label. It has to be part of the chain so
1123 // that it doesn't get dropped from the DAG, but it produces nothing and has
1125 let OutOperandList = (outs);
1126 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
1127 let hasSideEffects = 0;
1130 def FAULTING_OP : StandardPseudoInstruction {
1131 let OutOperandList = (outs unknown:$dst);
1132 let InOperandList = (ins variable_ops);
1133 let usesCustomInserter = 1;
1134 let hasSideEffects = 1;
1137 let isTerminator = 1;
1140 def PATCHABLE_OP : StandardPseudoInstruction {
1141 let OutOperandList = (outs);
1142 let InOperandList = (ins variable_ops);
1143 let usesCustomInserter = 1;
1146 let hasSideEffects = 1;
1148 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
1149 let OutOperandList = (outs);
1150 let InOperandList = (ins);
1151 let AsmString = "# XRay Function Enter.";
1152 let usesCustomInserter = 1;
1153 let hasSideEffects = 0;
1155 def PATCHABLE_RET : StandardPseudoInstruction {
1156 let OutOperandList = (outs);
1157 let InOperandList = (ins variable_ops);
1158 let AsmString = "# XRay Function Patchable RET.";
1159 let usesCustomInserter = 1;
1160 let hasSideEffects = 1;
1161 let isTerminator = 1;
1164 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
1165 let OutOperandList = (outs);
1166 let InOperandList = (ins);
1167 let AsmString = "# XRay Function Exit.";
1168 let usesCustomInserter = 1;
1169 let hasSideEffects = 0; // FIXME: is this correct?
1170 let isReturn = 0; // Original return instruction will follow
1172 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
1173 let OutOperandList = (outs);
1174 let InOperandList = (ins variable_ops);
1175 let AsmString = "# XRay Tail Call Exit.";
1176 let usesCustomInserter = 1;
1177 let hasSideEffects = 1;
1180 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
1181 let OutOperandList = (outs);
1182 let InOperandList = (ins ptr_rc:$event, i8imm:$size);
1183 let AsmString = "# XRay Custom Event Log.";
1184 let usesCustomInserter = 1;
1188 let hasSideEffects = 1;
1190 def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
1191 let OutOperandList = (outs);
1192 let InOperandList = (ins i16imm:$type, ptr_rc:$event, i32imm:$size);
1193 let AsmString = "# XRay Typed Event Log.";
1194 let usesCustomInserter = 1;
1198 let hasSideEffects = 1;
1200 def FENTRY_CALL : StandardPseudoInstruction {
1201 let OutOperandList = (outs);
1202 let InOperandList = (ins);
1203 let AsmString = "# FEntry call";
1204 let usesCustomInserter = 1;
1207 let hasSideEffects = 1;
1209 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
1210 let OutOperandList = (outs);
1211 let InOperandList = (ins variable_ops);
1213 let hasSideEffects = 1;
1216 // Generic opcodes used in GlobalISel.
1217 include "llvm/Target/GenericOpcodes.td"
1219 //===----------------------------------------------------------------------===//
1220 // AsmParser - This class can be implemented by targets that wish to implement
1223 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1224 // syntax on X86 for example).
1227 // AsmParserClassName - This specifies the suffix to use for the asmparser
1228 // class. Generated AsmParser classes are always prefixed with the target
1230 string AsmParserClassName = "AsmParser";
1232 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1233 // function of the AsmParser class to call on every matched instruction.
1234 // This can be used to perform target specific instruction post-processing.
1235 string AsmParserInstCleanup = "";
1237 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1238 // written register name matcher
1239 bit ShouldEmitMatchRegisterName = 1;
1241 // Set to true if the target needs a generated 'alternative register name'
1244 // This generates a function which can be used to lookup registers from
1245 // their aliases. This function will fail when called on targets where
1246 // several registers share the same alias (i.e. not a 1:1 mapping).
1247 bit ShouldEmitMatchRegisterAltName = 0;
1249 // Set to true if MatchRegisterName and MatchRegisterAltName functions
1250 // should be generated even if there are duplicate register names. The
1251 // target is responsible for coercing aliased registers as necessary
1252 // (e.g. in validateTargetOperandClass), and there are no guarantees about
1253 // which numeric register identifier will be returned in the case of
1254 // multiple matches.
1255 bit AllowDuplicateRegisterNames = 0;
1257 // HasMnemonicFirst - Set to false if target instructions don't always
1258 // start with a mnemonic as the first token.
1259 bit HasMnemonicFirst = 1;
1261 // ReportMultipleNearMisses -
1262 // When 0, the assembly matcher reports an error for one encoding or operand
1263 // that did not match the parsed instruction.
1264 // When 1, the assmebly matcher returns a list of encodings that were close
1265 // to matching the parsed instruction, so to allow more detailed error
1267 bit ReportMultipleNearMisses = 0;
1269 def DefaultAsmParser : AsmParser;
1271 //===----------------------------------------------------------------------===//
1272 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1273 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1274 // implemented by targets to describe such variants.
1276 class AsmParserVariant {
1277 // Variant - AsmParsers can be of multiple different variants. Variants are
1278 // used to support targets that need to parser multiple formats for the
1279 // assembly language.
1282 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1285 // CommentDelimiter - If given, the delimiter string used to recognize
1286 // comments which are hard coded in the .td assembler strings for individual
1288 string CommentDelimiter = "";
1290 // RegisterPrefix - If given, the token prefix which indicates a register
1291 // token. This is used by the matcher to automatically recognize hard coded
1292 // register tokens as constrained registers, instead of tokens, for the
1293 // purposes of matching.
1294 string RegisterPrefix = "";
1296 // TokenizingCharacters - Characters that are standalone tokens
1297 string TokenizingCharacters = "[]*!";
1299 // SeparatorCharacters - Characters that are not tokens
1300 string SeparatorCharacters = " \t,";
1302 // BreakCharacters - Characters that start new identifiers
1303 string BreakCharacters = "";
1305 def DefaultAsmParserVariant : AsmParserVariant;
1307 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1308 /// matches instructions and aliases.
1309 class AssemblerPredicate<string cond, string name = ""> {
1310 bit AssemblerMatcherPredicate = 1;
1311 string AssemblerCondString = cond;
1312 string PredicateName = name;
1315 /// TokenAlias - This class allows targets to define assembler token
1316 /// operand aliases. That is, a token literal operand which is equivalent
1317 /// to another, canonical, token literal. For example, ARM allows:
1318 /// vmov.u32 s4, #0 -> vmov.i32, #0
1319 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1320 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1321 /// def : TokenAlias<".u32", ".i32">;
1323 /// This works by marking the match class of 'From' as a subclass of the
1324 /// match class of 'To'.
1325 class TokenAlias<string From, string To> {
1326 string FromToken = From;
1327 string ToToken = To;
1330 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1331 /// aliases. This should be used when all forms of one mnemonic are accepted
1332 /// with a different mnemonic. For example, X86 allows:
1333 /// sal %al, 1 -> shl %al, 1
1334 /// sal %ax, %cl -> shl %ax, %cl
1335 /// sal %eax, %cl -> shl %eax, %cl
1336 /// etc. Though "sal" is accepted with many forms, all of them are directly
1337 /// translated to a shl, so it can be handled with (in the case of X86, it
1338 /// actually has one for each suffix as well):
1339 /// def : MnemonicAlias<"sal", "shl">;
1341 /// Mnemonic aliases are mapped before any other translation in the match phase,
1342 /// and do allow Requires predicates, e.g.:
1344 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1345 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1347 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1349 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1351 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1352 /// applied unconditionally.
1353 class MnemonicAlias<string From, string To, string VariantName = ""> {
1354 string FromMnemonic = From;
1355 string ToMnemonic = To;
1356 string AsmVariantName = VariantName;
1358 // Predicates - Predicates that must be true for this remapping to happen.
1359 list<Predicate> Predicates = [];
1362 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1363 /// match an instruction that has a different (more canonical) assembly
1365 class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
1366 string AsmString = Asm; // The .s format to match the instruction with.
1367 dag ResultInst = Result; // The MCInst to generate.
1369 // This determines which order the InstPrinter detects aliases for
1370 // printing. A larger value makes the alias more likely to be
1371 // emitted. The Instruction's own definition is notionally 0.5, so 0
1372 // disables printing and 1 enables it if there are no conflicting aliases.
1373 int EmitPriority = Emit;
1375 // Predicates - Predicates that must be true for this to match.
1376 list<Predicate> Predicates = [];
1378 // If the instruction specified in Result has defined an AsmMatchConverter
1379 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1380 // function when converting the OperandVector into an MCInst instead of the
1381 // function that is generated by the dag Result.
1382 // Setting this to 0 will cause the alias to ignore the Result instruction's
1383 // defined AsmMatchConverter and instead use the function generated by the
1385 bit UseInstAsmMatchConverter = 1;
1387 // Assembler variant name to use for this alias. If not specified then
1388 // assembler variants will be determined based on AsmString
1389 string AsmVariantName = VariantName;
1392 //===----------------------------------------------------------------------===//
1393 // AsmWriter - This class can be implemented by targets that need to customize
1394 // the format of the .s file writer.
1396 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1397 // on X86 for example).
1400 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1401 // class. Generated AsmWriter classes are always prefixed with the target
1403 string AsmWriterClassName = "InstPrinter";
1405 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1406 // the various print methods.
1407 // FIXME: Remove after all ports are updated.
1408 int PassSubtarget = 0;
1410 // Variant - AsmWriters can be of multiple different variants. Variants are
1411 // used to support targets that need to emit assembly code in ways that are
1412 // mostly the same for different targets, but have minor differences in
1413 // syntax. If the asmstring contains {|} characters in them, this integer
1414 // will specify which alternative to use. For example "{x|y|z}" with Variant
1415 // == 1, will expand to "y".
1418 def DefaultAsmWriter : AsmWriter;
1421 //===----------------------------------------------------------------------===//
1422 // Target - This class contains the "global" target information
1425 // InstructionSet - Instruction set description for this target.
1426 InstrInfo InstructionSet;
1428 // AssemblyParsers - The AsmParser instances available for this target.
1429 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1431 /// AssemblyParserVariants - The AsmParserVariant instances available for
1433 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1435 // AssemblyWriters - The AsmWriter instances available for this target.
1436 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1438 // AllowRegisterRenaming - Controls whether this target allows
1439 // post-register-allocation renaming of registers. This is done by
1440 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
1441 // for all opcodes if this flag is set to 0.
1442 int AllowRegisterRenaming = 0;
1445 //===----------------------------------------------------------------------===//
1446 // SubtargetFeature - A characteristic of the chip set.
1448 class SubtargetFeature<string n, string a, string v, string d,
1449 list<SubtargetFeature> i = []> {
1450 // Name - Feature name. Used by command line (-mattr=) to determine the
1451 // appropriate target chip.
1455 // Attribute - Attribute to be set by feature.
1457 string Attribute = a;
1459 // Value - Value the attribute to be set to by feature.
1463 // Desc - Feature description. Used by command line (-mattr=) to display help
1468 // Implies - Features that this feature implies are present. If one of those
1469 // features isn't set, then this one shouldn't be set either.
1471 list<SubtargetFeature> Implies = i;
1474 /// Specifies a Subtarget feature that this instruction is deprecated on.
1475 class Deprecated<SubtargetFeature dep> {
1476 SubtargetFeature DeprecatedFeatureMask = dep;
1479 /// A custom predicate used to determine if an instruction is
1480 /// deprecated or not.
1481 class ComplexDeprecationPredicate<string dep> {
1482 string ComplexDeprecationPredicate = dep;
1485 //===----------------------------------------------------------------------===//
1486 // Processor chip sets - These values represent each of the chip sets supported
1487 // by the scheduler. Each Processor definition requires corresponding
1488 // instruction itineraries.
1490 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1491 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1492 // appropriate target chip.
1496 // SchedModel - The machine model for scheduling and instruction cost.
1498 SchedMachineModel SchedModel = NoSchedModel;
1500 // ProcItin - The scheduling information for the target processor.
1502 ProcessorItineraries ProcItin = pi;
1504 // Features - list of
1505 list<SubtargetFeature> Features = f;
1508 // ProcessorModel allows subtargets to specify the more general
1509 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1510 // gradually move to this newer form.
1512 // Although this class always passes NoItineraries to the Processor
1513 // class, the SchedMachineModel may still define valid Itineraries.
1514 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1515 : Processor<n, NoItineraries, f> {
1519 //===----------------------------------------------------------------------===//
1520 // InstrMapping - This class is used to create mapping tables to relate
1521 // instructions with each other based on the values specified in RowFields,
1522 // ColFields, KeyCol and ValueCols.
1524 class InstrMapping {
1525 // FilterClass - Used to limit search space only to the instructions that
1526 // define the relationship modeled by this InstrMapping record.
1529 // RowFields - List of fields/attributes that should be same for all the
1530 // instructions in a row of the relation table. Think of this as a set of
1531 // properties shared by all the instructions related by this relationship
1532 // model and is used to categorize instructions into subgroups. For instance,
1533 // if we want to define a relation that maps 'Add' instruction to its
1534 // predicated forms, we can define RowFields like this:
1536 // let RowFields = BaseOp
1537 // All add instruction predicated/non-predicated will have to set their BaseOp
1538 // to the same value.
1540 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1541 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1542 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1543 list<string> RowFields = [];
1545 // List of fields/attributes that are same for all the instructions
1546 // in a column of the relation table.
1547 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1548 // based on the 'predSense' values. All the instruction in a specific
1549 // column have the same value and it is fixed for the column according
1550 // to the values set in 'ValueCols'.
1551 list<string> ColFields = [];
1553 // Values for the fields/attributes listed in 'ColFields'.
1554 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1555 // that models this relation) should be non-predicated.
1556 // In the example above, 'Add' is the key instruction.
1557 list<string> KeyCol = [];
1559 // List of values for the fields/attributes listed in 'ColFields', one for
1560 // each column in the relation table.
1562 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1563 // table. First column requires all the instructions to have predSense
1564 // set to 'true' and second column requires it to be 'false'.
1565 list<list<string> > ValueCols = [];
1568 //===----------------------------------------------------------------------===//
1569 // Pull in the common support for calling conventions.
1571 include "llvm/Target/TargetCallingConv.td"
1573 //===----------------------------------------------------------------------===//
1574 // Pull in the common support for DAG isel generation.
1576 include "llvm/Target/TargetSelectionDAG.td"
1578 //===----------------------------------------------------------------------===//
1579 // Pull in the common support for Global ISel register bank info generation.
1581 include "llvm/Target/GlobalISel/RegisterBank.td"
1583 //===----------------------------------------------------------------------===//
1584 // Pull in the common support for DAG isel generation.
1586 include "llvm/Target/GlobalISel/Target.td"
1588 //===----------------------------------------------------------------------===//
1589 // Pull in the common support for the Global ISel DAG-based selector generation.
1591 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
1593 //===----------------------------------------------------------------------===//
1594 // Pull in the common support for Pfm Counters generation.
1596 include "llvm/Target/TargetPfmCounters.td"