1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces which should be
10 // implemented by each target which is using a TableGen based code generator.
12 //===----------------------------------------------------------------------===//
14 // Include all information about LLVM intrinsics.
15 include "llvm/IR/Intrinsics.td"
17 //===----------------------------------------------------------------------===//
18 // Register file description - These classes are used to fill in the target
19 // description classes.
21 class RegisterClass; // Forward def
23 class HwMode<string FS> {
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
26 // when "feat1" is enabled and "feat2" is disabled at the same time.
27 // Any other features are not checked.
28 // When multiple modes are used, they should be mutually exclusive,
29 // otherwise the results are unpredictable.
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
36 def DefaultMode : HwMode<"">;
38 // A class used to associate objects with HW modes. It is only intended to
39 // be used as a base class, where the derived class should contain a member
40 // "Objects", which is a list of the same length as the list of modes.
41 // The n-th element on the Objects list will be associated with the n-th
42 // element on the Modes list.
43 class HwModeSelect<list<HwMode> Ms> {
44 list<HwMode> Modes = Ms;
47 // A common class that implements a counterpart of ValueType, which is
48 // dependent on a HW mode. This class inherits from ValueType itself,
49 // which makes it possible to use objects of this class where ValueType
50 // objects could be used. This is specifically applicable to selection
52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
53 : HwModeSelect<Ms>, ValueType<0, 0> {
54 // The length of this list must be the same as the length of Ms.
55 list<ValueType> Objects = Ts;
58 // A class representing the register size, spill size and spill alignment
59 // in bits of a register.
60 class RegInfo<int RS, int SS, int SA> {
61 int RegSize = RS; // Register size in bits.
62 int SpillSize = SS; // Spill slot size in bits.
63 int SpillAlignment = SA; // Spill slot alignment in bits.
66 // The register size/alignment information, parameterized by a HW mode.
67 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
69 // The length of this list must be the same as the length of Ms.
70 list<RegInfo> Objects = Ts;
73 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
74 class SubRegIndex<int size, int offset = 0> {
75 string Namespace = "";
77 // Size - Size (in bits) of the sub-registers represented by this index.
80 // Offset - Offset of the first bit that is part of this sub-register index.
81 // Set it to -1 if the same index is used to represent sub-registers that can
82 // be at different offsets (for example when using an index to access an
83 // element in a register tuple).
86 // ComposedOf - A list of two SubRegIndex instances, [A, B].
87 // This indicates that this SubRegIndex is the result of composing A and B.
88 // See ComposedSubRegIndex.
89 list<SubRegIndex> ComposedOf = [];
91 // CoveringSubRegIndices - A list of two or more sub-register indexes that
92 // cover this sub-register.
94 // This field should normally be left blank as TableGen can infer it.
96 // TableGen automatically detects sub-registers that straddle the registers
97 // in the SubRegs field of a Register definition. For example:
99 // Q0 = dsub_0 -> D0, dsub_1 -> D1
100 // Q1 = dsub_0 -> D2, dsub_1 -> D3
101 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
102 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
104 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
105 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
106 // CoveringSubRegIndices = [dsub_1, dsub_2].
107 list<SubRegIndex> CoveringSubRegIndices = [];
110 // ComposedSubRegIndex - A sub-register that is the result of composing A and B.
111 // Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
112 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
113 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
114 !if(!eq(B.Offset, -1), -1,
115 !add(A.Offset, B.Offset)))> {
117 let ComposedOf = [A, B];
120 // RegAltNameIndex - The alternate name set to use for register operands of
121 // this register class when printing.
122 class RegAltNameIndex {
123 string Namespace = "";
125 // A set to be used if the name for a register is not defined in this set.
126 // This allows creating name sets with only a few alternative names.
127 RegAltNameIndex FallbackRegAltNameIndex = ?;
129 def NoRegAltName : RegAltNameIndex;
131 // Register - You should define one instance of this class for each register
132 // in the target machine. String n will become the "name" of the register.
133 class Register<string n, list<string> altNames = []> {
134 string Namespace = "";
136 list<string> AltNames = altNames;
138 // Aliases - A list of registers that this register overlaps with. A read or
139 // modification of this register can potentially read or modify the aliased
141 list<Register> Aliases = [];
143 // SubRegs - A list of registers that are parts of this register. Note these
144 // are "immediate" sub-registers and the registers within the list do not
145 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
147 list<Register> SubRegs = [];
149 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
150 // to address it. Sub-sub-register indices are automatically inherited from
152 list<SubRegIndex> SubRegIndices = [];
154 // RegAltNameIndices - The alternate name indices which are valid for this
156 list<RegAltNameIndex> RegAltNameIndices = [];
158 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
159 // These values can be determined by locating the <target>.h file in the
160 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
161 // order of these names correspond to the enumeration used by gcc. A value of
162 // -1 indicates that the gcc number is undefined and -2 that register number
163 // is invalid for this mode/flavour.
164 list<int> DwarfNumbers = [];
166 // CostPerUse - Additional cost of instructions using this register compared
167 // to other registers in its class. The register allocator will try to
168 // minimize the number of instructions using a register with a CostPerUse.
169 // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where
170 // some registers require larger instruction encodings, by the RISC-V target,
171 // where some registers preclude using some C instructions.
174 // CoveredBySubRegs - When this bit is set, the value of this register is
175 // completely determined by the value of its sub-registers. For example, the
176 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
177 // covered by its sub-register AX.
178 bit CoveredBySubRegs = 0;
180 // HWEncoding - The target specific hardware encoding for this register.
181 bits<16> HWEncoding = 0;
183 bit isArtificial = 0;
186 // RegisterWithSubRegs - This can be used to define instances of Register which
187 // need to specify sub-registers.
188 // List "subregs" specifies which registers are sub-registers to this one. This
189 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
190 // This allows the code generator to be careful not to put two values with
191 // overlapping live ranges into registers which alias.
192 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
193 let SubRegs = subregs;
196 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
197 // of Operand's that are legal as type qualifiers in DAG patterns. This should
198 // only ever be used for defining multiclasses that are polymorphic over both
199 // RegisterClass's and other Operand's.
201 string OperandNamespace = "MCOI";
202 string DecoderMethod = "";
205 // RegisterClass - Now that all of the registers are defined, and aliases
206 // between registers are defined, specify which registers belong to which
207 // register classes. This also defines the default allocation order of
208 // registers by register allocators.
210 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
211 dag regList, RegAltNameIndex idx = NoRegAltName>
213 string Namespace = namespace;
215 // The register size/alignment information, parameterized by a HW mode.
216 RegInfoByHwMode RegInfos;
218 // RegType - Specify the list ValueType of the registers in this register
219 // class. Note that all registers in a register class must have the same
220 // ValueTypes. This is a list because some targets permit storing different
221 // types in same register, for example vector values with 128-bit total size,
222 // but different count/size of items, like SSE on x86.
224 list<ValueType> RegTypes = regTypes;
226 // Size - Specify the spill size in bits of the registers. A default value of
227 // zero lets tablegen pick an appropriate size.
230 // Alignment - Specify the alignment required of the registers when they are
231 // stored or loaded to memory.
233 int Alignment = alignment;
235 // CopyCost - This value is used to specify the cost of copying a value
236 // between two registers in this register class. The default value is one
237 // meaning it takes a single instruction to perform the copying. A negative
238 // value means copying is extremely expensive or impossible.
241 // MemberList - Specify which registers are in this class. If the
242 // allocation_order_* method are not specified, this also defines the order of
243 // allocation used by the register allocator.
245 dag MemberList = regList;
247 // AltNameIndex - The alternate register name to use when printing operands
248 // of this register class. Every register in the register class must have
249 // a valid alternate name for the given index.
250 RegAltNameIndex altNameIndex = idx;
252 // isAllocatable - Specify that the register class can be used for virtual
253 // registers and register allocation. Some register classes are only used to
254 // model instruction operand constraints, and should have isAllocatable = 0.
255 bit isAllocatable = 1;
257 // AltOrders - List of alternative allocation orders. The default order is
258 // MemberList itself, and that is good enough for most targets since the
259 // register allocators automatically remove reserved registers and move
260 // callee-saved registers to the end.
261 list<dag> AltOrders = [];
263 // AltOrderSelect - The body of a function that selects the allocation order
264 // to use in a given machine function. The code will be inserted in a
265 // function like this:
267 // static inline unsigned f(const MachineFunction &MF) { ... }
269 // The function should return 0 to select the default order defined by
270 // MemberList, 1 to select the first AltOrders entry and so on.
271 code AltOrderSelect = [{}];
273 // Specify allocation priority for register allocators using a greedy
274 // heuristic. Classes with higher priority values are assigned first. This is
275 // useful as it is sometimes beneficial to assign registers to highly
276 // constrained classes first. The value has to be in the range [0,63].
277 int AllocationPriority = 0;
279 // Generate register pressure set for this register class and any class
280 // synthesized from it. Set to 0 to inhibit unneeded pressure sets.
281 bit GeneratePressureSet = 1;
283 // Weight override for register pressure calculation. This is the value
284 // TargetRegisterClass::getRegClassWeight() will return. The weight is in
285 // units of pressure for this register class. If unset tablegen will
286 // calculate a weight based on a number of register units in this register
287 // class registers. The weight is per register.
290 // The diagnostic type to present when referencing this operand in a match
291 // failure error message. If this is empty, the default Match_InvalidOperand
292 // diagnostic type will be used. If this is "<name>", a Match_<name> enum
293 // value will be generated and used for this operand type. The target
294 // assembly parser is responsible for converting this into a user-facing
295 // diagnostic message.
296 string DiagnosticType = "";
298 // A diagnostic message to emit when an invalid value is provided for this
299 // register class when it is being used an an assembly operand. If this is
300 // non-empty, an anonymous diagnostic type enum value will be generated, and
301 // the assembly matcher will provide a function to map from diagnostic types
302 // to message strings.
303 string DiagnosticString = "";
306 // The memberList in a RegisterClass is a dag of set operations. TableGen
307 // evaluates these set operations and expand them into register lists. These
308 // are the most common operation, see test/TableGen/SetTheory.td for more
309 // examples of what is possible:
311 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
312 // register class, or a sub-expression. This is also the way to simply list
315 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
317 // (and GPR, CSR) - Set intersection. All registers from the first set that are
318 // also in the second set.
320 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
321 // numbered registers. Takes an optional 4th operand which is a stride to use
322 // when generating the sequence.
324 // (shl GPR, 4) - Remove the first N elements.
326 // (trunc GPR, 4) - Truncate after the first N elements.
328 // (rotl GPR, 1) - Rotate N places to the left.
330 // (rotr GPR, 1) - Rotate N places to the right.
332 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
334 // (interleave A, B, ...) - Interleave the elements from each argument list.
336 // All of these operators work on ordered sets, not lists. That means
337 // duplicates are removed from sub-expressions.
339 // Set operators. The rest is defined in TargetSelectionDAG.td.
344 // RegisterTuples - Automatically generate super-registers by forming tuples of
345 // sub-registers. This is useful for modeling register sequence constraints
346 // with pseudo-registers that are larger than the architectural registers.
348 // The sub-register lists are zipped together:
350 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
352 // Generates the same registers as:
354 // let SubRegIndices = [sube, subo] in {
355 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
356 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
359 // The generated pseudo-registers inherit super-classes and fields from their
360 // first sub-register. Most fields from the Register class are inferred, and
361 // the AsmName and Dwarf numbers are cleared.
363 // RegisterTuples instances can be used in other set operations to form
364 // register classes and so on. This is the only way of using the generated
367 // RegNames may be specified to supply asm names for the generated tuples.
368 // If used must have the same size as the list of produced registers.
369 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs,
370 list<string> RegNames = []> {
371 // SubRegs - N lists of registers to be zipped up. Super-registers are
372 // synthesized from the first element of each SubRegs list, the second
373 // element and so on.
374 list<dag> SubRegs = Regs;
376 // SubRegIndices - N SubRegIndex instances. This provides the names of the
377 // sub-registers in the synthesized super-registers.
378 list<SubRegIndex> SubRegIndices = Indices;
380 // List of asm names for the generated tuple registers.
381 list<string> RegAsmNames = RegNames;
385 //===----------------------------------------------------------------------===//
386 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
387 // to the register numbering used by gcc and gdb. These values are used by a
388 // debug information writer to describe where values may be located during
390 class DwarfRegNum<list<int> Numbers> {
391 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
392 // These values can be determined by locating the <target>.h file in the
393 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
394 // order of these names correspond to the enumeration used by gcc. A value of
395 // -1 indicates that the gcc number is undefined and -2 that register number
396 // is invalid for this mode/flavour.
397 list<int> DwarfNumbers = Numbers;
400 // DwarfRegAlias - This class declares that a given register uses the same dwarf
401 // numbers as another one. This is useful for making it clear that the two
402 // registers do have the same number. It also lets us build a mapping
403 // from dwarf register number to llvm register.
404 class DwarfRegAlias<Register reg> {
405 Register DwarfAlias = reg;
408 //===----------------------------------------------------------------------===//
409 // Pull in the common support for MCPredicate (portable scheduling predicates).
411 include "llvm/Target/TargetInstrPredicate.td"
413 //===----------------------------------------------------------------------===//
414 // Pull in the common support for scheduling
416 include "llvm/Target/TargetSchedule.td"
418 class Predicate; // Forward def
420 class InstructionEncoding {
421 // Size of encoded instruction.
424 // The "namespace" in which this instruction exists, on targets like ARM
425 // which multiple ISA namespaces exist.
426 string DecoderNamespace = "";
428 // List of predicates which will be turned into isel matching code.
429 list<Predicate> Predicates = [];
431 string DecoderMethod = "";
433 // Is the instruction decoder method able to completely determine if the
434 // given instruction is valid or not. If the TableGen definition of the
435 // instruction specifies bitpattern A??B where A and B are static bits, the
436 // hasCompleteDecoder flag says whether the decoder method fully handles the
437 // ?? space, i.e. if it is a final arbiter for the instruction validity.
438 // If not then the decoder attempts to continue decoding when the decoder
441 // This allows to handle situations where the encoding is not fully
442 // orthogonal. Example:
443 // * InstA with bitpattern 0b0000????,
444 // * InstB with bitpattern 0b000000?? but the associated decoder method
445 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
447 // The decoder tries to decode a bitpattern that matches both InstA and
448 // InstB bitpatterns first as InstB (because it is the most specific
449 // encoding). In the default case (hasCompleteDecoder = 1), when
450 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
451 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
452 // DecodeInstB() is not able to determine if all possible values of ?? are
453 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
454 // decode the bitpattern as InstA too.
455 bit hasCompleteDecoder = 1;
458 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
459 // an EncodingByHwMode, its Inst and Size members are ignored and Ts are used
460 // to encode and decode based on HwMode.
461 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
463 // The length of this list must be the same as the length of Ms.
464 list<InstructionEncoding> Objects = Ts;
467 //===----------------------------------------------------------------------===//
468 // Instruction set description - These classes correspond to the C++ classes in
469 // the Target/TargetInstrInfo.h file.
471 class Instruction : InstructionEncoding {
472 string Namespace = "";
474 dag OutOperandList; // An dag containing the MI def operand list.
475 dag InOperandList; // An dag containing the MI use operand list.
476 string AsmString = ""; // The .s format to print the instruction with.
478 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
479 // the Inst member of this Instruction is ignored.
480 EncodingByHwMode EncodingInfos;
482 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
483 // otherwise, uninitialized.
486 // The follow state will eventually be inferred automatically from the
487 // instruction pattern.
489 list<Register> Uses = []; // Default to using no non-operand registers
490 list<Register> Defs = []; // Default to modifying no non-operand registers
492 // Predicates - List of predicates which will be turned into isel matching
494 list<Predicate> Predicates = [];
496 // Size - Size of encoded instruction, or zero if the size cannot be determined
500 // Code size, for instruction selection.
501 // FIXME: What does this actually mean?
504 // Added complexity passed onto matching pattern.
505 int AddedComplexity = 0;
507 // Indicates if this is a pre-isel opcode that should be
508 // legalized/regbankselected/selected.
509 bit isPreISelOpcode = 0;
511 // These bits capture information about the high-level semantics of the
513 bit isReturn = 0; // Is this instruction a return instruction?
514 bit isBranch = 0; // Is this instruction a branch instruction?
515 bit isEHScopeReturn = 0; // Does this instruction end an EH scope?
516 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
517 bit isCompare = 0; // Is this instruction a comparison instruction?
518 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
519 bit isMoveReg = 0; // Is this instruction a move register instruction?
520 bit isBitcast = 0; // Is this instruction a bitcast instruction?
521 bit isSelect = 0; // Is this instruction a select instruction?
522 bit isBarrier = 0; // Can control flow fall through this instruction?
523 bit isCall = 0; // Is this instruction a call instruction?
524 bit isAdd = 0; // Is this instruction an add instruction?
525 bit isTrap = 0; // Is this instruction a trap instruction?
526 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
527 bit mayLoad = ?; // Is it possible for this inst to read memory?
528 bit mayStore = ?; // Is it possible for this inst to write memory?
529 bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
530 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
531 bit isCommutable = 0; // Is this 3 operand instruction commutable?
532 bit isTerminator = 0; // Is this part of the terminator for a basic block?
533 bit isReMaterializable = 0; // Is this instruction re-materializable?
534 bit isPredicable = 0; // 1 means this instruction is predicable
535 // even if it does not have any operand
536 // tablegen can identify as a predicate
537 bit isUnpredicable = 0; // 1 means this instruction is not predicable
538 // even if it _does_ have a predicate operand
539 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
540 bit usesCustomInserter = 0; // Pseudo instr needing special help.
541 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
542 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
543 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
544 bit isConvergent = 0; // Is this instruction convergent?
545 bit isAuthenticated = 0; // Does this instruction authenticate a pointer?
546 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
547 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
548 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
549 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
550 // If so, make sure to override
551 // TargetInstrInfo::getRegSequenceLikeInputs.
552 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
553 // If so, won't have encoding information for
554 // the [MC]CodeEmitter stuff.
555 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
556 // If so, make sure to override
557 // TargetInstrInfo::getExtractSubregLikeInputs.
558 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
559 // If so, make sure to override
560 // TargetInstrInfo::getInsertSubregLikeInputs.
561 bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
563 // Does the instruction have side effects that are not captured by any
564 // operands of the instruction or other flags?
565 bit hasSideEffects = ?;
567 // Is this instruction a "real" instruction (with a distinct machine
568 // encoding), or is it a pseudo instruction used for codegen modeling
570 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
571 // instructions can (and often do) still have encoding information
572 // associated with them. Once we've migrated all of them over to true
573 // pseudo-instructions that are lowered to real instructions prior to
574 // the printer/emitter, we can remove this attribute and just use isPseudo.
576 // The intended use is:
577 // isPseudo: Does not have encoding information and should be expanded,
578 // at the latest, during lowering to MCInst.
580 // isCodeGenOnly: Does have encoding information and can go through to the
581 // CodeEmitter unchanged, but duplicates a canonical instruction
582 // definition's encoding and should be ignored when constructing the
583 // assembler match tables.
584 bit isCodeGenOnly = 0;
586 // Is this instruction a pseudo instruction for use by the assembler parser.
587 bit isAsmParserOnly = 0;
589 // This instruction is not expected to be queried for scheduling latencies
590 // and therefore needs no scheduling information even for a complete
592 bit hasNoSchedulingInfo = 0;
594 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
596 // Scheduling information from TargetSchedule.td.
597 list<SchedReadWrite> SchedRW;
599 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
601 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
602 /// be encoded into the output machineinstr.
603 string DisableEncoding = "";
605 string PostEncoderMethod = "";
607 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
608 bits<64> TSFlags = 0;
610 ///@name Assembler Parser Support
613 string AsmMatchConverter = "";
615 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
616 /// two-operand matcher inst-alias for a three operand instruction.
617 /// For example, the arm instruction "add r3, r3, r5" can be written
618 /// as "add r3, r5". The constraint is of the same form as a tied-operand
619 /// constraint. For example, "$Rn = $Rd".
620 string TwoOperandAliasConstraint = "";
622 /// Assembler variant name to use for this instruction. If specified then
623 /// instruction will be presented only in MatchTable for this variant. If
624 /// not specified then assembler variants will be determined based on
626 string AsmVariantName = "";
630 /// UseNamedOperandTable - If set, the operand indices of this instruction
631 /// can be queried via the getNamedOperandIdx() function which is generated
633 bit UseNamedOperandTable = 0;
635 /// Should FastISel ignore this instruction. For certain ISAs, they have
636 /// instructions which map to the same ISD Opcode, value type operands and
637 /// instruction selection predicates. FastISel cannot handle such cases, but
638 /// SelectionDAG can.
639 bit FastISelShouldIgnore = 0;
642 /// Defines an additional encoding that disassembles to the given instruction
643 /// Like Instruction, the Inst and SoftFail fields are omitted to allow targets
644 // to specify their size.
645 class AdditionalEncoding<Instruction I> : InstructionEncoding {
646 Instruction AliasOf = I;
649 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
650 /// Which instruction it expands to and how the operands map from the
652 class PseudoInstExpansion<dag Result> {
653 dag ResultInst = Result; // The instruction to generate.
657 /// Predicates - These are extra conditionals which are turned into instruction
658 /// selector matching code. Currently each predicate is just a string.
659 class Predicate<string cond> {
660 string CondString = cond;
662 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
663 /// matcher, this is true. Targets should set this by inheriting their
664 /// feature from the AssemblerPredicate class in addition to Predicate.
665 bit AssemblerMatcherPredicate = 0;
667 /// AssemblerCondDag - Set of subtarget features being tested used
668 /// as alternative condition string used for assembler matcher. Must be used
669 /// with (all_of) to indicate that all features must be present, or (any_of)
670 /// to indicate that at least one must be. The required lack of presence of
671 /// a feature can be tested using a (not) node including the feature.
672 /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0".
673 /// "(all_of (not ModeThumb))" is translated to
674 /// "(Bits & ModeThumb) == 0".
675 /// "(all_of ModeThumb, FeatureThumb2)" is translated to
676 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
677 /// "(any_of ModeTumb, FeatureThumb2)" is translated to
678 /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0".
679 /// all_of and any_of cannot be combined in a single dag, instead multiple
680 /// predicates can be placed onto Instruction definitions.
681 dag AssemblerCondDag;
683 /// PredicateName - User-level name to use for the predicate. Mainly for use
684 /// in diagnostics such as missing feature errors in the asm matcher.
685 string PredicateName = "";
687 /// Setting this to '1' indicates that the predicate must be recomputed on
688 /// every function change. Most predicates can leave this at '0'.
690 /// Ignored by SelectionDAG, it always recomputes the predicate on every use.
691 bit RecomputePerFunction = 0;
694 /// NoHonorSignDependentRounding - This predicate is true if support for
695 /// sign-dependent-rounding is not enabled.
696 def NoHonorSignDependentRounding
697 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
699 class Requires<list<Predicate> preds> {
700 list<Predicate> Predicates = preds;
703 /// ops definition - This is just a simple marker used to identify the operand
704 /// list for an instruction. outs and ins are identical both syntactically and
705 /// semantically; they are used to define def operands and use operands to
706 /// improve readability. This should be used like this:
707 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
712 /// variable_ops definition - Mark this instruction as taking a variable number
717 /// PointerLikeRegClass - Values that are designed to have pointer width are
718 /// derived from this. TableGen treats the register class as having a symbolic
719 /// type that it doesn't know, and resolves the actual regclass to use by using
720 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
721 class PointerLikeRegClass<int Kind> {
722 int RegClassKind = Kind;
726 /// ptr_rc definition - Mark this operand as being a pointer value whose
727 /// register class is resolved dynamically via a callback to TargetInstrInfo.
728 /// FIXME: We should probably change this to a class which contain a list of
729 /// flags. But currently we have but one flag.
730 def ptr_rc : PointerLikeRegClass<0>;
732 /// unknown definition - Mark this operand as being of unknown type, causing
733 /// it to be resolved by inference in the context it is used.
735 def unknown : unknown_class;
737 /// AsmOperandClass - Representation for the kinds of operands which the target
738 /// specific parser can create and the assembly matcher may need to distinguish.
740 /// Operand classes are used to define the order in which instructions are
741 /// matched, to ensure that the instruction which gets matched for any
742 /// particular list of operands is deterministic.
744 /// The target specific parser must be able to classify a parsed operand into a
745 /// unique class which does not partially overlap with any other classes. It can
746 /// match a subset of some other class, in which case the super class field
747 /// should be defined.
748 class AsmOperandClass {
749 /// The name to use for this class, which should be usable as an enum value.
752 /// The super classes of this operand.
753 list<AsmOperandClass> SuperClasses = [];
755 /// The name of the method on the target specific operand to call to test
756 /// whether the operand is an instance of this class. If not set, this will
757 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
758 /// signature should be:
759 /// bool isFoo() const;
760 string PredicateMethod = ?;
762 /// The name of the method on the target specific operand to call to add the
763 /// target specific operand to an MCInst. If not set, this will default to
764 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
765 /// signature should be:
766 /// void addFooOperands(MCInst &Inst, unsigned N) const;
767 string RenderMethod = ?;
769 /// The name of the method on the target specific operand to call to custom
770 /// handle the operand parsing. This is useful when the operands do not relate
771 /// to immediates or registers and are very instruction specific (as flags to
772 /// set in a processor register, coprocessor number, ...).
773 string ParserMethod = ?;
775 // The diagnostic type to present when referencing this operand in a
776 // match failure error message. By default, use a generic "invalid operand"
777 // diagnostic. The target AsmParser maps these codes to text.
778 string DiagnosticType = "";
780 /// A diagnostic message to emit when an invalid value is provided for this
782 string DiagnosticString = "";
784 /// Set to 1 if this operand is optional and not always required. Typically,
785 /// the AsmParser will emit an error when it finishes parsing an
786 /// instruction if it hasn't matched all the operands yet. However, this
787 /// error will be suppressed if all of the remaining unmatched operands are
788 /// marked as IsOptional.
790 /// Optional arguments must be at the end of the operand list.
793 /// The name of the method on the target specific asm parser that returns the
794 /// default operand for this optional operand. This method is only used if
795 /// IsOptional == 1. If not set, this will default to "defaultFooOperands",
796 /// where Foo is the AsmOperandClass name. The method signature should be:
797 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const;
798 string DefaultMethod = ?;
801 def ImmAsmOperand : AsmOperandClass {
805 /// Operand Types - These provide the built-in operand types that may be used
806 /// by a target. Targets can optionally provide their own operand types as
807 /// needed, though this should not be needed for RISC targets.
808 class Operand<ValueType ty> : DAGOperand {
810 string PrintMethod = "printOperand";
811 string EncoderMethod = "";
812 bit hasCompleteDecoder = 1;
813 string OperandType = "OPERAND_UNKNOWN";
814 dag MIOperandInfo = (ops);
816 // MCOperandPredicate - Optionally, a code fragment operating on
817 // const MCOperand &MCOp, and returning a bool, to indicate if
818 // the value of MCOp is valid for the specific subclass of Operand
819 code MCOperandPredicate;
821 // ParserMatchClass - The "match class" that operands of this type fit
822 // in. Match classes are used to define the order in which instructions are
823 // match, to ensure that which instructions gets matched is deterministic.
825 // The target specific parser must be able to classify an parsed operand into
826 // a unique class, which does not partially overlap with any other classes. It
827 // can match a subset of some other class, in which case the AsmOperandClass
828 // should declare the other operand as one of its super classes.
829 AsmOperandClass ParserMatchClass = ImmAsmOperand;
832 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
834 // RegClass - The register class of the operand.
835 RegisterClass RegClass = regclass;
836 // PrintMethod - The target method to call to print register operands of
837 // this type. The method normally will just use an alt-name index to look
838 // up the name to print. Default to the generic printOperand().
839 string PrintMethod = pm;
841 // EncoderMethod - The target method name to call to encode this register
843 string EncoderMethod = "";
845 // ParserMatchClass - The "match class" that operands of this type fit
846 // in. Match classes are used to define the order in which instructions are
847 // match, to ensure that which instructions gets matched is deterministic.
849 // The target specific parser must be able to classify an parsed operand into
850 // a unique class, which does not partially overlap with any other classes. It
851 // can match a subset of some other class, in which case the AsmOperandClass
852 // should declare the other operand as one of its super classes.
853 AsmOperandClass ParserMatchClass;
855 string OperandType = "OPERAND_REGISTER";
857 // When referenced in the result of a CodeGen pattern, GlobalISel will
858 // normally copy the matched operand to the result. When this is set, it will
859 // emit a special copy that will replace zero-immediates with the specified
861 Register GIZeroRegister = ?;
864 let OperandType = "OPERAND_IMMEDIATE" in {
865 def i1imm : Operand<i1>;
866 def i8imm : Operand<i8>;
867 def i16imm : Operand<i16>;
868 def i32imm : Operand<i32>;
869 def i64imm : Operand<i64>;
871 def f32imm : Operand<f32>;
872 def f64imm : Operand<f64>;
875 // Register operands for generic instructions don't have an MVT, but do have
876 // constraints linking the operands (e.g. all operands of a G_ADD must
877 // have the same LLT).
878 class TypedOperand<string Ty> : Operand<untyped> {
879 let OperandType = Ty;
884 def type0 : TypedOperand<"OPERAND_GENERIC_0">;
885 def type1 : TypedOperand<"OPERAND_GENERIC_1">;
886 def type2 : TypedOperand<"OPERAND_GENERIC_2">;
887 def type3 : TypedOperand<"OPERAND_GENERIC_3">;
888 def type4 : TypedOperand<"OPERAND_GENERIC_4">;
889 def type5 : TypedOperand<"OPERAND_GENERIC_5">;
891 let IsPointer = 1 in {
892 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
893 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
894 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
895 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">;
896 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">;
897 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">;
900 // untyped_imm is for operands where isImm() will be true. It currently has no
901 // special behaviour and is only used for clarity.
902 def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> {
906 /// zero_reg definition - Special node to stand for the zero register.
910 /// undef_tied_input - Special node to indicate an input register tied
911 /// to an output which defaults to IMPLICIT_DEF.
912 def undef_tied_input;
914 /// All operands which the MC layer classifies as predicates should inherit from
915 /// this class in some manner. This is already handled for the most commonly
916 /// used PredicateOperand, but may be useful in other circumstances.
919 /// OperandWithDefaultOps - This Operand class can be used as the parent class
920 /// for an Operand that needs to be initialized with a default value if
921 /// no value is supplied in a pattern. This class can be used to simplify the
922 /// pattern definitions for instructions that have target specific flags
923 /// encoded as immediate operands.
924 class OperandWithDefaultOps<ValueType ty, dag defaultops>
926 dag DefaultOps = defaultops;
929 /// PredicateOperand - This can be used to define a predicate operand for an
930 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
931 /// AlwaysVal specifies the value of this predicate when set to "always
933 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
934 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
935 let MIOperandInfo = OpTypes;
938 /// OptionalDefOperand - This is used to define a optional definition operand
939 /// for an instruction. DefaultOps is the register the operand represents if
940 /// none is supplied, e.g. zero_reg.
941 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
942 : OperandWithDefaultOps<ty, defaultops> {
943 let MIOperandInfo = OpTypes;
947 // InstrInfo - This class should only be instantiated once to provide parameters
948 // which are global to the target machine.
951 // Target can specify its instructions in either big or little-endian formats.
952 // For instance, while both Sparc and PowerPC are big-endian platforms, the
953 // Sparc manual specifies its instructions in the format [31..0] (big), while
954 // PowerPC specifies them using the format [0..31] (little).
955 bit isLittleEndianEncoding = 0;
957 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
958 // by default, and TableGen will infer their value from the instruction
959 // pattern when possible.
961 // Normally, TableGen will issue an error it it can't infer the value of a
962 // property that hasn't been set explicitly. When guessInstructionProperties
963 // is set, it will guess a safe value instead.
965 // This option is a temporary migration help. It will go away.
966 bit guessInstructionProperties = 1;
968 // TableGen's instruction encoder generator has support for matching operands
969 // to bit-field variables both by name and by position. While matching by
970 // name is preferred, this is currently not possible for complex operands,
971 // and some targets still reply on the positional encoding rules. When
972 // generating a decoder for such targets, the positional encoding rules must
973 // be used by the decoder generator as well.
975 // This option is temporary; it will go away once the TableGen decoder
976 // generator has better support for complex operands and targets have
977 // migrated away from using positionally encoded operands.
978 bit decodePositionallyEncodedOperands = 0;
980 // When set, this indicates that there will be no overlap between those
981 // operands that are matched by ordering (positional operands) and those
984 // This option is temporary; it will go away once the TableGen decoder
985 // generator has better support for complex operands and targets have
986 // migrated away from using positionally encoded operands.
987 bit noNamedPositionallyEncodedOperands = 0;
990 // Standard Pseudo Instructions.
991 // This list must match TargetOpcodes.def.
992 // Only these instructions are allowed in the TargetOpcode namespace.
993 // Ensure mayLoad and mayStore have a default value, so as not to break
994 // targets that set guessInstructionProperties=0. Any local definition of
995 // mayLoad/mayStore takes precedence over these default values.
996 class StandardPseudoInstruction : Instruction {
999 let isCodeGenOnly = 1;
1001 let hasNoSchedulingInfo = 1;
1002 let Namespace = "TargetOpcode";
1004 def PHI : StandardPseudoInstruction {
1005 let OutOperandList = (outs unknown:$dst);
1006 let InOperandList = (ins variable_ops);
1007 let AsmString = "PHINODE";
1008 let hasSideEffects = 0;
1010 def INLINEASM : StandardPseudoInstruction {
1011 let OutOperandList = (outs);
1012 let InOperandList = (ins variable_ops);
1014 let hasSideEffects = 0; // Note side effect is encoded in an operand.
1016 def INLINEASM_BR : StandardPseudoInstruction {
1017 let OutOperandList = (outs);
1018 let InOperandList = (ins variable_ops);
1020 // Unlike INLINEASM, this is always treated as having side-effects.
1021 let hasSideEffects = 1;
1022 // Despite potentially branching, this instruction is intentionally _not_
1023 // marked as a terminator or a branch.
1025 def CFI_INSTRUCTION : StandardPseudoInstruction {
1026 let OutOperandList = (outs);
1027 let InOperandList = (ins i32imm:$id);
1030 let hasSideEffects = 0;
1031 let isNotDuplicable = 1;
1033 def EH_LABEL : StandardPseudoInstruction {
1034 let OutOperandList = (outs);
1035 let InOperandList = (ins i32imm:$id);
1038 let hasSideEffects = 0;
1039 let isNotDuplicable = 1;
1041 def GC_LABEL : StandardPseudoInstruction {
1042 let OutOperandList = (outs);
1043 let InOperandList = (ins i32imm:$id);
1046 let hasSideEffects = 0;
1047 let isNotDuplicable = 1;
1049 def ANNOTATION_LABEL : StandardPseudoInstruction {
1050 let OutOperandList = (outs);
1051 let InOperandList = (ins i32imm:$id);
1054 let hasSideEffects = 0;
1055 let isNotDuplicable = 1;
1057 def KILL : StandardPseudoInstruction {
1058 let OutOperandList = (outs);
1059 let InOperandList = (ins variable_ops);
1061 let hasSideEffects = 0;
1063 def EXTRACT_SUBREG : StandardPseudoInstruction {
1064 let OutOperandList = (outs unknown:$dst);
1065 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
1067 let hasSideEffects = 0;
1069 def INSERT_SUBREG : StandardPseudoInstruction {
1070 let OutOperandList = (outs unknown:$dst);
1071 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
1073 let hasSideEffects = 0;
1074 let Constraints = "$supersrc = $dst";
1076 def IMPLICIT_DEF : StandardPseudoInstruction {
1077 let OutOperandList = (outs unknown:$dst);
1078 let InOperandList = (ins);
1080 let hasSideEffects = 0;
1081 let isReMaterializable = 1;
1082 let isAsCheapAsAMove = 1;
1084 def SUBREG_TO_REG : StandardPseudoInstruction {
1085 let OutOperandList = (outs unknown:$dst);
1086 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
1088 let hasSideEffects = 0;
1090 def COPY_TO_REGCLASS : StandardPseudoInstruction {
1091 let OutOperandList = (outs unknown:$dst);
1092 let InOperandList = (ins unknown:$src, i32imm:$regclass);
1094 let hasSideEffects = 0;
1095 let isAsCheapAsAMove = 1;
1097 def DBG_VALUE : StandardPseudoInstruction {
1098 let OutOperandList = (outs);
1099 let InOperandList = (ins variable_ops);
1100 let AsmString = "DBG_VALUE";
1101 let hasSideEffects = 0;
1103 def DBG_LABEL : StandardPseudoInstruction {
1104 let OutOperandList = (outs);
1105 let InOperandList = (ins unknown:$label);
1106 let AsmString = "DBG_LABEL";
1107 let hasSideEffects = 0;
1109 def REG_SEQUENCE : StandardPseudoInstruction {
1110 let OutOperandList = (outs unknown:$dst);
1111 let InOperandList = (ins unknown:$supersrc, variable_ops);
1113 let hasSideEffects = 0;
1114 let isAsCheapAsAMove = 1;
1116 def COPY : StandardPseudoInstruction {
1117 let OutOperandList = (outs unknown:$dst);
1118 let InOperandList = (ins unknown:$src);
1120 let hasSideEffects = 0;
1121 let isAsCheapAsAMove = 1;
1122 let hasNoSchedulingInfo = 0;
1124 def BUNDLE : StandardPseudoInstruction {
1125 let OutOperandList = (outs);
1126 let InOperandList = (ins variable_ops);
1127 let AsmString = "BUNDLE";
1128 let hasSideEffects = 0;
1130 def LIFETIME_START : StandardPseudoInstruction {
1131 let OutOperandList = (outs);
1132 let InOperandList = (ins i32imm:$id);
1133 let AsmString = "LIFETIME_START";
1134 let hasSideEffects = 0;
1136 def LIFETIME_END : StandardPseudoInstruction {
1137 let OutOperandList = (outs);
1138 let InOperandList = (ins i32imm:$id);
1139 let AsmString = "LIFETIME_END";
1140 let hasSideEffects = 0;
1142 def STACKMAP : StandardPseudoInstruction {
1143 let OutOperandList = (outs);
1144 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
1145 let hasSideEffects = 1;
1148 let usesCustomInserter = 1;
1150 def PATCHPOINT : StandardPseudoInstruction {
1151 let OutOperandList = (outs unknown:$dst);
1152 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
1153 i32imm:$nargs, i32imm:$cc, variable_ops);
1154 let hasSideEffects = 1;
1157 let usesCustomInserter = 1;
1159 def STATEPOINT : StandardPseudoInstruction {
1160 let OutOperandList = (outs);
1161 let InOperandList = (ins variable_ops);
1162 let usesCustomInserter = 1;
1165 let hasSideEffects = 1;
1168 def LOAD_STACK_GUARD : StandardPseudoInstruction {
1169 let OutOperandList = (outs ptr_rc:$dst);
1170 let InOperandList = (ins);
1172 bit isReMaterializable = 1;
1173 let hasSideEffects = 0;
1176 def PREALLOCATED_SETUP : StandardPseudoInstruction {
1177 let OutOperandList = (outs);
1178 let InOperandList = (ins i32imm:$a);
1179 let usesCustomInserter = 1;
1180 let hasSideEffects = 1;
1182 def PREALLOCATED_ARG : StandardPseudoInstruction {
1183 let OutOperandList = (outs ptr_rc:$loc);
1184 let InOperandList = (ins i32imm:$a, i32imm:$b);
1185 let usesCustomInserter = 1;
1186 let hasSideEffects = 1;
1188 def LOCAL_ESCAPE : StandardPseudoInstruction {
1189 // This instruction is really just a label. It has to be part of the chain so
1190 // that it doesn't get dropped from the DAG, but it produces nothing and has
1192 let OutOperandList = (outs);
1193 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
1194 let hasSideEffects = 0;
1197 def FAULTING_OP : StandardPseudoInstruction {
1198 let OutOperandList = (outs unknown:$dst);
1199 let InOperandList = (ins variable_ops);
1200 let usesCustomInserter = 1;
1201 let hasSideEffects = 1;
1204 let isTerminator = 1;
1207 def PATCHABLE_OP : StandardPseudoInstruction {
1208 let OutOperandList = (outs);
1209 let InOperandList = (ins variable_ops);
1210 let usesCustomInserter = 1;
1213 let hasSideEffects = 1;
1215 def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
1216 let OutOperandList = (outs);
1217 let InOperandList = (ins);
1218 let AsmString = "# XRay Function Enter.";
1219 let usesCustomInserter = 1;
1220 let hasSideEffects = 1;
1222 def PATCHABLE_RET : StandardPseudoInstruction {
1223 let OutOperandList = (outs);
1224 let InOperandList = (ins variable_ops);
1225 let AsmString = "# XRay Function Patchable RET.";
1226 let usesCustomInserter = 1;
1227 let hasSideEffects = 1;
1228 let isTerminator = 1;
1231 def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
1232 let OutOperandList = (outs);
1233 let InOperandList = (ins);
1234 let AsmString = "# XRay Function Exit.";
1235 let usesCustomInserter = 1;
1236 let hasSideEffects = 1;
1237 let isReturn = 0; // Original return instruction will follow
1239 def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
1240 let OutOperandList = (outs);
1241 let InOperandList = (ins variable_ops);
1242 let AsmString = "# XRay Tail Call Exit.";
1243 let usesCustomInserter = 1;
1244 let hasSideEffects = 1;
1247 def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
1248 let OutOperandList = (outs);
1249 let InOperandList = (ins ptr_rc:$event, unknown:$size);
1250 let AsmString = "# XRay Custom Event Log.";
1251 let usesCustomInserter = 1;
1255 let hasSideEffects = 1;
1257 def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
1258 let OutOperandList = (outs);
1259 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size);
1260 let AsmString = "# XRay Typed Event Log.";
1261 let usesCustomInserter = 1;
1265 let hasSideEffects = 1;
1267 def FENTRY_CALL : StandardPseudoInstruction {
1268 let OutOperandList = (outs);
1269 let InOperandList = (ins);
1270 let AsmString = "# FEntry call";
1271 let usesCustomInserter = 1;
1274 let hasSideEffects = 1;
1276 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
1277 let OutOperandList = (outs);
1278 let InOperandList = (ins variable_ops);
1280 let hasSideEffects = 1;
1283 // Generic opcodes used in GlobalISel.
1284 include "llvm/Target/GenericOpcodes.td"
1286 //===----------------------------------------------------------------------===//
1287 // AsmParser - This class can be implemented by targets that wish to implement
1290 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
1291 // syntax on X86 for example).
1294 // AsmParserClassName - This specifies the suffix to use for the asmparser
1295 // class. Generated AsmParser classes are always prefixed with the target
1297 string AsmParserClassName = "AsmParser";
1299 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
1300 // function of the AsmParser class to call on every matched instruction.
1301 // This can be used to perform target specific instruction post-processing.
1302 string AsmParserInstCleanup = "";
1304 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand
1305 // written register name matcher
1306 bit ShouldEmitMatchRegisterName = 1;
1308 // Set to true if the target needs a generated 'alternative register name'
1311 // This generates a function which can be used to lookup registers from
1312 // their aliases. This function will fail when called on targets where
1313 // several registers share the same alias (i.e. not a 1:1 mapping).
1314 bit ShouldEmitMatchRegisterAltName = 0;
1316 // Set to true if MatchRegisterName and MatchRegisterAltName functions
1317 // should be generated even if there are duplicate register names. The
1318 // target is responsible for coercing aliased registers as necessary
1319 // (e.g. in validateTargetOperandClass), and there are no guarantees about
1320 // which numeric register identifier will be returned in the case of
1321 // multiple matches.
1322 bit AllowDuplicateRegisterNames = 0;
1324 // HasMnemonicFirst - Set to false if target instructions don't always
1325 // start with a mnemonic as the first token.
1326 bit HasMnemonicFirst = 1;
1328 // ReportMultipleNearMisses -
1329 // When 0, the assembly matcher reports an error for one encoding or operand
1330 // that did not match the parsed instruction.
1331 // When 1, the assembly matcher returns a list of encodings that were close
1332 // to matching the parsed instruction, so to allow more detailed error
1334 bit ReportMultipleNearMisses = 0;
1336 def DefaultAsmParser : AsmParser;
1338 //===----------------------------------------------------------------------===//
1339 // AsmParserVariant - Subtargets can have multiple different assembly parsers
1340 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
1341 // implemented by targets to describe such variants.
1343 class AsmParserVariant {
1344 // Variant - AsmParsers can be of multiple different variants. Variants are
1345 // used to support targets that need to parser multiple formats for the
1346 // assembly language.
1349 // Name - The AsmParser variant name (e.g., AT&T vs Intel).
1352 // CommentDelimiter - If given, the delimiter string used to recognize
1353 // comments which are hard coded in the .td assembler strings for individual
1355 string CommentDelimiter = "";
1357 // RegisterPrefix - If given, the token prefix which indicates a register
1358 // token. This is used by the matcher to automatically recognize hard coded
1359 // register tokens as constrained registers, instead of tokens, for the
1360 // purposes of matching.
1361 string RegisterPrefix = "";
1363 // TokenizingCharacters - Characters that are standalone tokens
1364 string TokenizingCharacters = "[]*!";
1366 // SeparatorCharacters - Characters that are not tokens
1367 string SeparatorCharacters = " \t,";
1369 // BreakCharacters - Characters that start new identifiers
1370 string BreakCharacters = "";
1372 def DefaultAsmParserVariant : AsmParserVariant;
1374 // Operators for combining SubtargetFeatures in AssemblerPredicates
1378 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
1379 /// matches instructions and aliases.
1380 class AssemblerPredicate<dag cond, string name = ""> {
1381 bit AssemblerMatcherPredicate = 1;
1382 dag AssemblerCondDag = cond;
1383 string PredicateName = name;
1386 /// TokenAlias - This class allows targets to define assembler token
1387 /// operand aliases. That is, a token literal operand which is equivalent
1388 /// to another, canonical, token literal. For example, ARM allows:
1389 /// vmov.u32 s4, #0 -> vmov.i32, #0
1390 /// 'u32' is a more specific designator for the 32-bit integer type specifier
1391 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
1392 /// def : TokenAlias<".u32", ".i32">;
1394 /// This works by marking the match class of 'From' as a subclass of the
1395 /// match class of 'To'.
1396 class TokenAlias<string From, string To> {
1397 string FromToken = From;
1398 string ToToken = To;
1401 /// MnemonicAlias - This class allows targets to define assembler mnemonic
1402 /// aliases. This should be used when all forms of one mnemonic are accepted
1403 /// with a different mnemonic. For example, X86 allows:
1404 /// sal %al, 1 -> shl %al, 1
1405 /// sal %ax, %cl -> shl %ax, %cl
1406 /// sal %eax, %cl -> shl %eax, %cl
1407 /// etc. Though "sal" is accepted with many forms, all of them are directly
1408 /// translated to a shl, so it can be handled with (in the case of X86, it
1409 /// actually has one for each suffix as well):
1410 /// def : MnemonicAlias<"sal", "shl">;
1412 /// Mnemonic aliases are mapped before any other translation in the match phase,
1413 /// and do allow Requires predicates, e.g.:
1415 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1416 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1418 /// Mnemonic aliases can also be constrained to specific variants, e.g.:
1420 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1422 /// If no variant (e.g., "att" or "intel") is specified then the alias is
1423 /// applied unconditionally.
1424 class MnemonicAlias<string From, string To, string VariantName = ""> {
1425 string FromMnemonic = From;
1426 string ToMnemonic = To;
1427 string AsmVariantName = VariantName;
1429 // Predicates - Predicates that must be true for this remapping to happen.
1430 list<Predicate> Predicates = [];
1433 /// InstAlias - This defines an alternate assembly syntax that is allowed to
1434 /// match an instruction that has a different (more canonical) assembly
1436 class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
1437 string AsmString = Asm; // The .s format to match the instruction with.
1438 dag ResultInst = Result; // The MCInst to generate.
1440 // This determines which order the InstPrinter detects aliases for
1441 // printing. A larger value makes the alias more likely to be
1442 // emitted. The Instruction's own definition is notionally 0.5, so 0
1443 // disables printing and 1 enables it if there are no conflicting aliases.
1444 int EmitPriority = Emit;
1446 // Predicates - Predicates that must be true for this to match.
1447 list<Predicate> Predicates = [];
1449 // If the instruction specified in Result has defined an AsmMatchConverter
1450 // then setting this to 1 will cause the alias to use the AsmMatchConverter
1451 // function when converting the OperandVector into an MCInst instead of the
1452 // function that is generated by the dag Result.
1453 // Setting this to 0 will cause the alias to ignore the Result instruction's
1454 // defined AsmMatchConverter and instead use the function generated by the
1456 bit UseInstAsmMatchConverter = 1;
1458 // Assembler variant name to use for this alias. If not specified then
1459 // assembler variants will be determined based on AsmString
1460 string AsmVariantName = VariantName;
1463 //===----------------------------------------------------------------------===//
1464 // AsmWriter - This class can be implemented by targets that need to customize
1465 // the format of the .s file writer.
1467 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1468 // on X86 for example).
1471 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
1472 // class. Generated AsmWriter classes are always prefixed with the target
1474 string AsmWriterClassName = "InstPrinter";
1476 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1477 // the various print methods.
1478 // FIXME: Remove after all ports are updated.
1479 int PassSubtarget = 0;
1481 // Variant - AsmWriters can be of multiple different variants. Variants are
1482 // used to support targets that need to emit assembly code in ways that are
1483 // mostly the same for different targets, but have minor differences in
1484 // syntax. If the asmstring contains {|} characters in them, this integer
1485 // will specify which alternative to use. For example "{x|y|z}" with Variant
1486 // == 1, will expand to "y".
1489 def DefaultAsmWriter : AsmWriter;
1492 //===----------------------------------------------------------------------===//
1493 // Target - This class contains the "global" target information
1496 // InstructionSet - Instruction set description for this target.
1497 InstrInfo InstructionSet;
1499 // AssemblyParsers - The AsmParser instances available for this target.
1500 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1502 /// AssemblyParserVariants - The AsmParserVariant instances available for
1504 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1506 // AssemblyWriters - The AsmWriter instances available for this target.
1507 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1509 // AllowRegisterRenaming - Controls whether this target allows
1510 // post-register-allocation renaming of registers. This is done by
1511 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
1512 // for all opcodes if this flag is set to 0.
1513 int AllowRegisterRenaming = 0;
1516 //===----------------------------------------------------------------------===//
1517 // SubtargetFeature - A characteristic of the chip set.
1519 class SubtargetFeature<string n, string a, string v, string d,
1520 list<SubtargetFeature> i = []> {
1521 // Name - Feature name. Used by command line (-mattr=) to determine the
1522 // appropriate target chip.
1526 // Attribute - Attribute to be set by feature.
1528 string Attribute = a;
1530 // Value - Value the attribute to be set to by feature.
1534 // Desc - Feature description. Used by command line (-mattr=) to display help
1539 // Implies - Features that this feature implies are present. If one of those
1540 // features isn't set, then this one shouldn't be set either.
1542 list<SubtargetFeature> Implies = i;
1545 /// Specifies a Subtarget feature that this instruction is deprecated on.
1546 class Deprecated<SubtargetFeature dep> {
1547 SubtargetFeature DeprecatedFeatureMask = dep;
1550 /// A custom predicate used to determine if an instruction is
1551 /// deprecated or not.
1552 class ComplexDeprecationPredicate<string dep> {
1553 string ComplexDeprecationPredicate = dep;
1556 //===----------------------------------------------------------------------===//
1557 // Processor chip sets - These values represent each of the chip sets supported
1558 // by the scheduler. Each Processor definition requires corresponding
1559 // instruction itineraries.
1561 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1562 // Name - Chip set name. Used by command line (-mcpu=) to determine the
1563 // appropriate target chip.
1567 // SchedModel - The machine model for scheduling and instruction cost.
1569 SchedMachineModel SchedModel = NoSchedModel;
1571 // ProcItin - The scheduling information for the target processor.
1573 ProcessorItineraries ProcItin = pi;
1575 // Features - list of
1576 list<SubtargetFeature> Features = f;
1579 // ProcessorModel allows subtargets to specify the more general
1580 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1581 // gradually move to this newer form.
1583 // Although this class always passes NoItineraries to the Processor
1584 // class, the SchedMachineModel may still define valid Itineraries.
1585 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1586 : Processor<n, NoItineraries, f> {
1590 //===----------------------------------------------------------------------===//
1591 // InstrMapping - This class is used to create mapping tables to relate
1592 // instructions with each other based on the values specified in RowFields,
1593 // ColFields, KeyCol and ValueCols.
1595 class InstrMapping {
1596 // FilterClass - Used to limit search space only to the instructions that
1597 // define the relationship modeled by this InstrMapping record.
1600 // RowFields - List of fields/attributes that should be same for all the
1601 // instructions in a row of the relation table. Think of this as a set of
1602 // properties shared by all the instructions related by this relationship
1603 // model and is used to categorize instructions into subgroups. For instance,
1604 // if we want to define a relation that maps 'Add' instruction to its
1605 // predicated forms, we can define RowFields like this:
1607 // let RowFields = BaseOp
1608 // All add instruction predicated/non-predicated will have to set their BaseOp
1609 // to the same value.
1611 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1612 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1613 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1614 list<string> RowFields = [];
1616 // List of fields/attributes that are same for all the instructions
1617 // in a column of the relation table.
1618 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1619 // based on the 'predSense' values. All the instruction in a specific
1620 // column have the same value and it is fixed for the column according
1621 // to the values set in 'ValueCols'.
1622 list<string> ColFields = [];
1624 // Values for the fields/attributes listed in 'ColFields'.
1625 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1626 // that models this relation) should be non-predicated.
1627 // In the example above, 'Add' is the key instruction.
1628 list<string> KeyCol = [];
1630 // List of values for the fields/attributes listed in 'ColFields', one for
1631 // each column in the relation table.
1633 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1634 // table. First column requires all the instructions to have predSense
1635 // set to 'true' and second column requires it to be 'false'.
1636 list<list<string> > ValueCols = [];
1639 //===----------------------------------------------------------------------===//
1640 // Pull in the common support for calling conventions.
1642 include "llvm/Target/TargetCallingConv.td"
1644 //===----------------------------------------------------------------------===//
1645 // Pull in the common support for DAG isel generation.
1647 include "llvm/Target/TargetSelectionDAG.td"
1649 //===----------------------------------------------------------------------===//
1650 // Pull in the common support for Global ISel register bank info generation.
1652 include "llvm/Target/GlobalISel/RegisterBank.td"
1654 //===----------------------------------------------------------------------===//
1655 // Pull in the common support for DAG isel generation.
1657 include "llvm/Target/GlobalISel/Target.td"
1659 //===----------------------------------------------------------------------===//
1660 // Pull in the common support for the Global ISel DAG-based selector generation.
1662 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
1664 //===----------------------------------------------------------------------===//
1665 // Pull in the common support for Pfm Counters generation.
1667 include "llvm/Target/TargetPfmCounters.td"