1 //===- DemandedBits.cpp - Determine demanded bits -------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This pass implements a demanded bits analysis. A demanded bit is one that
10 // contributes to a result; bits that are not demanded can be either zero or
11 // one without affecting control or data flow. For example in this sequence:
13 // %1 = add i32 %x, %y
14 // %2 = trunc i32 %1 to i16
16 // Only the lowest 16 bits of %1 are demanded; the rest are removed by the
19 //===----------------------------------------------------------------------===//
21 #include "llvm/Analysis/DemandedBits.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/Analysis/AssumptionCache.h"
26 #include "llvm/Analysis/ValueTracking.h"
27 #include "llvm/IR/BasicBlock.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Dominators.h"
32 #include "llvm/IR/InstIterator.h"
33 #include "llvm/IR/InstrTypes.h"
34 #include "llvm/IR/Instruction.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/IR/Module.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/IR/PassManager.h"
40 #include "llvm/IR/PatternMatch.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/IR/Use.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/Casting.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/KnownBits.h"
48 #include "llvm/Support/raw_ostream.h"
53 using namespace llvm::PatternMatch;
55 #define DEBUG_TYPE "demanded-bits"
57 char DemandedBitsWrapperPass::ID = 0;
59 INITIALIZE_PASS_BEGIN(DemandedBitsWrapperPass, "demanded-bits",
60 "Demanded bits analysis", false, false)
61 INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
62 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
63 INITIALIZE_PASS_END(DemandedBitsWrapperPass, "demanded-bits",
64 "Demanded bits analysis", false, false)
66 DemandedBitsWrapperPass::DemandedBitsWrapperPass() : FunctionPass(ID) {
67 initializeDemandedBitsWrapperPassPass(*PassRegistry::getPassRegistry());
70 void DemandedBitsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AssumptionCacheTracker>();
73 AU.addRequired<DominatorTreeWrapperPass>();
77 void DemandedBitsWrapperPass::print(raw_ostream &OS, const Module *M) const {
81 static bool isAlwaysLive(Instruction *I) {
82 return I->isTerminator() || isa<DbgInfoIntrinsic>(I) || I->isEHPad() ||
83 I->mayHaveSideEffects();
86 void DemandedBits::determineLiveOperandBits(
87 const Instruction *UserI, const Value *Val, unsigned OperandNo,
88 const APInt &AOut, APInt &AB, KnownBits &Known, KnownBits &Known2,
89 bool &KnownBitsComputed) {
90 unsigned BitWidth = AB.getBitWidth();
92 // We're called once per operand, but for some instructions, we need to
93 // compute known bits of both operands in order to determine the live bits of
94 // either (when both operands are instructions themselves). We don't,
95 // however, want to do this twice, so we cache the result in APInts that live
96 // in the caller. For the two-relevant-operands case, both operand values are
98 auto ComputeKnownBits =
99 [&](unsigned BitWidth, const Value *V1, const Value *V2) {
100 if (KnownBitsComputed)
102 KnownBitsComputed = true;
104 const DataLayout &DL = UserI->getModule()->getDataLayout();
105 Known = KnownBits(BitWidth);
106 computeKnownBits(V1, Known, DL, 0, &AC, UserI, &DT);
109 Known2 = KnownBits(BitWidth);
110 computeKnownBits(V2, Known2, DL, 0, &AC, UserI, &DT);
114 switch (UserI->getOpcode()) {
116 case Instruction::Call:
117 case Instruction::Invoke:
118 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI))
119 switch (II->getIntrinsicID()) {
121 case Intrinsic::bswap:
122 // The alive bits of the input are the swapped alive bits of
124 AB = AOut.byteSwap();
126 case Intrinsic::bitreverse:
127 // The alive bits of the input are the reversed alive bits of
129 AB = AOut.reverseBits();
131 case Intrinsic::ctlz:
132 if (OperandNo == 0) {
133 // We need some output bits, so we need all bits of the
134 // input to the left of, and including, the leftmost bit
136 ComputeKnownBits(BitWidth, Val, nullptr);
137 AB = APInt::getHighBitsSet(BitWidth,
138 std::min(BitWidth, Known.countMaxLeadingZeros()+1));
141 case Intrinsic::cttz:
142 if (OperandNo == 0) {
143 // We need some output bits, so we need all bits of the
144 // input to the right of, and including, the rightmost bit
146 ComputeKnownBits(BitWidth, Val, nullptr);
147 AB = APInt::getLowBitsSet(BitWidth,
148 std::min(BitWidth, Known.countMaxTrailingZeros()+1));
151 case Intrinsic::fshl:
152 case Intrinsic::fshr: {
154 if (OperandNo == 2) {
155 // Shift amount is modulo the bitwidth. For powers of two we have
156 // SA % BW == SA & (BW - 1).
157 if (isPowerOf2_32(BitWidth))
159 } else if (match(II->getOperand(2), m_APInt(SA))) {
160 // Normalize to funnel shift left. APInt shifts of BitWidth are well-
161 // defined, so no need to special-case zero shifts here.
162 uint64_t ShiftAmt = SA->urem(BitWidth);
163 if (II->getIntrinsicID() == Intrinsic::fshr)
164 ShiftAmt = BitWidth - ShiftAmt;
167 AB = AOut.lshr(ShiftAmt);
168 else if (OperandNo == 1)
169 AB = AOut.shl(BitWidth - ShiftAmt);
175 case Instruction::Add:
176 case Instruction::Sub:
177 case Instruction::Mul:
178 // Find the highest live output bit. We don't need any more input
179 // bits than that (adds, and thus subtracts, ripple only to the
181 AB = APInt::getLowBitsSet(BitWidth, AOut.getActiveBits());
183 case Instruction::Shl:
184 if (OperandNo == 0) {
185 const APInt *ShiftAmtC;
186 if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
187 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
188 AB = AOut.lshr(ShiftAmt);
190 // If the shift is nuw/nsw, then the high bits are not dead
191 // (because we've promised that they *must* be zero).
192 const ShlOperator *S = cast<ShlOperator>(UserI);
193 if (S->hasNoSignedWrap())
194 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
195 else if (S->hasNoUnsignedWrap())
196 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
200 case Instruction::LShr:
201 if (OperandNo == 0) {
202 const APInt *ShiftAmtC;
203 if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
204 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
205 AB = AOut.shl(ShiftAmt);
207 // If the shift is exact, then the low bits are not dead
208 // (they must be zero).
209 if (cast<LShrOperator>(UserI)->isExact())
210 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
214 case Instruction::AShr:
215 if (OperandNo == 0) {
216 const APInt *ShiftAmtC;
217 if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
218 uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
219 AB = AOut.shl(ShiftAmt);
220 // Because the high input bit is replicated into the
221 // high-order bits of the result, if we need any of those
222 // bits, then we must keep the highest input bit.
223 if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
227 // If the shift is exact, then the low bits are not dead
228 // (they must be zero).
229 if (cast<AShrOperator>(UserI)->isExact())
230 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
234 case Instruction::And:
237 // For bits that are known zero, the corresponding bits in the
238 // other operand are dead (unless they're both zero, in which
239 // case they can't both be dead, so just mark the LHS bits as
241 ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
245 AB &= ~(Known.Zero & ~Known2.Zero);
247 case Instruction::Or:
250 // For bits that are known one, the corresponding bits in the
251 // other operand are dead (unless they're both one, in which
252 // case they can't both be dead, so just mark the LHS bits as
254 ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
258 AB &= ~(Known.One & ~Known2.One);
260 case Instruction::Xor:
261 case Instruction::PHI:
264 case Instruction::Trunc:
265 AB = AOut.zext(BitWidth);
267 case Instruction::ZExt:
268 AB = AOut.trunc(BitWidth);
270 case Instruction::SExt:
271 AB = AOut.trunc(BitWidth);
272 // Because the high input bit is replicated into the
273 // high-order bits of the result, if we need any of those
274 // bits, then we must keep the highest input bit.
275 if ((AOut & APInt::getHighBitsSet(AOut.getBitWidth(),
276 AOut.getBitWidth() - BitWidth))
280 case Instruction::Select:
284 case Instruction::ExtractElement:
288 case Instruction::InsertElement:
289 case Instruction::ShuffleVector:
290 if (OperandNo == 0 || OperandNo == 1)
296 bool DemandedBitsWrapperPass::runOnFunction(Function &F) {
297 auto &AC = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
298 auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
299 DB.emplace(F, AC, DT);
303 void DemandedBitsWrapperPass::releaseMemory() {
307 void DemandedBits::performAnalysis() {
309 // Analysis already completed for this function.
317 SmallSetVector<Instruction*, 16> Worklist;
319 // Collect the set of "root" instructions that are known live.
320 for (Instruction &I : instructions(F)) {
321 if (!isAlwaysLive(&I))
324 LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
325 // For integer-valued instructions, set up an initial empty set of alive
326 // bits and add the instruction to the work list. For other instructions
327 // add their operands to the work list (for integer values operands, mark
328 // all bits as live).
329 Type *T = I.getType();
330 if (T->isIntOrIntVectorTy()) {
331 if (AliveBits.try_emplace(&I, T->getScalarSizeInBits(), 0).second)
337 // Non-integer-typed instructions...
338 for (Use &OI : I.operands()) {
339 if (Instruction *J = dyn_cast<Instruction>(OI)) {
340 Type *T = J->getType();
341 if (T->isIntOrIntVectorTy())
342 AliveBits[J] = APInt::getAllOnesValue(T->getScalarSizeInBits());
348 // To save memory, we don't add I to the Visited set here. Instead, we
349 // check isAlwaysLive on every instruction when searching for dead
350 // instructions later (we need to check isAlwaysLive for the
351 // integer-typed instructions anyway).
354 // Propagate liveness backwards to operands.
355 while (!Worklist.empty()) {
356 Instruction *UserI = Worklist.pop_back_val();
358 LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
360 bool InputIsKnownDead = false;
361 if (UserI->getType()->isIntOrIntVectorTy()) {
362 AOut = AliveBits[UserI];
363 LLVM_DEBUG(dbgs() << " Alive Out: 0x"
364 << Twine::utohexstr(AOut.getLimitedValue()));
366 // If all bits of the output are dead, then all bits of the input
368 InputIsKnownDead = !AOut && !isAlwaysLive(UserI);
370 LLVM_DEBUG(dbgs() << "\n");
372 KnownBits Known, Known2;
373 bool KnownBitsComputed = false;
374 // Compute the set of alive bits for each operand. These are anded into the
375 // existing set, if any, and if that changes the set of alive bits, the
376 // operand is added to the work-list.
377 for (Use &OI : UserI->operands()) {
378 // We also want to detect dead uses of arguments, but will only store
379 // demanded bits for instructions.
380 Instruction *I = dyn_cast<Instruction>(OI);
381 if (!I && !isa<Argument>(OI))
384 Type *T = OI->getType();
385 if (T->isIntOrIntVectorTy()) {
386 unsigned BitWidth = T->getScalarSizeInBits();
387 APInt AB = APInt::getAllOnesValue(BitWidth);
388 if (InputIsKnownDead) {
389 AB = APInt(BitWidth, 0);
391 // Bits of each operand that are used to compute alive bits of the
392 // output are alive, all others are dead.
393 determineLiveOperandBits(UserI, OI, OI.getOperandNo(), AOut, AB,
394 Known, Known2, KnownBitsComputed);
396 // Keep track of uses which have no demanded bits.
397 if (AB.isNullValue())
398 DeadUses.insert(&OI);
404 // If we've added to the set of alive bits (or the operand has not
405 // been previously visited), then re-queue the operand to be visited
407 auto Res = AliveBits.try_emplace(I);
408 if (Res.second || (AB |= Res.first->second) != Res.first->second) {
409 Res.first->second = std::move(AB);
413 } else if (I && Visited.insert(I).second) {
420 APInt DemandedBits::getDemandedBits(Instruction *I) {
423 auto Found = AliveBits.find(I);
424 if (Found != AliveBits.end())
425 return Found->second;
427 const DataLayout &DL = I->getModule()->getDataLayout();
428 return APInt::getAllOnesValue(
429 DL.getTypeSizeInBits(I->getType()->getScalarType()));
432 bool DemandedBits::isInstructionDead(Instruction *I) {
435 return !Visited.count(I) && AliveBits.find(I) == AliveBits.end() &&
439 bool DemandedBits::isUseDead(Use *U) {
440 // We only track integer uses, everything else is assumed live.
441 if (!(*U)->getType()->isIntOrIntVectorTy())
444 // Uses by always-live instructions are never dead.
445 Instruction *UserI = cast<Instruction>(U->getUser());
446 if (isAlwaysLive(UserI))
450 if (DeadUses.count(U))
453 // If no output bits are demanded, no input bits are demanded and the use
454 // is dead. These uses might not be explicitly present in the DeadUses map.
455 if (UserI->getType()->isIntOrIntVectorTy()) {
456 auto Found = AliveBits.find(UserI);
457 if (Found != AliveBits.end() && Found->second.isNullValue())
464 void DemandedBits::print(raw_ostream &OS) {
466 for (auto &KV : AliveBits) {
467 OS << "DemandedBits: 0x" << Twine::utohexstr(KV.second.getLimitedValue())
468 << " for " << *KV.first << '\n';
472 FunctionPass *llvm::createDemandedBitsWrapperPass() {
473 return new DemandedBitsWrapperPass();
476 AnalysisKey DemandedBitsAnalysis::Key;
478 DemandedBits DemandedBitsAnalysis::run(Function &F,
479 FunctionAnalysisManager &AM) {
480 auto &AC = AM.getResult<AssumptionAnalysis>(F);
481 auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
482 return DemandedBits(F, AC, DT);
485 PreservedAnalyses DemandedBitsPrinterPass::run(Function &F,
486 FunctionAnalysisManager &AM) {
487 AM.getResult<DemandedBitsAnalysis>(F).print(OS);
488 return PreservedAnalyses::all();