1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Methods common to all machine instructions.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Analysis/MemoryLocation.h"
26 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfoMetadata.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/ModuleSlotTracker.h"
53 #include "llvm/IR/Operator.h"
54 #include "llvm/IR/Type.h"
55 #include "llvm/IR/Value.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
60 #include "llvm/Support/CommandLine.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Support/FormattedStream.h"
65 #include "llvm/Support/LowLevelTypeImpl.h"
66 #include "llvm/Support/MathExtras.h"
67 #include "llvm/Support/raw_ostream.h"
68 #include "llvm/Target/TargetIntrinsicInfo.h"
69 #include "llvm/Target/TargetMachine.h"
80 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
81 if (const MachineBasicBlock *MBB = MI.getParent())
82 if (const MachineFunction *MF = MBB->getParent())
87 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 static void tryToGetTargetInfo(const MachineInstr &MI,
90 const TargetRegisterInfo *&TRI,
91 const MachineRegisterInfo *&MRI,
92 const TargetIntrinsicInfo *&IntrinsicInfo,
93 const TargetInstrInfo *&TII) {
95 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
96 TRI = MF->getSubtarget().getRegisterInfo();
97 MRI = &MF->getRegInfo();
98 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
99 TII = MF->getSubtarget().getInstrInfo();
103 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
104 if (MCID->ImplicitDefs)
105 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
108 if (MCID->ImplicitUses)
109 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
114 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
115 /// implicit operands. It reserves space for the number of operands specified by
117 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
118 DebugLoc dl, bool NoImp)
119 : MCID(&tid), debugLoc(std::move(dl)) {
120 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
122 // Reserve space for the expected number of operands.
123 if (unsigned NumOps = MCID->getNumOperands() +
124 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
125 CapOperands = OperandCapacity::get(NumOps);
126 Operands = MF.allocateOperandArray(CapOperands);
130 addImplicitDefUseOperands(MF);
133 /// MachineInstr ctor - Copies MachineInstr arg exactly
135 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
136 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
137 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
139 CapOperands = OperandCapacity::get(MI.getNumOperands());
140 Operands = MF.allocateOperandArray(CapOperands);
143 for (const MachineOperand &MO : MI.operands())
146 // Copy all the sensible flags.
150 /// getRegInfo - If this instruction is embedded into a MachineFunction,
151 /// return the MachineRegisterInfo object for the current function, otherwise
153 MachineRegisterInfo *MachineInstr::getRegInfo() {
154 if (MachineBasicBlock *MBB = getParent())
155 return &MBB->getParent()->getRegInfo();
159 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
160 /// this instruction from their respective use lists. This requires that the
161 /// operands already be on their use lists.
162 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
163 for (MachineOperand &MO : operands())
165 MRI.removeRegOperandFromUseList(&MO);
168 /// AddRegOperandsToUseLists - Add all of the register operands in
169 /// this instruction from their respective use lists. This requires that the
170 /// operands not be on their use lists yet.
171 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
172 for (MachineOperand &MO : operands())
174 MRI.addRegOperandToUseList(&MO);
177 void MachineInstr::addOperand(const MachineOperand &Op) {
178 MachineBasicBlock *MBB = getParent();
179 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
180 MachineFunction *MF = MBB->getParent();
181 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
185 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
186 /// ranges. If MRI is non-null also update use-def chains.
187 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
188 unsigned NumOps, MachineRegisterInfo *MRI) {
190 return MRI->moveOperands(Dst, Src, NumOps);
191 // MachineOperand is a trivially copyable type so we can just use memmove.
192 assert(Dst && Src && "Unknown operands");
193 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
196 /// addOperand - Add the specified operand to the instruction. If it is an
197 /// implicit operand, it is added to the end of the operand list. If it is
198 /// an explicit operand it is added at the end of the explicit operand list
199 /// (before the first implicit operand).
200 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
201 assert(MCID && "Cannot add operands before providing an instr descriptor");
203 // Check if we're adding one of our existing operands.
204 if (&Op >= Operands && &Op < Operands + NumOperands) {
205 // This is unusual: MI->addOperand(MI->getOperand(i)).
206 // If adding Op requires reallocating or moving existing operands around,
207 // the Op reference could go stale. Support it by copying Op.
208 MachineOperand CopyOp(Op);
209 return addOperand(MF, CopyOp);
212 // Find the insert location for the new operand. Implicit registers go at
213 // the end, everything else goes before the implicit regs.
215 // FIXME: Allow mixed explicit and implicit operands on inline asm.
216 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
217 // implicit-defs, but they must not be moved around. See the FIXME in
219 unsigned OpNo = getNumOperands();
220 bool isImpReg = Op.isReg() && Op.isImplicit();
221 if (!isImpReg && !isInlineAsm()) {
222 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
224 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
229 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
230 Op.getType() == MachineOperand::MO_MCSymbol;
231 // OpNo now points as the desired insertion point. Unless this is a variadic
232 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
233 // RegMask operands go between the explicit and implicit operands.
234 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
235 OpNo < MCID->getNumOperands() || isDebugOp) &&
236 "Trying to add an operand to a machine instr that is already done!");
239 MachineRegisterInfo *MRI = getRegInfo();
241 // Determine if the Operands array needs to be reallocated.
242 // Save the old capacity and operand array.
243 OperandCapacity OldCap = CapOperands;
244 MachineOperand *OldOperands = Operands;
245 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
246 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
247 Operands = MF.allocateOperandArray(CapOperands);
248 // Move the operands before the insertion point.
250 moveOperands(Operands, OldOperands, OpNo, MRI);
253 // Move the operands following the insertion point.
254 if (OpNo != NumOperands)
255 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
259 // Deallocate the old operand array.
260 if (OldOperands != Operands && OldOperands)
261 MF.deallocateOperandArray(OldCap, OldOperands);
263 // Copy Op into place. It still needs to be inserted into the MRI use lists.
264 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
265 NewMO->ParentMI = this;
267 // When adding a register operand, tell MRI about it.
268 if (NewMO->isReg()) {
269 // Ensure isOnRegUseList() returns false, regardless of Op's status.
270 NewMO->Contents.Reg.Prev = nullptr;
271 // Ignore existing ties. This is not a property that can be copied.
273 // Add the new operand to MRI, but only for instructions in an MBB.
275 MRI->addRegOperandToUseList(NewMO);
276 // The MCID operand information isn't accurate until we start adding
277 // explicit operands. The implicit operands are added first, then the
278 // explicits are inserted before them.
280 // Tie uses to defs as indicated in MCInstrDesc.
281 if (NewMO->isUse()) {
282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
284 tieOperands(DefIdx, OpNo);
286 // If the register operand is flagged as early, mark the operand as such.
287 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
288 NewMO->setIsEarlyClobber(true);
293 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
294 /// fewer operand than it started with.
296 void MachineInstr::RemoveOperand(unsigned OpNo) {
297 assert(OpNo < getNumOperands() && "Invalid operand number");
298 untieRegOperand(OpNo);
301 // Moving tied operands would break the ties.
302 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
303 if (Operands[i].isReg())
304 assert(!Operands[i].isTied() && "Cannot move tied operands");
307 MachineRegisterInfo *MRI = getRegInfo();
308 if (MRI && Operands[OpNo].isReg())
309 MRI->removeRegOperandFromUseList(Operands + OpNo);
311 // Don't call the MachineOperand destructor. A lot of this code depends on
312 // MachineOperand having a trivial destructor anyway, and adding a call here
313 // wouldn't make it 'destructor-correct'.
315 if (unsigned N = NumOperands - 1 - OpNo)
316 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
320 void MachineInstr::setExtraInfo(MachineFunction &MF,
321 ArrayRef<MachineMemOperand *> MMOs,
322 MCSymbol *PreInstrSymbol,
323 MCSymbol *PostInstrSymbol,
324 MDNode *HeapAllocMarker) {
325 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
326 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
327 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
329 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
331 // Drop all extra info if there is none.
332 if (NumPointers <= 0) {
337 // If more than one pointer, then store out of line. Store heap alloc markers
338 // out of line because PointerSumType cannot hold more than 4 tag types with
340 // FIXME: Maybe we should make the symbols in the extra info mutable?
341 else if (NumPointers > 1 || HasHeapAllocMarker) {
342 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
343 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
347 // Otherwise store the single pointer inline.
348 if (HasPreInstrSymbol)
349 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
350 else if (HasPostInstrSymbol)
351 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
353 Info.set<EIIK_MMO>(MMOs[0]);
356 void MachineInstr::dropMemRefs(MachineFunction &MF) {
357 if (memoperands_empty())
360 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
361 getHeapAllocMarker());
364 void MachineInstr::setMemRefs(MachineFunction &MF,
365 ArrayRef<MachineMemOperand *> MMOs) {
371 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
372 getHeapAllocMarker());
375 void MachineInstr::addMemOperand(MachineFunction &MF,
376 MachineMemOperand *MO) {
377 SmallVector<MachineMemOperand *, 2> MMOs;
378 MMOs.append(memoperands_begin(), memoperands_end());
380 setMemRefs(MF, MMOs);
383 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
385 // Nothing to do for a self-clone!
388 assert(&MF == MI.getMF() &&
389 "Invalid machine functions when cloning memory refrences!");
390 // See if we can just steal the extra info already allocated for the
391 // instruction. We can do this whenever the pre- and post-instruction symbols
392 // are the same (including null).
393 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
394 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
395 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
400 // Otherwise, fall back on a copy-based clone.
401 setMemRefs(MF, MI.memoperands());
404 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
406 static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
407 ArrayRef<MachineMemOperand *> RHS) {
408 if (LHS.size() != RHS.size())
411 auto LHSPointees = make_pointee_range(LHS);
412 auto RHSPointees = make_pointee_range(RHS);
413 return std::equal(LHSPointees.begin(), LHSPointees.end(),
414 RHSPointees.begin());
417 void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
418 ArrayRef<const MachineInstr *> MIs) {
419 // Try handling easy numbers of MIs with simpler mechanisms.
424 if (MIs.size() == 1) {
425 cloneMemRefs(MF, *MIs[0]);
428 // Because an empty memoperands list provides *no* information and must be
429 // handled conservatively (assuming the instruction can do anything), the only
430 // way to merge with it is to drop all other memoperands.
431 if (MIs[0]->memoperands_empty()) {
436 // Handle the general case.
437 SmallVector<MachineMemOperand *, 2> MergedMMOs;
438 // Start with the first instruction.
439 assert(&MF == MIs[0]->getMF() &&
440 "Invalid machine functions when cloning memory references!");
441 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
442 // Now walk all the other instructions and accumulate any different MMOs.
443 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
444 assert(&MF == MI.getMF() &&
445 "Invalid machine functions when cloning memory references!");
447 // Skip MIs with identical operands to the first. This is a somewhat
448 // arbitrary hack but will catch common cases without being quadratic.
449 // TODO: We could fully implement merge semantics here if needed.
450 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
453 // Because an empty memoperands list provides *no* information and must be
454 // handled conservatively (assuming the instruction can do anything), the
455 // only way to merge with it is to drop all other memoperands.
456 if (MI.memoperands_empty()) {
461 // Otherwise accumulate these into our temporary buffer of the merged state.
462 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
465 setMemRefs(MF, MergedMMOs);
468 void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
469 // Do nothing if old and new symbols are the same.
470 if (Symbol == getPreInstrSymbol())
473 // If there was only one symbol and we're removing it, just clear info.
474 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
479 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
480 getHeapAllocMarker());
483 void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
484 // Do nothing if old and new symbols are the same.
485 if (Symbol == getPostInstrSymbol())
488 // If there was only one symbol and we're removing it, just clear info.
489 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
494 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
495 getHeapAllocMarker());
498 void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
499 // Do nothing if old and new symbols are the same.
500 if (Marker == getHeapAllocMarker())
503 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
507 void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
508 const MachineInstr &MI) {
510 // Nothing to do for a self-clone!
513 assert(&MF == MI.getMF() &&
514 "Invalid machine functions when cloning instruction symbols!");
516 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
517 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
518 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
521 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
522 // For now, the just return the union of the flags. If the flags get more
523 // complicated over time, we might need more logic here.
524 return getFlags() | Other.getFlags();
527 uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
528 uint16_t MIFlags = 0;
529 // Copy the wrapping flags.
530 if (const OverflowingBinaryOperator *OB =
531 dyn_cast<OverflowingBinaryOperator>(&I)) {
532 if (OB->hasNoSignedWrap())
533 MIFlags |= MachineInstr::MIFlag::NoSWrap;
534 if (OB->hasNoUnsignedWrap())
535 MIFlags |= MachineInstr::MIFlag::NoUWrap;
538 // Copy the exact flag.
539 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
541 MIFlags |= MachineInstr::MIFlag::IsExact;
543 // Copy the fast-math flags.
544 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
545 const FastMathFlags Flags = FP->getFastMathFlags();
547 MIFlags |= MachineInstr::MIFlag::FmNoNans;
549 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
550 if (Flags.noSignedZeros())
551 MIFlags |= MachineInstr::MIFlag::FmNsz;
552 if (Flags.allowReciprocal())
553 MIFlags |= MachineInstr::MIFlag::FmArcp;
554 if (Flags.allowContract())
555 MIFlags |= MachineInstr::MIFlag::FmContract;
556 if (Flags.approxFunc())
557 MIFlags |= MachineInstr::MIFlag::FmAfn;
558 if (Flags.allowReassoc())
559 MIFlags |= MachineInstr::MIFlag::FmReassoc;
565 void MachineInstr::copyIRFlags(const Instruction &I) {
566 Flags = copyFlagsFromInstruction(I);
569 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
570 assert(!isBundledWithPred() && "Must be called on bundle header");
571 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
572 if (MII->getDesc().getFlags() & Mask) {
573 if (Type == AnyInBundle)
576 if (Type == AllInBundle && !MII->isBundle())
579 // This was the last instruction in the bundle.
580 if (!MII->isBundledWithSucc())
581 return Type == AllInBundle;
585 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
586 MICheckType Check) const {
587 // If opcodes or number of operands are not the same then the two
588 // instructions are obviously not identical.
589 if (Other.getOpcode() != getOpcode() ||
590 Other.getNumOperands() != getNumOperands())
594 // We have passed the test above that both instructions have the same
595 // opcode, so we know that both instructions are bundles here. Let's compare
596 // MIs inside the bundle.
597 assert(Other.isBundle() && "Expected that both instructions are bundles.");
598 MachineBasicBlock::const_instr_iterator I1 = getIterator();
599 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
600 // Loop until we analysed the last intruction inside at least one of the
602 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
605 if (!I1->isIdenticalTo(*I2, Check))
608 // If we've reached the end of just one of the two bundles, but not both,
609 // the instructions are not identical.
610 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
614 // Check operands to make sure they match.
615 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
616 const MachineOperand &MO = getOperand(i);
617 const MachineOperand &OMO = Other.getOperand(i);
619 if (!MO.isIdenticalTo(OMO))
624 // Clients may or may not want to ignore defs when testing for equality.
625 // For example, machine CSE pass only cares about finding common
626 // subexpressions, so it's safe to ignore virtual register defs.
628 if (Check == IgnoreDefs)
630 else if (Check == IgnoreVRegDefs) {
631 if (!Register::isVirtualRegister(MO.getReg()) ||
632 !Register::isVirtualRegister(OMO.getReg()))
633 if (!MO.isIdenticalTo(OMO))
636 if (!MO.isIdenticalTo(OMO))
638 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
642 if (!MO.isIdenticalTo(OMO))
644 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
648 // If DebugLoc does not match then two debug instructions are not identical.
650 if (getDebugLoc() && Other.getDebugLoc() &&
651 getDebugLoc() != Other.getDebugLoc())
656 const MachineFunction *MachineInstr::getMF() const {
657 return getParent()->getParent();
660 MachineInstr *MachineInstr::removeFromParent() {
661 assert(getParent() && "Not embedded in a basic block!");
662 return getParent()->remove(this);
665 MachineInstr *MachineInstr::removeFromBundle() {
666 assert(getParent() && "Not embedded in a basic block!");
667 return getParent()->remove_instr(this);
670 void MachineInstr::eraseFromParent() {
671 assert(getParent() && "Not embedded in a basic block!");
672 getParent()->erase(this);
675 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
676 assert(getParent() && "Not embedded in a basic block!");
677 MachineBasicBlock *MBB = getParent();
678 MachineFunction *MF = MBB->getParent();
679 assert(MF && "Not embedded in a function!");
681 MachineInstr *MI = (MachineInstr *)this;
682 MachineRegisterInfo &MRI = MF->getRegInfo();
684 for (const MachineOperand &MO : MI->operands()) {
685 if (!MO.isReg() || !MO.isDef())
687 Register Reg = MO.getReg();
688 if (!Reg.isVirtual())
690 MRI.markUsesInDebugValueAsUndef(Reg);
692 MI->eraseFromParent();
695 void MachineInstr::eraseFromBundle() {
696 assert(getParent() && "Not embedded in a basic block!");
697 getParent()->erase_instr(this);
700 bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
703 switch (getOpcode()) {
704 case TargetOpcode::PATCHABLE_EVENT_CALL:
705 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
706 case TargetOpcode::PATCHPOINT:
707 case TargetOpcode::STACKMAP:
708 case TargetOpcode::STATEPOINT:
714 bool MachineInstr::shouldUpdateCallSiteInfo() const {
716 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
717 return isCandidateForCallSiteEntry();
720 unsigned MachineInstr::getNumExplicitOperands() const {
721 unsigned NumOperands = MCID->getNumOperands();
722 if (!MCID->isVariadic())
725 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
726 const MachineOperand &MO = getOperand(I);
727 // The operands must always be in the following order:
728 // - explicit reg defs,
729 // - other explicit operands (reg uses, immediates, etc.),
730 // - implicit reg defs
731 // - implicit reg uses
732 if (MO.isReg() && MO.isImplicit())
739 unsigned MachineInstr::getNumExplicitDefs() const {
740 unsigned NumDefs = MCID->getNumDefs();
741 if (!MCID->isVariadic())
744 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
745 const MachineOperand &MO = getOperand(I);
746 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
753 void MachineInstr::bundleWithPred() {
754 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
755 setFlag(BundledPred);
756 MachineBasicBlock::instr_iterator Pred = getIterator();
758 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
759 Pred->setFlag(BundledSucc);
762 void MachineInstr::bundleWithSucc() {
763 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
764 setFlag(BundledSucc);
765 MachineBasicBlock::instr_iterator Succ = getIterator();
767 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
768 Succ->setFlag(BundledPred);
771 void MachineInstr::unbundleFromPred() {
772 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
773 clearFlag(BundledPred);
774 MachineBasicBlock::instr_iterator Pred = getIterator();
776 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
777 Pred->clearFlag(BundledSucc);
780 void MachineInstr::unbundleFromSucc() {
781 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
782 clearFlag(BundledSucc);
783 MachineBasicBlock::instr_iterator Succ = getIterator();
785 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
786 Succ->clearFlag(BundledPred);
789 bool MachineInstr::isStackAligningInlineAsm() const {
791 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
792 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
798 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
799 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
800 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
801 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
804 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
805 unsigned *GroupNo) const {
806 assert(isInlineAsm() && "Expected an inline asm instruction");
807 assert(OpIdx < getNumOperands() && "OpIdx out of range");
809 // Ignore queries about the initial operands.
810 if (OpIdx < InlineAsm::MIOp_FirstOperand)
815 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
817 const MachineOperand &FlagMO = getOperand(i);
818 // If we reach the implicit register operands, stop looking.
821 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
822 if (i + NumOps > OpIdx) {
832 const DILabel *MachineInstr::getDebugLabel() const {
833 assert(isDebugLabel() && "not a DBG_LABEL");
834 return cast<DILabel>(getOperand(0).getMetadata());
837 const MachineOperand &MachineInstr::getDebugVariableOp() const {
838 assert(isDebugValue() && "not a DBG_VALUE");
839 return getOperand(2);
842 MachineOperand &MachineInstr::getDebugVariableOp() {
843 assert(isDebugValue() && "not a DBG_VALUE");
844 return getOperand(2);
847 const DILocalVariable *MachineInstr::getDebugVariable() const {
848 assert(isDebugValue() && "not a DBG_VALUE");
849 return cast<DILocalVariable>(getOperand(2).getMetadata());
852 MachineOperand &MachineInstr::getDebugExpressionOp() {
853 assert(isDebugValue() && "not a DBG_VALUE");
854 return getOperand(3);
857 const DIExpression *MachineInstr::getDebugExpression() const {
858 assert(isDebugValue() && "not a DBG_VALUE");
859 return cast<DIExpression>(getOperand(3).getMetadata());
862 bool MachineInstr::isDebugEntryValue() const {
863 return isDebugValue() && getDebugExpression()->isEntryValue();
866 const TargetRegisterClass*
867 MachineInstr::getRegClassConstraint(unsigned OpIdx,
868 const TargetInstrInfo *TII,
869 const TargetRegisterInfo *TRI) const {
870 assert(getParent() && "Can't have an MBB reference here!");
871 assert(getMF() && "Can't have an MF reference here!");
872 const MachineFunction &MF = *getMF();
874 // Most opcodes have fixed constraints in their MCInstrDesc.
876 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
878 if (!getOperand(OpIdx).isReg())
881 // For tied uses on inline asm, get the constraint from the def.
883 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
886 // Inline asm stores register class constraints in the flag word.
887 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
891 unsigned Flag = getOperand(FlagIdx).getImm();
893 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
894 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
895 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
896 InlineAsm::hasRegClassConstraint(Flag, RCID))
897 return TRI->getRegClass(RCID);
899 // Assume that all registers in a memory operand are pointers.
900 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
901 return TRI->getPointerRegClass(MF);
906 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
907 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
908 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
909 // Check every operands inside the bundle if we have
912 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
914 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
915 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
917 // Otherwise, just check the current operands.
918 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
919 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
923 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
924 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
925 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
926 assert(CurRC && "Invalid initial register class");
927 // Check if Reg is constrained by some of its use/def from MI.
928 const MachineOperand &MO = getOperand(OpIdx);
929 if (!MO.isReg() || MO.getReg() != Reg)
931 // If yes, accumulate the constraints through the operand.
932 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
935 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
936 unsigned OpIdx, const TargetRegisterClass *CurRC,
937 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
938 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
939 const MachineOperand &MO = getOperand(OpIdx);
941 "Cannot get register constraints for non-register operand");
942 assert(CurRC && "Invalid initial register class");
943 if (unsigned SubIdx = MO.getSubReg()) {
945 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
947 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
949 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
953 /// Return the number of instructions inside the MI bundle, not counting the
954 /// header instruction.
955 unsigned MachineInstr::getBundleSize() const {
956 MachineBasicBlock::const_instr_iterator I = getIterator();
958 while (I->isBundledWithSucc()) {
965 /// Returns true if the MachineInstr has an implicit-use operand of exactly
966 /// the given register (not considering sub/super-registers).
967 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
968 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
969 const MachineOperand &MO = getOperand(i);
970 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
976 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
977 /// the specific register or -1 if it is not found. It further tightens
978 /// the search criteria to a use that kills the register if isKill is true.
979 int MachineInstr::findRegisterUseOperandIdx(
980 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
981 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982 const MachineOperand &MO = getOperand(i);
983 if (!MO.isReg() || !MO.isUse())
985 Register MOReg = MO.getReg();
988 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
989 if (!isKill || MO.isKill())
995 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
996 /// indicating if this instruction reads or writes Reg. This also considers
999 MachineInstr::readsWritesVirtualRegister(Register Reg,
1000 SmallVectorImpl<unsigned> *Ops) const {
1001 bool PartDef = false; // Partial redefine.
1002 bool FullDef = false; // Full define.
1005 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1006 const MachineOperand &MO = getOperand(i);
1007 if (!MO.isReg() || MO.getReg() != Reg)
1012 Use |= !MO.isUndef();
1013 else if (MO.getSubReg() && !MO.isUndef())
1014 // A partial def undef doesn't count as reading the register.
1019 // A partial redefine uses Reg unless there is also a full define.
1020 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1023 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1024 /// the specified register or -1 if it is not found. If isDead is true, defs
1025 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1026 /// also checks if there is a def of a super-register.
1028 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1029 const TargetRegisterInfo *TRI) const {
1030 bool isPhys = Register::isPhysicalRegister(Reg);
1031 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1032 const MachineOperand &MO = getOperand(i);
1033 // Accept regmask operands when Overlap is set.
1034 // Ignore them when looking for a specific def operand (Overlap == false).
1035 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1037 if (!MO.isReg() || !MO.isDef())
1039 Register MOReg = MO.getReg();
1040 bool Found = (MOReg == Reg);
1041 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1043 Found = TRI->regsOverlap(MOReg, Reg);
1045 Found = TRI->isSubRegister(MOReg, Reg);
1047 if (Found && (!isDead || MO.isDead()))
1053 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1054 /// operand list that is used to represent the predicate. It returns -1 if
1056 int MachineInstr::findFirstPredOperandIdx() const {
1057 // Don't call MCID.findFirstPredOperandIdx() because this variant
1058 // is sometimes called on an instruction that's not yet complete, and
1059 // so the number of operands is less than the MCID indicates. In
1060 // particular, the PTX target does this.
1061 const MCInstrDesc &MCID = getDesc();
1062 if (MCID.isPredicable()) {
1063 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1064 if (MCID.OpInfo[i].isPredicate())
1071 // MachineOperand::TiedTo is 4 bits wide.
1072 const unsigned TiedMax = 15;
1074 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1076 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1077 /// field. TiedTo can have these values:
1079 /// 0: Operand is not tied to anything.
1080 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1081 /// TiedMax: Tied to an operand >= TiedMax-1.
1083 /// The tied def must be one of the first TiedMax operands on a normal
1084 /// instruction. INLINEASM instructions allow more tied defs.
1086 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1087 MachineOperand &DefMO = getOperand(DefIdx);
1088 MachineOperand &UseMO = getOperand(UseIdx);
1089 assert(DefMO.isDef() && "DefIdx must be a def operand");
1090 assert(UseMO.isUse() && "UseIdx must be a use operand");
1091 assert(!DefMO.isTied() && "Def is already tied to another use");
1092 assert(!UseMO.isTied() && "Use is already tied to another def");
1094 if (DefIdx < TiedMax)
1095 UseMO.TiedTo = DefIdx + 1;
1097 // Inline asm can use the group descriptors to find tied operands, but on
1098 // normal instruction, the tied def must be within the first TiedMax
1100 assert(isInlineAsm() && "DefIdx out of range");
1101 UseMO.TiedTo = TiedMax;
1104 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1105 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1108 /// Given the index of a tied register operand, find the operand it is tied to.
1109 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1110 /// which must exist.
1111 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1112 const MachineOperand &MO = getOperand(OpIdx);
1113 assert(MO.isTied() && "Operand isn't tied");
1115 // Normally TiedTo is in range.
1116 if (MO.TiedTo < TiedMax)
1117 return MO.TiedTo - 1;
1119 // Uses on normal instructions can be out of range.
1120 if (!isInlineAsm()) {
1121 // Normal tied defs must be in the 0..TiedMax-1 range.
1124 // MO is a def. Search for the tied use.
1125 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1126 const MachineOperand &UseMO = getOperand(i);
1127 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1130 llvm_unreachable("Can't find tied use");
1133 // Now deal with inline asm by parsing the operand group descriptor flags.
1134 // Find the beginning of each operand group.
1135 SmallVector<unsigned, 8> GroupIdx;
1136 unsigned OpIdxGroup = ~0u;
1138 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1140 const MachineOperand &FlagMO = getOperand(i);
1141 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1142 unsigned CurGroup = GroupIdx.size();
1143 GroupIdx.push_back(i);
1144 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1145 // OpIdx belongs to this operand group.
1146 if (OpIdx > i && OpIdx < i + NumOps)
1147 OpIdxGroup = CurGroup;
1149 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1151 // Operands in this group are tied to operands in TiedGroup which must be
1152 // earlier. Find the number of operands between the two groups.
1153 unsigned Delta = i - GroupIdx[TiedGroup];
1155 // OpIdx is a use tied to TiedGroup.
1156 if (OpIdxGroup == CurGroup)
1157 return OpIdx - Delta;
1159 // OpIdx is a def tied to this use group.
1160 if (OpIdxGroup == TiedGroup)
1161 return OpIdx + Delta;
1163 llvm_unreachable("Invalid tied operand on inline asm");
1166 /// clearKillInfo - Clears kill flags on all operands.
1168 void MachineInstr::clearKillInfo() {
1169 for (MachineOperand &MO : operands()) {
1170 if (MO.isReg() && MO.isUse())
1171 MO.setIsKill(false);
1175 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1177 const TargetRegisterInfo &RegInfo) {
1178 if (Register::isPhysicalRegister(ToReg)) {
1180 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1181 for (MachineOperand &MO : operands()) {
1182 if (!MO.isReg() || MO.getReg() != FromReg)
1184 MO.substPhysReg(ToReg, RegInfo);
1187 for (MachineOperand &MO : operands()) {
1188 if (!MO.isReg() || MO.getReg() != FromReg)
1190 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1195 /// isSafeToMove - Return true if it is safe to move this instruction. If
1196 /// SawStore is set to true, it means that there is a store (or call) between
1197 /// the instruction's location and its intended destination.
1198 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1199 // Ignore stuff that we obviously can't move.
1201 // Treat volatile loads as stores. This is not strictly necessary for
1202 // volatiles, but it is required for atomic loads. It is not allowed to move
1203 // a load across an atomic load with Ordering > Monotonic.
1204 if (mayStore() || isCall() || isPHI() ||
1205 (mayLoad() && hasOrderedMemoryRef())) {
1210 if (isPosition() || isDebugInstr() || isTerminator() ||
1211 mayRaiseFPException() || hasUnmodeledSideEffects())
1214 // See if this instruction does a load. If so, we have to guarantee that the
1215 // loaded value doesn't change between the load and the its intended
1216 // destination. The check for isInvariantLoad gives the targe the chance to
1217 // classify the load as always returning a constant, e.g. a constant pool
1219 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1220 // Otherwise, this is a real load. If there is a store between the load and
1221 // end of block, we can't move it.
1227 bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1228 bool UseTBAA) const {
1229 const MachineFunction *MF = getMF();
1230 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1231 const MachineFrameInfo &MFI = MF->getFrameInfo();
1233 // If neither instruction stores to memory, they can't alias in any
1234 // meaningful way, even if they read from the same address.
1235 if (!mayStore() && !Other.mayStore())
1238 // Both instructions must be memory operations to be able to alias.
1239 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1242 // Let the target decide if memory accesses cannot possibly overlap.
1243 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1246 // FIXME: Need to handle multiple memory operands to support all targets.
1247 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1250 MachineMemOperand *MMOa = *memoperands_begin();
1251 MachineMemOperand *MMOb = *Other.memoperands_begin();
1253 // The following interface to AA is fashioned after DAGCombiner::isAlias
1254 // and operates with MachineMemOperand offset with some important
1256 // - LLVM fundamentally assumes flat address spaces.
1257 // - MachineOperand offset can *only* result from legalization and
1258 // cannot affect queries other than the trivial case of overlap
1260 // - These offsets never wrap and never step outside
1261 // of allocated objects.
1262 // - There should never be any negative offsets here.
1264 // FIXME: Modify API to hide this math from "user"
1265 // Even before we go to AA we can reason locally about some
1266 // memory objects. It can save compile time, and possibly catch some
1267 // corner cases not currently covered.
1269 int64_t OffsetA = MMOa->getOffset();
1270 int64_t OffsetB = MMOb->getOffset();
1271 int64_t MinOffset = std::min(OffsetA, OffsetB);
1273 uint64_t WidthA = MMOa->getSize();
1274 uint64_t WidthB = MMOb->getSize();
1275 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1276 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1278 const Value *ValA = MMOa->getValue();
1279 const Value *ValB = MMOb->getValue();
1280 bool SameVal = (ValA && ValB && (ValA == ValB));
1282 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1283 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1284 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1286 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1288 if (PSVa && PSVb && (PSVa == PSVb))
1293 if (!KnownWidthA || !KnownWidthB)
1295 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1296 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1297 return (MinOffset + LowWidth > MaxOffset);
1306 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1307 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1309 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1310 : MemoryLocation::UnknownSize;
1311 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1312 : MemoryLocation::UnknownSize;
1314 AliasResult AAResult = AA->alias(
1315 MemoryLocation(ValA, OverlapA,
1316 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1317 MemoryLocation(ValB, OverlapB,
1318 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1320 return (AAResult != NoAlias);
1323 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1324 /// or volatile memory reference, or if the information describing the memory
1325 /// reference is not available. Return false if it is known to have no ordered
1326 /// memory references.
1327 bool MachineInstr::hasOrderedMemoryRef() const {
1328 // An instruction known never to access memory won't have a volatile access.
1332 !hasUnmodeledSideEffects())
1335 // Otherwise, if the instruction has no memory reference information,
1336 // conservatively assume it wasn't preserved.
1337 if (memoperands_empty())
1340 // Check if any of our memory operands are ordered.
1341 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1342 return !MMO->isUnordered();
1346 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1347 /// trap and is loading from a location whose value is invariant across a run of
1349 bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1350 // If the instruction doesn't load at all, it isn't an invariant load.
1354 // If the instruction has lost its memoperands, conservatively assume that
1355 // it may not be an invariant load.
1356 if (memoperands_empty())
1359 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1361 for (MachineMemOperand *MMO : memoperands()) {
1362 if (!MMO->isUnordered())
1363 // If the memory operand has ordering side effects, we can't move the
1364 // instruction. Such an instruction is technically an invariant load,
1365 // but the caller code would need updated to expect that.
1367 if (MMO->isStore()) return false;
1368 if (MMO->isInvariant() && MMO->isDereferenceable())
1371 // A load from a constant PseudoSourceValue is invariant.
1372 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1373 if (PSV->isConstant(&MFI))
1376 if (const Value *V = MMO->getValue()) {
1377 // If we have an AliasAnalysis, ask it whether the memory is constant.
1379 AA->pointsToConstantMemory(
1380 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1384 // Otherwise assume conservatively.
1388 // Everything checks out.
1392 /// isConstantValuePHI - If the specified instruction is a PHI that always
1393 /// merges together the same virtual register, return the register, otherwise
1395 unsigned MachineInstr::isConstantValuePHI() const {
1398 assert(getNumOperands() >= 3 &&
1399 "It's illegal to have a PHI without source operands");
1401 Register Reg = getOperand(1).getReg();
1402 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1403 if (getOperand(i).getReg() != Reg)
1408 bool MachineInstr::hasUnmodeledSideEffects() const {
1409 if (hasProperty(MCID::UnmodeledSideEffects))
1411 if (isInlineAsm()) {
1412 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1413 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1420 bool MachineInstr::isLoadFoldBarrier() const {
1421 return mayStore() || isCall() || hasUnmodeledSideEffects();
1424 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1426 bool MachineInstr::allDefsAreDead() const {
1427 for (const MachineOperand &MO : operands()) {
1428 if (!MO.isReg() || MO.isUse())
1436 /// copyImplicitOps - Copy implicit register operands from specified
1437 /// instruction to this instruction.
1438 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1439 const MachineInstr &MI) {
1440 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1442 const MachineOperand &MO = MI.getOperand(i);
1443 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1448 bool MachineInstr::hasComplexRegisterTies() const {
1449 const MCInstrDesc &MCID = getDesc();
1450 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1451 const auto &Operand = getOperand(I);
1452 if (!Operand.isReg() || Operand.isDef())
1453 // Ignore the defined registers as MCID marks only the uses as tied.
1455 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1456 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1457 if (ExpectedTiedIdx != TiedIdx)
1463 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1464 const MachineRegisterInfo &MRI) const {
1465 const MachineOperand &Op = getOperand(OpIdx);
1469 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1470 return MRI.getType(Op.getReg());
1472 auto &OpInfo = getDesc().OpInfo[OpIdx];
1473 if (!OpInfo.isGenericType())
1474 return MRI.getType(Op.getReg());
1476 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1479 LLT TypeToPrint = MRI.getType(Op.getReg());
1480 // Don't mark the type index printed if it wasn't actually printed: maybe
1481 // another operand with the same type index has an actual type attached:
1482 if (TypeToPrint.isValid())
1483 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1487 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1488 LLVM_DUMP_METHOD void MachineInstr::dump() const {
1493 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1494 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1495 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1496 if (Depth >= MaxDepth)
1498 if (!AlreadySeenInstrs.insert(this).second)
1500 // PadToColumn always inserts at least one space.
1501 // Don't mess up the alignment if we don't want any space.
1503 fdbgs().PadToColumn(Depth * 2);
1505 for (const MachineOperand &MO : operands()) {
1506 if (!MO.isReg() || MO.isDef())
1508 Register Reg = MO.getReg();
1509 if (Reg.isPhysical())
1511 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1512 if (NewMI == nullptr)
1514 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1518 LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1519 unsigned MaxDepth) const {
1520 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1521 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1525 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1526 bool SkipDebugLoc, bool AddNewLine,
1527 const TargetInstrInfo *TII) const {
1528 const Module *M = nullptr;
1529 const Function *F = nullptr;
1530 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1531 F = &MF->getFunction();
1534 TII = MF->getSubtarget().getInstrInfo();
1537 ModuleSlotTracker MST(M);
1539 MST.incorporateFunction(*F);
1540 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1543 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1544 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1545 bool AddNewLine, const TargetInstrInfo *TII) const {
1546 // We can be a bit tidier if we know the MachineFunction.
1547 const TargetRegisterInfo *TRI = nullptr;
1548 const MachineRegisterInfo *MRI = nullptr;
1549 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1550 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1552 if (isCFIInstruction())
1553 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1555 SmallBitVector PrintedTypes(8);
1556 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1557 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1558 if (!ShouldPrintRegisterTies)
1560 const MachineOperand &MO = getOperand(OpIdx);
1561 if (MO.isReg() && MO.isTied() && !MO.isDef())
1562 return findTiedOperandIdx(OpIdx);
1565 unsigned StartOp = 0;
1566 unsigned e = getNumOperands();
1568 // Print explicitly defined operands on the left of an assignment syntax.
1569 while (StartOp < e) {
1570 const MachineOperand &MO = getOperand(StartOp);
1571 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1577 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1578 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1579 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1580 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1587 if (getFlag(MachineInstr::FrameSetup))
1588 OS << "frame-setup ";
1589 if (getFlag(MachineInstr::FrameDestroy))
1590 OS << "frame-destroy ";
1591 if (getFlag(MachineInstr::FmNoNans))
1593 if (getFlag(MachineInstr::FmNoInfs))
1595 if (getFlag(MachineInstr::FmNsz))
1597 if (getFlag(MachineInstr::FmArcp))
1599 if (getFlag(MachineInstr::FmContract))
1601 if (getFlag(MachineInstr::FmAfn))
1603 if (getFlag(MachineInstr::FmReassoc))
1605 if (getFlag(MachineInstr::NoUWrap))
1607 if (getFlag(MachineInstr::NoSWrap))
1609 if (getFlag(MachineInstr::IsExact))
1611 if (getFlag(MachineInstr::NoFPExcept))
1612 OS << "nofpexcept ";
1613 if (getFlag(MachineInstr::NoMerge))
1616 // Print the opcode name.
1618 OS << TII->getName(getOpcode());
1625 // Print the rest of the operands.
1626 bool FirstOp = true;
1627 unsigned AsmDescOp = ~0u;
1628 unsigned AsmOpCount = 0;
1630 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1631 // Print asm string.
1633 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1634 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1635 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1636 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1637 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1640 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1641 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1642 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1643 OS << " [sideeffect]";
1644 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1646 if (ExtraInfo & InlineAsm::Extra_MayStore)
1647 OS << " [maystore]";
1648 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1649 OS << " [isconvergent]";
1650 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1651 OS << " [alignstack]";
1652 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1653 OS << " [attdialect]";
1654 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1655 OS << " [inteldialect]";
1657 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1661 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1662 const MachineOperand &MO = getOperand(i);
1664 if (FirstOp) FirstOp = false; else OS << ",";
1667 if (isDebugValue() && MO.isMetadata()) {
1668 // Pretty print DBG_VALUE instructions.
1669 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1670 if (DIV && !DIV->getName().empty())
1671 OS << "!\"" << DIV->getName() << '\"';
1673 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1674 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1675 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1676 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1678 } else if (isDebugLabel() && MO.isMetadata()) {
1679 // Pretty print DBG_LABEL instructions.
1680 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1681 if (DIL && !DIL->getName().empty())
1682 OS << "\"" << DIL->getName() << '\"';
1684 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1685 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1686 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1687 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1689 } else if (i == AsmDescOp && MO.isImm()) {
1690 // Pretty print the inline asm operand descriptor.
1691 OS << '$' << AsmOpCount++;
1692 unsigned Flag = MO.getImm();
1694 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1697 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1698 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1700 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1702 OS << ":RC" << RCID;
1705 if (InlineAsm::isMemKind(Flag)) {
1706 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1707 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1710 unsigned TiedTo = 0;
1711 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1712 OS << " tiedto:$" << TiedTo;
1716 // Compute the index of the next operand descriptor.
1717 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1719 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1720 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1721 if (MO.isImm() && isOperandSubregIdx(i))
1722 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1724 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1725 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1729 // Print any optional symbols attached to this instruction as-if they were
1731 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1736 OS << " pre-instr-symbol ";
1737 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1739 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1744 OS << " post-instr-symbol ";
1745 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1747 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1752 OS << " heap-alloc-marker ";
1753 HeapAllocMarker->printAsOperand(OS, MST);
1756 if (!SkipDebugLoc) {
1757 if (const DebugLoc &DL = getDebugLoc()) {
1760 OS << " debug-location ";
1761 DL->printAsOperand(OS, MST);
1765 if (!memoperands_empty()) {
1766 SmallVector<StringRef, 0> SSNs;
1767 const LLVMContext *Context = nullptr;
1768 std::unique_ptr<LLVMContext> CtxPtr;
1769 const MachineFrameInfo *MFI = nullptr;
1770 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1771 MFI = &MF->getFrameInfo();
1772 Context = &MF->getFunction().getContext();
1774 CtxPtr = std::make_unique<LLVMContext>();
1775 Context = CtxPtr.get();
1779 bool NeedComma = false;
1780 for (const MachineMemOperand *Op : memoperands()) {
1783 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1791 bool HaveSemi = false;
1793 // Print debug location information.
1794 if (const DebugLoc &DL = getDebugLoc()) {
1803 // Print extra comments for DEBUG_VALUE.
1804 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1809 auto *DV = getDebugVariable();
1810 OS << " line no:" << DV->getLine();
1811 if (isIndirectDebugValue())
1820 bool MachineInstr::addRegisterKilled(Register IncomingReg,
1821 const TargetRegisterInfo *RegInfo,
1822 bool AddIfNotFound) {
1823 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1824 bool hasAliases = isPhysReg &&
1825 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1827 SmallVector<unsigned,4> DeadOps;
1828 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1829 MachineOperand &MO = getOperand(i);
1830 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1833 // DEBUG_VALUE nodes do not contribute to code generation and should
1834 // always be ignored. Failure to do so may result in trying to modify
1835 // KILL flags on DEBUG_VALUE nodes.
1839 Register Reg = MO.getReg();
1843 if (Reg == IncomingReg) {
1846 // The register is already marked kill.
1848 if (isPhysReg && isRegTiedToDefOperand(i))
1849 // Two-address uses of physregs must not be marked kill.
1854 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1855 // A super-register kill already exists.
1856 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1858 if (RegInfo->isSubRegister(IncomingReg, Reg))
1859 DeadOps.push_back(i);
1863 // Trim unneeded kill operands.
1864 while (!DeadOps.empty()) {
1865 unsigned OpIdx = DeadOps.back();
1866 if (getOperand(OpIdx).isImplicit() &&
1867 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1868 RemoveOperand(OpIdx);
1870 getOperand(OpIdx).setIsKill(false);
1874 // If not found, this means an alias of one of the operands is killed. Add a
1875 // new implicit operand if required.
1876 if (!Found && AddIfNotFound) {
1877 addOperand(MachineOperand::CreateReg(IncomingReg,
1886 void MachineInstr::clearRegisterKills(Register Reg,
1887 const TargetRegisterInfo *RegInfo) {
1888 if (!Register::isPhysicalRegister(Reg))
1890 for (MachineOperand &MO : operands()) {
1891 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1893 Register OpReg = MO.getReg();
1894 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1895 MO.setIsKill(false);
1899 bool MachineInstr::addRegisterDead(Register Reg,
1900 const TargetRegisterInfo *RegInfo,
1901 bool AddIfNotFound) {
1902 bool isPhysReg = Register::isPhysicalRegister(Reg);
1903 bool hasAliases = isPhysReg &&
1904 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1906 SmallVector<unsigned,4> DeadOps;
1907 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1908 MachineOperand &MO = getOperand(i);
1909 if (!MO.isReg() || !MO.isDef())
1911 Register MOReg = MO.getReg();
1918 } else if (hasAliases && MO.isDead() &&
1919 Register::isPhysicalRegister(MOReg)) {
1920 // There exists a super-register that's marked dead.
1921 if (RegInfo->isSuperRegister(Reg, MOReg))
1923 if (RegInfo->isSubRegister(Reg, MOReg))
1924 DeadOps.push_back(i);
1928 // Trim unneeded dead operands.
1929 while (!DeadOps.empty()) {
1930 unsigned OpIdx = DeadOps.back();
1931 if (getOperand(OpIdx).isImplicit() &&
1932 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1933 RemoveOperand(OpIdx);
1935 getOperand(OpIdx).setIsDead(false);
1939 // If not found, this means an alias of one of the operands is dead. Add a
1940 // new implicit operand if required.
1941 if (Found || !AddIfNotFound)
1944 addOperand(MachineOperand::CreateReg(Reg,
1952 void MachineInstr::clearRegisterDeads(Register Reg) {
1953 for (MachineOperand &MO : operands()) {
1954 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1956 MO.setIsDead(false);
1960 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
1961 for (MachineOperand &MO : operands()) {
1962 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1964 MO.setIsUndef(IsUndef);
1968 void MachineInstr::addRegisterDefined(Register Reg,
1969 const TargetRegisterInfo *RegInfo) {
1970 if (Register::isPhysicalRegister(Reg)) {
1971 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1975 for (const MachineOperand &MO : operands()) {
1976 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1977 MO.getSubReg() == 0)
1981 addOperand(MachineOperand::CreateReg(Reg,
1986 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1987 const TargetRegisterInfo &TRI) {
1988 bool HasRegMask = false;
1989 for (MachineOperand &MO : operands()) {
1990 if (MO.isRegMask()) {
1994 if (!MO.isReg() || !MO.isDef()) continue;
1995 Register Reg = MO.getReg();
1996 if (!Reg.isPhysical())
1998 // If there are no uses, including partial uses, the def is dead.
1999 if (llvm::none_of(UsedRegs,
2000 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2004 // This is a call with a register mask operand.
2005 // Mask clobbers are always dead, so add defs for the non-dead defines.
2007 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2009 addRegisterDefined(*I, &TRI);
2013 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2014 // Build up a buffer of hash code components.
2015 SmallVector<size_t, 16> HashComponents;
2016 HashComponents.reserve(MI->getNumOperands() + 1);
2017 HashComponents.push_back(MI->getOpcode());
2018 for (const MachineOperand &MO : MI->operands()) {
2019 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2020 continue; // Skip virtual register defs.
2022 HashComponents.push_back(hash_value(MO));
2024 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2027 void MachineInstr::emitError(StringRef Msg) const {
2028 // Find the source location cookie.
2029 unsigned LocCookie = 0;
2030 const MDNode *LocMD = nullptr;
2031 for (unsigned i = getNumOperands(); i != 0; --i) {
2032 if (getOperand(i-1).isMetadata() &&
2033 (LocMD = getOperand(i-1).getMetadata()) &&
2034 LocMD->getNumOperands() != 0) {
2035 if (const ConstantInt *CI =
2036 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2037 LocCookie = CI->getZExtValue();
2043 if (const MachineBasicBlock *MBB = getParent())
2044 if (const MachineFunction *MF = MBB->getParent())
2045 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2046 report_fatal_error(Msg);
2049 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2050 const MCInstrDesc &MCID, bool IsIndirect,
2051 Register Reg, const MDNode *Variable,
2052 const MDNode *Expr) {
2053 assert(isa<DILocalVariable>(Variable) && "not a variable");
2054 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2055 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2056 "Expected inlined-at fields to agree");
2057 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2061 MIB.addReg(0U, RegState::Debug);
2062 return MIB.addMetadata(Variable).addMetadata(Expr);
2065 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2066 const MCInstrDesc &MCID, bool IsIndirect,
2067 MachineOperand &MO, const MDNode *Variable,
2068 const MDNode *Expr) {
2069 assert(isa<DILocalVariable>(Variable) && "not a variable");
2070 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2071 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2072 "Expected inlined-at fields to agree");
2074 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2076 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2080 MIB.addReg(0U, RegState::Debug);
2081 return MIB.addMetadata(Variable).addMetadata(Expr);
2084 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2085 MachineBasicBlock::iterator I,
2086 const DebugLoc &DL, const MCInstrDesc &MCID,
2087 bool IsIndirect, Register Reg,
2088 const MDNode *Variable, const MDNode *Expr) {
2089 MachineFunction &MF = *BB.getParent();
2090 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2092 return MachineInstrBuilder(MF, MI);
2095 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2096 MachineBasicBlock::iterator I,
2097 const DebugLoc &DL, const MCInstrDesc &MCID,
2098 bool IsIndirect, MachineOperand &MO,
2099 const MDNode *Variable, const MDNode *Expr) {
2100 MachineFunction &MF = *BB.getParent();
2101 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2103 return MachineInstrBuilder(MF, *MI);
2106 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2107 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2108 static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2109 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2110 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2111 "Expected inlined-at fields to agree");
2113 const DIExpression *Expr = MI.getDebugExpression();
2114 if (MI.isIndirectDebugValue()) {
2115 assert(MI.getDebugOffset().getImm() == 0 &&
2116 "DBG_VALUE with nonzero offset");
2117 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2122 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2123 MachineBasicBlock::iterator I,
2124 const MachineInstr &Orig,
2126 const DIExpression *Expr = computeExprForSpill(Orig);
2127 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2128 .addFrameIndex(FrameIndex)
2130 .addMetadata(Orig.getDebugVariable())
2134 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2135 const DIExpression *Expr = computeExprForSpill(Orig);
2136 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
2137 Orig.getDebugOffset().ChangeToImmediate(0U);
2138 Orig.getDebugExpressionOp().setMetadata(Expr);
2141 void MachineInstr::collectDebugValues(
2142 SmallVectorImpl<MachineInstr *> &DbgValues) {
2143 MachineInstr &MI = *this;
2144 if (!MI.getOperand(0).isReg())
2147 MachineBasicBlock::iterator DI = MI; ++DI;
2148 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2150 if (!DI->isDebugValue())
2152 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
2153 DbgValues.push_back(&*DI);
2157 void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2158 // Collect matching debug values.
2159 SmallVector<MachineInstr *, 2> DbgValues;
2161 if (!getOperand(0).isReg())
2164 Register DefReg = getOperand(0).getReg();
2165 auto *MRI = getRegInfo();
2166 for (auto &MO : MRI->use_operands(DefReg)) {
2167 auto *DI = MO.getParent();
2168 if (!DI->isDebugValue())
2170 if (DI->getDebugOperandForReg(DefReg)) {
2171 DbgValues.push_back(DI);
2175 // Propagate Reg to debug value instructions.
2176 for (auto *DBI : DbgValues)
2177 DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
2180 using MMOList = SmallVector<const MachineMemOperand *, 2>;
2182 static unsigned getSpillSlotSize(const MMOList &Accesses,
2183 const MachineFrameInfo &MFI) {
2185 for (auto A : Accesses)
2186 if (MFI.isSpillSlotObjectIndex(
2187 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2189 Size += A->getSize();
2194 MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2196 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2197 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2198 if (MFI.isSpillSlotObjectIndex(FI))
2199 return (*memoperands_begin())->getSize();
2205 MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2207 if (TII->hasStoreToStackSlot(*this, Accesses))
2208 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2213 MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2215 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2216 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2217 if (MFI.isSpillSlotObjectIndex(FI))
2218 return (*memoperands_begin())->getSize();
2224 MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2226 if (TII->hasLoadFromStackSlot(*this, Accesses))
2227 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());