1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Methods common to all machine instructions.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Analysis/MemoryLocation.h"
26 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/Config/llvm-config.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfoMetadata.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/DerivedTypes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Metadata.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/ModuleSlotTracker.h"
53 #include "llvm/IR/Operator.h"
54 #include "llvm/IR/Type.h"
55 #include "llvm/IR/Value.h"
56 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/MC/MCRegisterInfo.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/Casting.h"
60 #include "llvm/Support/CommandLine.h"
61 #include "llvm/Support/Compiler.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Support/LowLevelTypeImpl.h"
65 #include "llvm/Support/MathExtras.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetIntrinsicInfo.h"
68 #include "llvm/Target/TargetMachine.h"
79 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
80 if (const MachineBasicBlock *MBB = MI.getParent())
81 if (const MachineFunction *MF = MBB->getParent())
86 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
88 static void tryToGetTargetInfo(const MachineInstr &MI,
89 const TargetRegisterInfo *&TRI,
90 const MachineRegisterInfo *&MRI,
91 const TargetIntrinsicInfo *&IntrinsicInfo,
92 const TargetInstrInfo *&TII) {
94 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95 TRI = MF->getSubtarget().getRegisterInfo();
96 MRI = &MF->getRegInfo();
97 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98 TII = MF->getSubtarget().getInstrInfo();
102 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
103 if (MCID->ImplicitDefs)
104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107 if (MCID->ImplicitUses)
108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114 /// implicit operands. It reserves space for the number of operands specified by
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117 DebugLoc dl, bool NoImp)
118 : MCID(&tid), debugLoc(std::move(dl)) {
119 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
121 // Reserve space for the expected number of operands.
122 if (unsigned NumOps = MCID->getNumOperands() +
123 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124 CapOperands = OperandCapacity::get(NumOps);
125 Operands = MF.allocateOperandArray(CapOperands);
129 addImplicitDefUseOperands(MF);
132 /// MachineInstr ctor - Copies MachineInstr arg exactly
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
138 CapOperands = OperandCapacity::get(MI.getNumOperands());
139 Operands = MF.allocateOperandArray(CapOperands);
142 for (const MachineOperand &MO : MI.operands())
145 // Copy all the sensible flags.
149 /// getRegInfo - If this instruction is embedded into a MachineFunction,
150 /// return the MachineRegisterInfo object for the current function, otherwise
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
153 if (MachineBasicBlock *MBB = getParent())
154 return &MBB->getParent()->getRegInfo();
158 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159 /// this instruction from their respective use lists. This requires that the
160 /// operands already be on their use lists.
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162 for (MachineOperand &MO : operands())
164 MRI.removeRegOperandFromUseList(&MO);
167 /// AddRegOperandsToUseLists - Add all of the register operands in
168 /// this instruction from their respective use lists. This requires that the
169 /// operands not be on their use lists yet.
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171 for (MachineOperand &MO : operands())
173 MRI.addRegOperandToUseList(&MO);
176 void MachineInstr::addOperand(const MachineOperand &Op) {
177 MachineBasicBlock *MBB = getParent();
178 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
179 MachineFunction *MF = MBB->getParent();
180 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
184 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185 /// ranges. If MRI is non-null also update use-def chains.
186 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
187 unsigned NumOps, MachineRegisterInfo *MRI) {
189 return MRI->moveOperands(Dst, Src, NumOps);
191 // MachineOperand is a trivially copyable type so we can just use memmove.
192 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
195 /// addOperand - Add the specified operand to the instruction. If it is an
196 /// implicit operand, it is added to the end of the operand list. If it is
197 /// an explicit operand it is added at the end of the explicit operand list
198 /// (before the first implicit operand).
199 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
200 assert(MCID && "Cannot add operands before providing an instr descriptor");
202 // Check if we're adding one of our existing operands.
203 if (&Op >= Operands && &Op < Operands + NumOperands) {
204 // This is unusual: MI->addOperand(MI->getOperand(i)).
205 // If adding Op requires reallocating or moving existing operands around,
206 // the Op reference could go stale. Support it by copying Op.
207 MachineOperand CopyOp(Op);
208 return addOperand(MF, CopyOp);
211 // Find the insert location for the new operand. Implicit registers go at
212 // the end, everything else goes before the implicit regs.
214 // FIXME: Allow mixed explicit and implicit operands on inline asm.
215 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216 // implicit-defs, but they must not be moved around. See the FIXME in
218 unsigned OpNo = getNumOperands();
219 bool isImpReg = Op.isReg() && Op.isImplicit();
220 if (!isImpReg && !isInlineAsm()) {
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
223 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
228 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
229 Op.getType() == MachineOperand::MO_MCSymbol;
230 // OpNo now points as the desired insertion point. Unless this is a variadic
231 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
232 // RegMask operands go between the explicit and implicit operands.
233 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
234 OpNo < MCID->getNumOperands() || isDebugOp) &&
235 "Trying to add an operand to a machine instr that is already done!");
238 MachineRegisterInfo *MRI = getRegInfo();
240 // Determine if the Operands array needs to be reallocated.
241 // Save the old capacity and operand array.
242 OperandCapacity OldCap = CapOperands;
243 MachineOperand *OldOperands = Operands;
244 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
245 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
246 Operands = MF.allocateOperandArray(CapOperands);
247 // Move the operands before the insertion point.
249 moveOperands(Operands, OldOperands, OpNo, MRI);
252 // Move the operands following the insertion point.
253 if (OpNo != NumOperands)
254 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
258 // Deallocate the old operand array.
259 if (OldOperands != Operands && OldOperands)
260 MF.deallocateOperandArray(OldCap, OldOperands);
262 // Copy Op into place. It still needs to be inserted into the MRI use lists.
263 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
264 NewMO->ParentMI = this;
266 // When adding a register operand, tell MRI about it.
267 if (NewMO->isReg()) {
268 // Ensure isOnRegUseList() returns false, regardless of Op's status.
269 NewMO->Contents.Reg.Prev = nullptr;
270 // Ignore existing ties. This is not a property that can be copied.
272 // Add the new operand to MRI, but only for instructions in an MBB.
274 MRI->addRegOperandToUseList(NewMO);
275 // The MCID operand information isn't accurate until we start adding
276 // explicit operands. The implicit operands are added first, then the
277 // explicits are inserted before them.
279 // Tie uses to defs as indicated in MCInstrDesc.
280 if (NewMO->isUse()) {
281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
283 tieOperands(DefIdx, OpNo);
285 // If the register operand is flagged as early, mark the operand as such.
286 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
287 NewMO->setIsEarlyClobber(true);
292 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
293 /// fewer operand than it started with.
295 void MachineInstr::RemoveOperand(unsigned OpNo) {
296 assert(OpNo < getNumOperands() && "Invalid operand number");
297 untieRegOperand(OpNo);
300 // Moving tied operands would break the ties.
301 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
302 if (Operands[i].isReg())
303 assert(!Operands[i].isTied() && "Cannot move tied operands");
306 MachineRegisterInfo *MRI = getRegInfo();
307 if (MRI && Operands[OpNo].isReg())
308 MRI->removeRegOperandFromUseList(Operands + OpNo);
310 // Don't call the MachineOperand destructor. A lot of this code depends on
311 // MachineOperand having a trivial destructor anyway, and adding a call here
312 // wouldn't make it 'destructor-correct'.
314 if (unsigned N = NumOperands - 1 - OpNo)
315 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
319 void MachineInstr::dropMemRefs(MachineFunction &MF) {
320 if (memoperands_empty())
323 // See if we can just drop all of our extra info.
324 if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
328 if (!getPostInstrSymbol()) {
329 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
332 if (!getPreInstrSymbol()) {
333 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
337 // Otherwise allocate a fresh extra info with just these symbols.
338 Info.set<EIIK_OutOfLine>(
339 MF.createMIExtraInfo({}, getPreInstrSymbol(), getPostInstrSymbol()));
342 void MachineInstr::setMemRefs(MachineFunction &MF,
343 ArrayRef<MachineMemOperand *> MMOs) {
349 // Try to store a single MMO inline.
350 if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
351 Info.set<EIIK_MMO>(MMOs[0]);
355 // Otherwise create an extra info struct with all of our info.
356 Info.set<EIIK_OutOfLine>(
357 MF.createMIExtraInfo(MMOs, getPreInstrSymbol(), getPostInstrSymbol()));
360 void MachineInstr::addMemOperand(MachineFunction &MF,
361 MachineMemOperand *MO) {
362 SmallVector<MachineMemOperand *, 2> MMOs;
363 MMOs.append(memoperands_begin(), memoperands_end());
365 setMemRefs(MF, MMOs);
368 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
370 // Nothing to do for a self-clone!
373 assert(&MF == MI.getMF() &&
374 "Invalid machine functions when cloning memory refrences!");
375 // See if we can just steal the extra info already allocated for the
376 // instruction. We can do this whenever the pre- and post-instruction symbols
377 // are the same (including null).
378 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
379 getPostInstrSymbol() == MI.getPostInstrSymbol()) {
384 // Otherwise, fall back on a copy-based clone.
385 setMemRefs(MF, MI.memoperands());
388 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
390 static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
391 ArrayRef<MachineMemOperand *> RHS) {
392 if (LHS.size() != RHS.size())
395 auto LHSPointees = make_pointee_range(LHS);
396 auto RHSPointees = make_pointee_range(RHS);
397 return std::equal(LHSPointees.begin(), LHSPointees.end(),
398 RHSPointees.begin());
401 void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
402 ArrayRef<const MachineInstr *> MIs) {
403 // Try handling easy numbers of MIs with simpler mechanisms.
408 if (MIs.size() == 1) {
409 cloneMemRefs(MF, *MIs[0]);
412 // Because an empty memoperands list provides *no* information and must be
413 // handled conservatively (assuming the instruction can do anything), the only
414 // way to merge with it is to drop all other memoperands.
415 if (MIs[0]->memoperands_empty()) {
420 // Handle the general case.
421 SmallVector<MachineMemOperand *, 2> MergedMMOs;
422 // Start with the first instruction.
423 assert(&MF == MIs[0]->getMF() &&
424 "Invalid machine functions when cloning memory references!");
425 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
426 // Now walk all the other instructions and accumulate any different MMOs.
427 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
428 assert(&MF == MI.getMF() &&
429 "Invalid machine functions when cloning memory references!");
431 // Skip MIs with identical operands to the first. This is a somewhat
432 // arbitrary hack but will catch common cases without being quadratic.
433 // TODO: We could fully implement merge semantics here if needed.
434 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
437 // Because an empty memoperands list provides *no* information and must be
438 // handled conservatively (assuming the instruction can do anything), the
439 // only way to merge with it is to drop all other memoperands.
440 if (MI.memoperands_empty()) {
445 // Otherwise accumulate these into our temporary buffer of the merged state.
446 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
449 setMemRefs(MF, MergedMMOs);
452 void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
453 MCSymbol *OldSymbol = getPreInstrSymbol();
454 if (OldSymbol == Symbol)
456 if (OldSymbol && !Symbol) {
457 // We're removing a symbol rather than adding one. Try to clean up any
458 // extra info carried around.
459 if (Info.is<EIIK_PreInstrSymbol>()) {
464 if (memoperands_empty()) {
465 assert(getPostInstrSymbol() &&
466 "Should never have only a single symbol allocated out-of-line!");
467 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
471 // Otherwise fallback on the generic update.
472 } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
473 // If we don't have any other extra info, we can store this inline.
474 Info.set<EIIK_PreInstrSymbol>(Symbol);
478 // Otherwise, allocate a full new set of extra info.
479 // FIXME: Maybe we should make the symbols in the extra info mutable?
480 Info.set<EIIK_OutOfLine>(
481 MF.createMIExtraInfo(memoperands(), Symbol, getPostInstrSymbol()));
484 void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
485 MCSymbol *OldSymbol = getPostInstrSymbol();
486 if (OldSymbol == Symbol)
488 if (OldSymbol && !Symbol) {
489 // We're removing a symbol rather than adding one. Try to clean up any
490 // extra info carried around.
491 if (Info.is<EIIK_PostInstrSymbol>()) {
496 if (memoperands_empty()) {
497 assert(getPreInstrSymbol() &&
498 "Should never have only a single symbol allocated out-of-line!");
499 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
503 // Otherwise fallback on the generic update.
504 } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
505 // If we don't have any other extra info, we can store this inline.
506 Info.set<EIIK_PostInstrSymbol>(Symbol);
510 // Otherwise, allocate a full new set of extra info.
511 // FIXME: Maybe we should make the symbols in the extra info mutable?
512 Info.set<EIIK_OutOfLine>(
513 MF.createMIExtraInfo(memoperands(), getPreInstrSymbol(), Symbol));
516 void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
517 const MachineInstr &MI) {
519 // Nothing to do for a self-clone!
522 assert(&MF == MI.getMF() &&
523 "Invalid machine functions when cloning instruction symbols!");
525 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
526 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
529 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
530 // For now, the just return the union of the flags. If the flags get more
531 // complicated over time, we might need more logic here.
532 return getFlags() | Other.getFlags();
535 uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
536 uint16_t MIFlags = 0;
537 // Copy the wrapping flags.
538 if (const OverflowingBinaryOperator *OB =
539 dyn_cast<OverflowingBinaryOperator>(&I)) {
540 if (OB->hasNoSignedWrap())
541 MIFlags |= MachineInstr::MIFlag::NoSWrap;
542 if (OB->hasNoUnsignedWrap())
543 MIFlags |= MachineInstr::MIFlag::NoUWrap;
546 // Copy the exact flag.
547 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
549 MIFlags |= MachineInstr::MIFlag::IsExact;
551 // Copy the fast-math flags.
552 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
553 const FastMathFlags Flags = FP->getFastMathFlags();
555 MIFlags |= MachineInstr::MIFlag::FmNoNans;
557 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
558 if (Flags.noSignedZeros())
559 MIFlags |= MachineInstr::MIFlag::FmNsz;
560 if (Flags.allowReciprocal())
561 MIFlags |= MachineInstr::MIFlag::FmArcp;
562 if (Flags.allowContract())
563 MIFlags |= MachineInstr::MIFlag::FmContract;
564 if (Flags.approxFunc())
565 MIFlags |= MachineInstr::MIFlag::FmAfn;
566 if (Flags.allowReassoc())
567 MIFlags |= MachineInstr::MIFlag::FmReassoc;
573 void MachineInstr::copyIRFlags(const Instruction &I) {
574 Flags = copyFlagsFromInstruction(I);
577 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
578 assert(!isBundledWithPred() && "Must be called on bundle header");
579 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
580 if (MII->getDesc().getFlags() & Mask) {
581 if (Type == AnyInBundle)
584 if (Type == AllInBundle && !MII->isBundle())
587 // This was the last instruction in the bundle.
588 if (!MII->isBundledWithSucc())
589 return Type == AllInBundle;
593 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
594 MICheckType Check) const {
595 // If opcodes or number of operands are not the same then the two
596 // instructions are obviously not identical.
597 if (Other.getOpcode() != getOpcode() ||
598 Other.getNumOperands() != getNumOperands())
602 // We have passed the test above that both instructions have the same
603 // opcode, so we know that both instructions are bundles here. Let's compare
604 // MIs inside the bundle.
605 assert(Other.isBundle() && "Expected that both instructions are bundles.");
606 MachineBasicBlock::const_instr_iterator I1 = getIterator();
607 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
608 // Loop until we analysed the last intruction inside at least one of the
610 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
613 if (!I1->isIdenticalTo(*I2, Check))
616 // If we've reached the end of just one of the two bundles, but not both,
617 // the instructions are not identical.
618 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
622 // Check operands to make sure they match.
623 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
624 const MachineOperand &MO = getOperand(i);
625 const MachineOperand &OMO = Other.getOperand(i);
627 if (!MO.isIdenticalTo(OMO))
632 // Clients may or may not want to ignore defs when testing for equality.
633 // For example, machine CSE pass only cares about finding common
634 // subexpressions, so it's safe to ignore virtual register defs.
636 if (Check == IgnoreDefs)
638 else if (Check == IgnoreVRegDefs) {
639 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
640 !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
641 if (!MO.isIdenticalTo(OMO))
644 if (!MO.isIdenticalTo(OMO))
646 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
650 if (!MO.isIdenticalTo(OMO))
652 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
656 // If DebugLoc does not match then two debug instructions are not identical.
658 if (getDebugLoc() && Other.getDebugLoc() &&
659 getDebugLoc() != Other.getDebugLoc())
664 const MachineFunction *MachineInstr::getMF() const {
665 return getParent()->getParent();
668 MachineInstr *MachineInstr::removeFromParent() {
669 assert(getParent() && "Not embedded in a basic block!");
670 return getParent()->remove(this);
673 MachineInstr *MachineInstr::removeFromBundle() {
674 assert(getParent() && "Not embedded in a basic block!");
675 return getParent()->remove_instr(this);
678 void MachineInstr::eraseFromParent() {
679 assert(getParent() && "Not embedded in a basic block!");
680 getParent()->erase(this);
683 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
684 assert(getParent() && "Not embedded in a basic block!");
685 MachineBasicBlock *MBB = getParent();
686 MachineFunction *MF = MBB->getParent();
687 assert(MF && "Not embedded in a function!");
689 MachineInstr *MI = (MachineInstr *)this;
690 MachineRegisterInfo &MRI = MF->getRegInfo();
692 for (const MachineOperand &MO : MI->operands()) {
693 if (!MO.isReg() || !MO.isDef())
695 unsigned Reg = MO.getReg();
696 if (!TargetRegisterInfo::isVirtualRegister(Reg))
698 MRI.markUsesInDebugValueAsUndef(Reg);
700 MI->eraseFromParent();
703 void MachineInstr::eraseFromBundle() {
704 assert(getParent() && "Not embedded in a basic block!");
705 getParent()->erase_instr(this);
708 unsigned MachineInstr::getNumExplicitOperands() const {
709 unsigned NumOperands = MCID->getNumOperands();
710 if (!MCID->isVariadic())
713 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
714 const MachineOperand &MO = getOperand(I);
715 // The operands must always be in the following order:
716 // - explicit reg defs,
717 // - other explicit operands (reg uses, immediates, etc.),
718 // - implicit reg defs
719 // - implicit reg uses
720 if (MO.isReg() && MO.isImplicit())
727 unsigned MachineInstr::getNumExplicitDefs() const {
728 unsigned NumDefs = MCID->getNumDefs();
729 if (!MCID->isVariadic())
732 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
733 const MachineOperand &MO = getOperand(I);
734 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
741 void MachineInstr::bundleWithPred() {
742 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
743 setFlag(BundledPred);
744 MachineBasicBlock::instr_iterator Pred = getIterator();
746 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
747 Pred->setFlag(BundledSucc);
750 void MachineInstr::bundleWithSucc() {
751 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
752 setFlag(BundledSucc);
753 MachineBasicBlock::instr_iterator Succ = getIterator();
755 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
756 Succ->setFlag(BundledPred);
759 void MachineInstr::unbundleFromPred() {
760 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
761 clearFlag(BundledPred);
762 MachineBasicBlock::instr_iterator Pred = getIterator();
764 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
765 Pred->clearFlag(BundledSucc);
768 void MachineInstr::unbundleFromSucc() {
769 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
770 clearFlag(BundledSucc);
771 MachineBasicBlock::instr_iterator Succ = getIterator();
773 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
774 Succ->clearFlag(BundledPred);
777 bool MachineInstr::isStackAligningInlineAsm() const {
779 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
780 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
786 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
787 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
788 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
789 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
792 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
793 unsigned *GroupNo) const {
794 assert(isInlineAsm() && "Expected an inline asm instruction");
795 assert(OpIdx < getNumOperands() && "OpIdx out of range");
797 // Ignore queries about the initial operands.
798 if (OpIdx < InlineAsm::MIOp_FirstOperand)
803 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
805 const MachineOperand &FlagMO = getOperand(i);
806 // If we reach the implicit register operands, stop looking.
809 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
810 if (i + NumOps > OpIdx) {
820 const DILabel *MachineInstr::getDebugLabel() const {
821 assert(isDebugLabel() && "not a DBG_LABEL");
822 return cast<DILabel>(getOperand(0).getMetadata());
825 const DILocalVariable *MachineInstr::getDebugVariable() const {
826 assert(isDebugValue() && "not a DBG_VALUE");
827 return cast<DILocalVariable>(getOperand(2).getMetadata());
830 const DIExpression *MachineInstr::getDebugExpression() const {
831 assert(isDebugValue() && "not a DBG_VALUE");
832 return cast<DIExpression>(getOperand(3).getMetadata());
835 const TargetRegisterClass*
836 MachineInstr::getRegClassConstraint(unsigned OpIdx,
837 const TargetInstrInfo *TII,
838 const TargetRegisterInfo *TRI) const {
839 assert(getParent() && "Can't have an MBB reference here!");
840 assert(getMF() && "Can't have an MF reference here!");
841 const MachineFunction &MF = *getMF();
843 // Most opcodes have fixed constraints in their MCInstrDesc.
845 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
847 if (!getOperand(OpIdx).isReg())
850 // For tied uses on inline asm, get the constraint from the def.
852 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
855 // Inline asm stores register class constraints in the flag word.
856 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
860 unsigned Flag = getOperand(FlagIdx).getImm();
862 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
863 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
864 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
865 InlineAsm::hasRegClassConstraint(Flag, RCID))
866 return TRI->getRegClass(RCID);
868 // Assume that all registers in a memory operand are pointers.
869 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
870 return TRI->getPointerRegClass(MF);
875 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
876 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
877 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
878 // Check every operands inside the bundle if we have
881 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
883 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
884 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
886 // Otherwise, just check the current operands.
887 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
888 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
892 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
893 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
894 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
895 assert(CurRC && "Invalid initial register class");
896 // Check if Reg is constrained by some of its use/def from MI.
897 const MachineOperand &MO = getOperand(OpIdx);
898 if (!MO.isReg() || MO.getReg() != Reg)
900 // If yes, accumulate the constraints through the operand.
901 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
904 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
905 unsigned OpIdx, const TargetRegisterClass *CurRC,
906 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
907 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
908 const MachineOperand &MO = getOperand(OpIdx);
910 "Cannot get register constraints for non-register operand");
911 assert(CurRC && "Invalid initial register class");
912 if (unsigned SubIdx = MO.getSubReg()) {
914 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
916 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
918 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
922 /// Return the number of instructions inside the MI bundle, not counting the
923 /// header instruction.
924 unsigned MachineInstr::getBundleSize() const {
925 MachineBasicBlock::const_instr_iterator I = getIterator();
927 while (I->isBundledWithSucc()) {
934 /// Returns true if the MachineInstr has an implicit-use operand of exactly
935 /// the given register (not considering sub/super-registers).
936 bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
937 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
938 const MachineOperand &MO = getOperand(i);
939 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
945 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
946 /// the specific register or -1 if it is not found. It further tightens
947 /// the search criteria to a use that kills the register if isKill is true.
948 int MachineInstr::findRegisterUseOperandIdx(
949 unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
950 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
951 const MachineOperand &MO = getOperand(i);
952 if (!MO.isReg() || !MO.isUse())
954 unsigned MOReg = MO.getReg();
957 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
958 if (!isKill || MO.isKill())
964 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
965 /// indicating if this instruction reads or writes Reg. This also considers
968 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
969 SmallVectorImpl<unsigned> *Ops) const {
970 bool PartDef = false; // Partial redefine.
971 bool FullDef = false; // Full define.
974 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
975 const MachineOperand &MO = getOperand(i);
976 if (!MO.isReg() || MO.getReg() != Reg)
981 Use |= !MO.isUndef();
982 else if (MO.getSubReg() && !MO.isUndef())
983 // A partial def undef doesn't count as reading the register.
988 // A partial redefine uses Reg unless there is also a full define.
989 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
992 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
993 /// the specified register or -1 if it is not found. If isDead is true, defs
994 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
995 /// also checks if there is a def of a super-register.
997 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
998 const TargetRegisterInfo *TRI) const {
999 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1000 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1001 const MachineOperand &MO = getOperand(i);
1002 // Accept regmask operands when Overlap is set.
1003 // Ignore them when looking for a specific def operand (Overlap == false).
1004 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1006 if (!MO.isReg() || !MO.isDef())
1008 unsigned MOReg = MO.getReg();
1009 bool Found = (MOReg == Reg);
1010 if (!Found && TRI && isPhys &&
1011 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1013 Found = TRI->regsOverlap(MOReg, Reg);
1015 Found = TRI->isSubRegister(MOReg, Reg);
1017 if (Found && (!isDead || MO.isDead()))
1023 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1024 /// operand list that is used to represent the predicate. It returns -1 if
1026 int MachineInstr::findFirstPredOperandIdx() const {
1027 // Don't call MCID.findFirstPredOperandIdx() because this variant
1028 // is sometimes called on an instruction that's not yet complete, and
1029 // so the number of operands is less than the MCID indicates. In
1030 // particular, the PTX target does this.
1031 const MCInstrDesc &MCID = getDesc();
1032 if (MCID.isPredicable()) {
1033 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1034 if (MCID.OpInfo[i].isPredicate())
1041 // MachineOperand::TiedTo is 4 bits wide.
1042 const unsigned TiedMax = 15;
1044 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1046 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1047 /// field. TiedTo can have these values:
1049 /// 0: Operand is not tied to anything.
1050 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1051 /// TiedMax: Tied to an operand >= TiedMax-1.
1053 /// The tied def must be one of the first TiedMax operands on a normal
1054 /// instruction. INLINEASM instructions allow more tied defs.
1056 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1057 MachineOperand &DefMO = getOperand(DefIdx);
1058 MachineOperand &UseMO = getOperand(UseIdx);
1059 assert(DefMO.isDef() && "DefIdx must be a def operand");
1060 assert(UseMO.isUse() && "UseIdx must be a use operand");
1061 assert(!DefMO.isTied() && "Def is already tied to another use");
1062 assert(!UseMO.isTied() && "Use is already tied to another def");
1064 if (DefIdx < TiedMax)
1065 UseMO.TiedTo = DefIdx + 1;
1067 // Inline asm can use the group descriptors to find tied operands, but on
1068 // normal instruction, the tied def must be within the first TiedMax
1070 assert(isInlineAsm() && "DefIdx out of range");
1071 UseMO.TiedTo = TiedMax;
1074 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1075 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1078 /// Given the index of a tied register operand, find the operand it is tied to.
1079 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1080 /// which must exist.
1081 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1082 const MachineOperand &MO = getOperand(OpIdx);
1083 assert(MO.isTied() && "Operand isn't tied");
1085 // Normally TiedTo is in range.
1086 if (MO.TiedTo < TiedMax)
1087 return MO.TiedTo - 1;
1089 // Uses on normal instructions can be out of range.
1090 if (!isInlineAsm()) {
1091 // Normal tied defs must be in the 0..TiedMax-1 range.
1094 // MO is a def. Search for the tied use.
1095 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1096 const MachineOperand &UseMO = getOperand(i);
1097 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1100 llvm_unreachable("Can't find tied use");
1103 // Now deal with inline asm by parsing the operand group descriptor flags.
1104 // Find the beginning of each operand group.
1105 SmallVector<unsigned, 8> GroupIdx;
1106 unsigned OpIdxGroup = ~0u;
1108 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1110 const MachineOperand &FlagMO = getOperand(i);
1111 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1112 unsigned CurGroup = GroupIdx.size();
1113 GroupIdx.push_back(i);
1114 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1115 // OpIdx belongs to this operand group.
1116 if (OpIdx > i && OpIdx < i + NumOps)
1117 OpIdxGroup = CurGroup;
1119 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1121 // Operands in this group are tied to operands in TiedGroup which must be
1122 // earlier. Find the number of operands between the two groups.
1123 unsigned Delta = i - GroupIdx[TiedGroup];
1125 // OpIdx is a use tied to TiedGroup.
1126 if (OpIdxGroup == CurGroup)
1127 return OpIdx - Delta;
1129 // OpIdx is a def tied to this use group.
1130 if (OpIdxGroup == TiedGroup)
1131 return OpIdx + Delta;
1133 llvm_unreachable("Invalid tied operand on inline asm");
1136 /// clearKillInfo - Clears kill flags on all operands.
1138 void MachineInstr::clearKillInfo() {
1139 for (MachineOperand &MO : operands()) {
1140 if (MO.isReg() && MO.isUse())
1141 MO.setIsKill(false);
1145 void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1147 const TargetRegisterInfo &RegInfo) {
1148 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1150 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1151 for (MachineOperand &MO : operands()) {
1152 if (!MO.isReg() || MO.getReg() != FromReg)
1154 MO.substPhysReg(ToReg, RegInfo);
1157 for (MachineOperand &MO : operands()) {
1158 if (!MO.isReg() || MO.getReg() != FromReg)
1160 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1165 /// isSafeToMove - Return true if it is safe to move this instruction. If
1166 /// SawStore is set to true, it means that there is a store (or call) between
1167 /// the instruction's location and its intended destination.
1168 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1169 // Ignore stuff that we obviously can't move.
1171 // Treat volatile loads as stores. This is not strictly necessary for
1172 // volatiles, but it is required for atomic loads. It is not allowed to move
1173 // a load across an atomic load with Ordering > Monotonic.
1174 if (mayStore() || isCall() || isPHI() ||
1175 (mayLoad() && hasOrderedMemoryRef())) {
1180 if (isPosition() || isDebugInstr() || isTerminator() ||
1181 mayRaiseFPException() || hasUnmodeledSideEffects())
1184 // See if this instruction does a load. If so, we have to guarantee that the
1185 // loaded value doesn't change between the load and the its intended
1186 // destination. The check for isInvariantLoad gives the targe the chance to
1187 // classify the load as always returning a constant, e.g. a constant pool
1189 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1190 // Otherwise, this is a real load. If there is a store between the load and
1191 // end of block, we can't move it.
1197 bool MachineInstr::mayAlias(AliasAnalysis *AA, const MachineInstr &Other,
1198 bool UseTBAA) const {
1199 const MachineFunction *MF = getMF();
1200 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1201 const MachineFrameInfo &MFI = MF->getFrameInfo();
1203 // If neither instruction stores to memory, they can't alias in any
1204 // meaningful way, even if they read from the same address.
1205 if (!mayStore() && !Other.mayStore())
1208 // Let the target decide if memory accesses cannot possibly overlap.
1209 if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1212 // FIXME: Need to handle multiple memory operands to support all targets.
1213 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1216 MachineMemOperand *MMOa = *memoperands_begin();
1217 MachineMemOperand *MMOb = *Other.memoperands_begin();
1219 // The following interface to AA is fashioned after DAGCombiner::isAlias
1220 // and operates with MachineMemOperand offset with some important
1222 // - LLVM fundamentally assumes flat address spaces.
1223 // - MachineOperand offset can *only* result from legalization and
1224 // cannot affect queries other than the trivial case of overlap
1226 // - These offsets never wrap and never step outside
1227 // of allocated objects.
1228 // - There should never be any negative offsets here.
1230 // FIXME: Modify API to hide this math from "user"
1231 // Even before we go to AA we can reason locally about some
1232 // memory objects. It can save compile time, and possibly catch some
1233 // corner cases not currently covered.
1235 int64_t OffsetA = MMOa->getOffset();
1236 int64_t OffsetB = MMOb->getOffset();
1237 int64_t MinOffset = std::min(OffsetA, OffsetB);
1239 uint64_t WidthA = MMOa->getSize();
1240 uint64_t WidthB = MMOb->getSize();
1241 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1242 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1244 const Value *ValA = MMOa->getValue();
1245 const Value *ValB = MMOb->getValue();
1246 bool SameVal = (ValA && ValB && (ValA == ValB));
1248 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1249 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1250 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1252 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1254 if (PSVa && PSVb && (PSVa == PSVb))
1259 if (!KnownWidthA || !KnownWidthB)
1261 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1262 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1263 return (MinOffset + LowWidth > MaxOffset);
1272 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1273 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1275 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1276 : MemoryLocation::UnknownSize;
1277 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1278 : MemoryLocation::UnknownSize;
1280 AliasResult AAResult = AA->alias(
1281 MemoryLocation(ValA, OverlapA,
1282 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1283 MemoryLocation(ValB, OverlapB,
1284 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1286 return (AAResult != NoAlias);
1289 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1290 /// or volatile memory reference, or if the information describing the memory
1291 /// reference is not available. Return false if it is known to have no ordered
1292 /// memory references.
1293 bool MachineInstr::hasOrderedMemoryRef() const {
1294 // An instruction known never to access memory won't have a volatile access.
1298 !hasUnmodeledSideEffects())
1301 // Otherwise, if the instruction has no memory reference information,
1302 // conservatively assume it wasn't preserved.
1303 if (memoperands_empty())
1306 // Check if any of our memory operands are ordered.
1307 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1308 return !MMO->isUnordered();
1312 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1313 /// trap and is loading from a location whose value is invariant across a run of
1315 bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1316 // If the instruction doesn't load at all, it isn't an invariant load.
1320 // If the instruction has lost its memoperands, conservatively assume that
1321 // it may not be an invariant load.
1322 if (memoperands_empty())
1325 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1327 for (MachineMemOperand *MMO : memoperands()) {
1328 if (!MMO->isUnordered())
1329 // If the memory operand has ordering side effects, we can't move the
1330 // instruction. Such an instruction is technically an invariant load,
1331 // but the caller code would need updated to expect that.
1333 if (MMO->isStore()) return false;
1334 if (MMO->isInvariant() && MMO->isDereferenceable())
1337 // A load from a constant PseudoSourceValue is invariant.
1338 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1339 if (PSV->isConstant(&MFI))
1342 if (const Value *V = MMO->getValue()) {
1343 // If we have an AliasAnalysis, ask it whether the memory is constant.
1345 AA->pointsToConstantMemory(
1346 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1350 // Otherwise assume conservatively.
1354 // Everything checks out.
1358 /// isConstantValuePHI - If the specified instruction is a PHI that always
1359 /// merges together the same virtual register, return the register, otherwise
1361 unsigned MachineInstr::isConstantValuePHI() const {
1364 assert(getNumOperands() >= 3 &&
1365 "It's illegal to have a PHI without source operands");
1367 unsigned Reg = getOperand(1).getReg();
1368 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1369 if (getOperand(i).getReg() != Reg)
1374 bool MachineInstr::hasUnmodeledSideEffects() const {
1375 if (hasProperty(MCID::UnmodeledSideEffects))
1377 if (isInlineAsm()) {
1378 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1379 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1386 bool MachineInstr::isLoadFoldBarrier() const {
1387 return mayStore() || isCall() || hasUnmodeledSideEffects();
1390 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1392 bool MachineInstr::allDefsAreDead() const {
1393 for (const MachineOperand &MO : operands()) {
1394 if (!MO.isReg() || MO.isUse())
1402 /// copyImplicitOps - Copy implicit register operands from specified
1403 /// instruction to this instruction.
1404 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1405 const MachineInstr &MI) {
1406 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1408 const MachineOperand &MO = MI.getOperand(i);
1409 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1414 bool MachineInstr::hasComplexRegisterTies() const {
1415 const MCInstrDesc &MCID = getDesc();
1416 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1417 const auto &Operand = getOperand(I);
1418 if (!Operand.isReg() || Operand.isDef())
1419 // Ignore the defined registers as MCID marks only the uses as tied.
1421 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1422 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1423 if (ExpectedTiedIdx != TiedIdx)
1429 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1430 const MachineRegisterInfo &MRI) const {
1431 const MachineOperand &Op = getOperand(OpIdx);
1435 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1436 return MRI.getType(Op.getReg());
1438 auto &OpInfo = getDesc().OpInfo[OpIdx];
1439 if (!OpInfo.isGenericType())
1440 return MRI.getType(Op.getReg());
1442 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1445 LLT TypeToPrint = MRI.getType(Op.getReg());
1446 // Don't mark the type index printed if it wasn't actually printed: maybe
1447 // another operand with the same type index has an actual type attached:
1448 if (TypeToPrint.isValid())
1449 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1453 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1454 LLVM_DUMP_METHOD void MachineInstr::dump() const {
1460 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1461 bool SkipDebugLoc, bool AddNewLine,
1462 const TargetInstrInfo *TII) const {
1463 const Module *M = nullptr;
1464 const Function *F = nullptr;
1465 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1466 F = &MF->getFunction();
1469 TII = MF->getSubtarget().getInstrInfo();
1472 ModuleSlotTracker MST(M);
1474 MST.incorporateFunction(*F);
1475 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1478 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1479 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1480 bool AddNewLine, const TargetInstrInfo *TII) const {
1481 // We can be a bit tidier if we know the MachineFunction.
1482 const MachineFunction *MF = nullptr;
1483 const TargetRegisterInfo *TRI = nullptr;
1484 const MachineRegisterInfo *MRI = nullptr;
1485 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1486 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1488 if (isCFIInstruction())
1489 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1491 SmallBitVector PrintedTypes(8);
1492 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1493 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1494 if (!ShouldPrintRegisterTies)
1496 const MachineOperand &MO = getOperand(OpIdx);
1497 if (MO.isReg() && MO.isTied() && !MO.isDef())
1498 return findTiedOperandIdx(OpIdx);
1501 unsigned StartOp = 0;
1502 unsigned e = getNumOperands();
1504 // Print explicitly defined operands on the left of an assignment syntax.
1505 while (StartOp < e) {
1506 const MachineOperand &MO = getOperand(StartOp);
1507 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1513 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1514 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1515 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1516 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1523 if (getFlag(MachineInstr::FrameSetup))
1524 OS << "frame-setup ";
1525 if (getFlag(MachineInstr::FrameDestroy))
1526 OS << "frame-destroy ";
1527 if (getFlag(MachineInstr::FmNoNans))
1529 if (getFlag(MachineInstr::FmNoInfs))
1531 if (getFlag(MachineInstr::FmNsz))
1533 if (getFlag(MachineInstr::FmArcp))
1535 if (getFlag(MachineInstr::FmContract))
1537 if (getFlag(MachineInstr::FmAfn))
1539 if (getFlag(MachineInstr::FmReassoc))
1541 if (getFlag(MachineInstr::NoUWrap))
1543 if (getFlag(MachineInstr::NoSWrap))
1545 if (getFlag(MachineInstr::IsExact))
1547 if (getFlag(MachineInstr::FPExcept))
1550 // Print the opcode name.
1552 OS << TII->getName(getOpcode());
1559 // Print the rest of the operands.
1560 bool FirstOp = true;
1561 unsigned AsmDescOp = ~0u;
1562 unsigned AsmOpCount = 0;
1564 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1565 // Print asm string.
1567 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1568 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1569 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1570 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1571 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1574 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1575 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1576 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1577 OS << " [sideeffect]";
1578 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1580 if (ExtraInfo & InlineAsm::Extra_MayStore)
1581 OS << " [maystore]";
1582 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1583 OS << " [isconvergent]";
1584 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1585 OS << " [alignstack]";
1586 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1587 OS << " [attdialect]";
1588 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1589 OS << " [inteldialect]";
1591 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1595 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1596 const MachineOperand &MO = getOperand(i);
1598 if (FirstOp) FirstOp = false; else OS << ",";
1601 if (isDebugValue() && MO.isMetadata()) {
1602 // Pretty print DBG_VALUE instructions.
1603 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1604 if (DIV && !DIV->getName().empty())
1605 OS << "!\"" << DIV->getName() << '\"';
1607 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1608 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1609 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1610 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1612 } else if (isDebugLabel() && MO.isMetadata()) {
1613 // Pretty print DBG_LABEL instructions.
1614 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1615 if (DIL && !DIL->getName().empty())
1616 OS << "\"" << DIL->getName() << '\"';
1618 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1619 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1620 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1621 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1623 } else if (i == AsmDescOp && MO.isImm()) {
1624 // Pretty print the inline asm operand descriptor.
1625 OS << '$' << AsmOpCount++;
1626 unsigned Flag = MO.getImm();
1627 switch (InlineAsm::getKind(Flag)) {
1628 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1629 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1630 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1631 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1632 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1633 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1634 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1638 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1639 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1641 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1643 OS << ":RC" << RCID;
1646 if (InlineAsm::isMemKind(Flag)) {
1647 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1649 case InlineAsm::Constraint_es: OS << ":es"; break;
1650 case InlineAsm::Constraint_i: OS << ":i"; break;
1651 case InlineAsm::Constraint_m: OS << ":m"; break;
1652 case InlineAsm::Constraint_o: OS << ":o"; break;
1653 case InlineAsm::Constraint_v: OS << ":v"; break;
1654 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1655 case InlineAsm::Constraint_R: OS << ":R"; break;
1656 case InlineAsm::Constraint_S: OS << ":S"; break;
1657 case InlineAsm::Constraint_T: OS << ":T"; break;
1658 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1659 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1660 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1661 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1662 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1663 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1664 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1665 case InlineAsm::Constraint_X: OS << ":X"; break;
1666 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1667 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1668 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1669 default: OS << ":?"; break;
1673 unsigned TiedTo = 0;
1674 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1675 OS << " tiedto:$" << TiedTo;
1679 // Compute the index of the next operand descriptor.
1680 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1682 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1683 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1684 if (MO.isImm() && isOperandSubregIdx(i))
1685 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1687 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1688 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1692 // Print any optional symbols attached to this instruction as-if they were
1694 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1699 OS << " pre-instr-symbol ";
1700 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1702 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1707 OS << " post-instr-symbol ";
1708 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1711 if (!SkipDebugLoc) {
1712 if (const DebugLoc &DL = getDebugLoc()) {
1715 OS << " debug-location ";
1716 DL->printAsOperand(OS, MST);
1720 if (!memoperands_empty()) {
1721 SmallVector<StringRef, 0> SSNs;
1722 const LLVMContext *Context = nullptr;
1723 std::unique_ptr<LLVMContext> CtxPtr;
1724 const MachineFrameInfo *MFI = nullptr;
1725 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1726 MFI = &MF->getFrameInfo();
1727 Context = &MF->getFunction().getContext();
1729 CtxPtr = llvm::make_unique<LLVMContext>();
1730 Context = CtxPtr.get();
1734 bool NeedComma = false;
1735 for (const MachineMemOperand *Op : memoperands()) {
1738 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1746 bool HaveSemi = false;
1748 // Print debug location information.
1749 if (const DebugLoc &DL = getDebugLoc()) {
1758 // Print extra comments for DEBUG_VALUE.
1759 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1764 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1765 OS << " line no:" << DV->getLine();
1766 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1767 DebugLoc InlinedAtDL(InlinedAt);
1768 if (InlinedAtDL && MF) {
1769 OS << " inlined @[ ";
1770 InlinedAtDL.print(OS);
1774 if (isIndirectDebugValue())
1783 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1784 const TargetRegisterInfo *RegInfo,
1785 bool AddIfNotFound) {
1786 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1787 bool hasAliases = isPhysReg &&
1788 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1790 SmallVector<unsigned,4> DeadOps;
1791 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1792 MachineOperand &MO = getOperand(i);
1793 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1796 // DEBUG_VALUE nodes do not contribute to code generation and should
1797 // always be ignored. Failure to do so may result in trying to modify
1798 // KILL flags on DEBUG_VALUE nodes.
1802 unsigned Reg = MO.getReg();
1806 if (Reg == IncomingReg) {
1809 // The register is already marked kill.
1811 if (isPhysReg && isRegTiedToDefOperand(i))
1812 // Two-address uses of physregs must not be marked kill.
1817 } else if (hasAliases && MO.isKill() &&
1818 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1819 // A super-register kill already exists.
1820 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1822 if (RegInfo->isSubRegister(IncomingReg, Reg))
1823 DeadOps.push_back(i);
1827 // Trim unneeded kill operands.
1828 while (!DeadOps.empty()) {
1829 unsigned OpIdx = DeadOps.back();
1830 if (getOperand(OpIdx).isImplicit() &&
1831 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1832 RemoveOperand(OpIdx);
1834 getOperand(OpIdx).setIsKill(false);
1838 // If not found, this means an alias of one of the operands is killed. Add a
1839 // new implicit operand if required.
1840 if (!Found && AddIfNotFound) {
1841 addOperand(MachineOperand::CreateReg(IncomingReg,
1850 void MachineInstr::clearRegisterKills(unsigned Reg,
1851 const TargetRegisterInfo *RegInfo) {
1852 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1854 for (MachineOperand &MO : operands()) {
1855 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1857 unsigned OpReg = MO.getReg();
1858 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1859 MO.setIsKill(false);
1863 bool MachineInstr::addRegisterDead(unsigned Reg,
1864 const TargetRegisterInfo *RegInfo,
1865 bool AddIfNotFound) {
1866 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1867 bool hasAliases = isPhysReg &&
1868 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1870 SmallVector<unsigned,4> DeadOps;
1871 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1872 MachineOperand &MO = getOperand(i);
1873 if (!MO.isReg() || !MO.isDef())
1875 unsigned MOReg = MO.getReg();
1882 } else if (hasAliases && MO.isDead() &&
1883 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1884 // There exists a super-register that's marked dead.
1885 if (RegInfo->isSuperRegister(Reg, MOReg))
1887 if (RegInfo->isSubRegister(Reg, MOReg))
1888 DeadOps.push_back(i);
1892 // Trim unneeded dead operands.
1893 while (!DeadOps.empty()) {
1894 unsigned OpIdx = DeadOps.back();
1895 if (getOperand(OpIdx).isImplicit() &&
1896 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1897 RemoveOperand(OpIdx);
1899 getOperand(OpIdx).setIsDead(false);
1903 // If not found, this means an alias of one of the operands is dead. Add a
1904 // new implicit operand if required.
1905 if (Found || !AddIfNotFound)
1908 addOperand(MachineOperand::CreateReg(Reg,
1916 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1917 for (MachineOperand &MO : operands()) {
1918 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1920 MO.setIsDead(false);
1924 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1925 for (MachineOperand &MO : operands()) {
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1928 MO.setIsUndef(IsUndef);
1932 void MachineInstr::addRegisterDefined(unsigned Reg,
1933 const TargetRegisterInfo *RegInfo) {
1934 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1935 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1939 for (const MachineOperand &MO : operands()) {
1940 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1941 MO.getSubReg() == 0)
1945 addOperand(MachineOperand::CreateReg(Reg,
1950 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1951 const TargetRegisterInfo &TRI) {
1952 bool HasRegMask = false;
1953 for (MachineOperand &MO : operands()) {
1954 if (MO.isRegMask()) {
1958 if (!MO.isReg() || !MO.isDef()) continue;
1959 unsigned Reg = MO.getReg();
1960 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1961 // If there are no uses, including partial uses, the def is dead.
1962 if (llvm::none_of(UsedRegs,
1963 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1967 // This is a call with a register mask operand.
1968 // Mask clobbers are always dead, so add defs for the non-dead defines.
1970 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1972 addRegisterDefined(*I, &TRI);
1976 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1977 // Build up a buffer of hash code components.
1978 SmallVector<size_t, 8> HashComponents;
1979 HashComponents.reserve(MI->getNumOperands() + 1);
1980 HashComponents.push_back(MI->getOpcode());
1981 for (const MachineOperand &MO : MI->operands()) {
1982 if (MO.isReg() && MO.isDef() &&
1983 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1984 continue; // Skip virtual register defs.
1986 HashComponents.push_back(hash_value(MO));
1988 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1991 void MachineInstr::emitError(StringRef Msg) const {
1992 // Find the source location cookie.
1993 unsigned LocCookie = 0;
1994 const MDNode *LocMD = nullptr;
1995 for (unsigned i = getNumOperands(); i != 0; --i) {
1996 if (getOperand(i-1).isMetadata() &&
1997 (LocMD = getOperand(i-1).getMetadata()) &&
1998 LocMD->getNumOperands() != 0) {
1999 if (const ConstantInt *CI =
2000 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2001 LocCookie = CI->getZExtValue();
2007 if (const MachineBasicBlock *MBB = getParent())
2008 if (const MachineFunction *MF = MBB->getParent())
2009 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2010 report_fatal_error(Msg);
2013 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2014 const MCInstrDesc &MCID, bool IsIndirect,
2015 unsigned Reg, const MDNode *Variable,
2016 const MDNode *Expr) {
2017 assert(isa<DILocalVariable>(Variable) && "not a variable");
2018 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2019 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2020 "Expected inlined-at fields to agree");
2021 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2025 MIB.addReg(0U, RegState::Debug);
2026 return MIB.addMetadata(Variable).addMetadata(Expr);
2029 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2030 const MCInstrDesc &MCID, bool IsIndirect,
2031 MachineOperand &MO, const MDNode *Variable,
2032 const MDNode *Expr) {
2033 assert(isa<DILocalVariable>(Variable) && "not a variable");
2034 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2035 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2036 "Expected inlined-at fields to agree");
2038 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2040 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2044 MIB.addReg(0U, RegState::Debug);
2045 return MIB.addMetadata(Variable).addMetadata(Expr);
2048 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2049 MachineBasicBlock::iterator I,
2050 const DebugLoc &DL, const MCInstrDesc &MCID,
2051 bool IsIndirect, unsigned Reg,
2052 const MDNode *Variable, const MDNode *Expr) {
2053 MachineFunction &MF = *BB.getParent();
2054 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2056 return MachineInstrBuilder(MF, MI);
2059 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2060 MachineBasicBlock::iterator I,
2061 const DebugLoc &DL, const MCInstrDesc &MCID,
2062 bool IsIndirect, MachineOperand &MO,
2063 const MDNode *Variable, const MDNode *Expr) {
2064 MachineFunction &MF = *BB.getParent();
2065 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2067 return MachineInstrBuilder(MF, *MI);
2070 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2071 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2072 static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2073 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2074 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2075 "Expected inlined-at fields to agree");
2077 const DIExpression *Expr = MI.getDebugExpression();
2078 if (MI.isIndirectDebugValue()) {
2079 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
2080 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2085 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2086 MachineBasicBlock::iterator I,
2087 const MachineInstr &Orig,
2089 const DIExpression *Expr = computeExprForSpill(Orig);
2090 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2091 .addFrameIndex(FrameIndex)
2093 .addMetadata(Orig.getDebugVariable())
2097 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2098 const DIExpression *Expr = computeExprForSpill(Orig);
2099 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2100 Orig.getOperand(1).ChangeToImmediate(0U);
2101 Orig.getOperand(3).setMetadata(Expr);
2104 void MachineInstr::collectDebugValues(
2105 SmallVectorImpl<MachineInstr *> &DbgValues) {
2106 MachineInstr &MI = *this;
2107 if (!MI.getOperand(0).isReg())
2110 MachineBasicBlock::iterator DI = MI; ++DI;
2111 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2113 if (!DI->isDebugValue())
2115 if (DI->getOperand(0).isReg() &&
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2117 DbgValues.push_back(&*DI);
2121 void MachineInstr::changeDebugValuesDefReg(unsigned Reg) {
2122 // Collect matching debug values.
2123 SmallVector<MachineInstr *, 2> DbgValues;
2124 collectDebugValues(DbgValues);
2126 // Propagate Reg to debug value instructions.
2127 for (auto *DBI : DbgValues)
2128 DBI->getOperand(0).setReg(Reg);
2131 using MMOList = SmallVector<const MachineMemOperand *, 2>;
2133 static unsigned getSpillSlotSize(MMOList &Accesses,
2134 const MachineFrameInfo &MFI) {
2136 for (auto A : Accesses)
2137 if (MFI.isSpillSlotObjectIndex(
2138 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2140 Size += A->getSize();
2145 MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2147 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2148 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2149 if (MFI.isSpillSlotObjectIndex(FI))
2150 return (*memoperands_begin())->getSize();
2156 MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2158 if (TII->hasStoreToStackSlot(*this, Accesses))
2159 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2164 MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2166 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2167 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2168 if (MFI.isSpillSlotObjectIndex(FI))
2169 return (*memoperands_begin())->getSize();
2175 MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2177 if (TII->hasLoadFromStackSlot(*this, Accesses))
2178 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());